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ARM: dts: add Ebang EBAZ4205 device tree

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The Ebang EBAZ4205 is a simple board based on the Xilinx Zynq-7000 SoC.
Its features are:
 - one serial port
 - 256 MB RAM
 - 128 MB NAND flash
 - SDcard slot
 - IP101GA 10/100 Mbit Ethernet PHY (connected to PL IOs)
 - two LEDs (connected to PL IOs)
 - one Push Button (connect to PL IOs)
 - (optional) RTC
 - (optional) Input voltage supervisor

The NAND flash is not supported in mainline linux yet. Unfortunately,
the PHY is connected via the PL, thus for working ethernet the FPGA has
to be configured. Also, depending on the board variant, the PHY has no
external crystal and its clock needs to be driven by the PL. FCLK3 is
used for this and is kept enabled.

Signed-off-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20210120194033.26970-4-michael@walle.cc
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Michael Walle 2021-01-20 20:40:33 +01:00 committed by Michal Simek
parent 12e6d3eb8e
commit 00c2747814
2 changed files with 110 additions and 0 deletions
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1
arch/arm/boot/dts/Makefile
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@ -1307,6 +1307,7 @@ dtb-$(CONFIG_ARCH_VT8500) += \
wm8850-w70v2.dtb
dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-cc108.dtb \
zynq-ebaz4205.dtb \
zynq-microzed.dtb \
zynq-parallella.dtb \
zynq-zc702.dtb \

109
arch/arm/boot/dts/zynq-ebaz4205.dts Normal file
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@ -0,0 +1,109 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Michael Walle <michael@walle.cc>
*/
/dts-v1/;
/include/ "zynq-7000.dtsi"
/ {
model = "Ebang EBAZ4205";
compatible = "ebang,ebaz4205", "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
serial0 = &uart1;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x10000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&clkc {
ps-clk-frequency = <33333333>;
fclk-enable = <8>;
};
&gem0 {
status = "okay";
phy-mode = "mii";
phy-handle = <&phy>;
/* PHY clock */
assigned-clocks = <&clkc 18>;
assigned-clock-rates = <25000000>;
phy: ethernet-phy@0 {
reg = <0>;
};
};
&pinctrl0 {
pinctrl_sdhci0_default: sdhci0-default {
mux {
groups = "sdio0_2_grp";
function = "sdio0";
};
conf {
groups = "sdio0_2_grp";
io-standard = <3>;
slew-rate = <0>;
bias-disable;
};
mux-cd {
groups = "gpio0_34_grp";
function = "sdio0_cd";
};
conf-cd {
groups = "gpio0_34_grp";
io-standard = <3>;
slew-rate = <0>;
bias-high-impedance;
bias-pull-up;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_4_grp";
function = "uart1";
};
conf {
groups = "uart1_4_grp";
io-standard = <3>;
slew-rate = <0>;
};
conf-rx {
pins = "MIO25";
bias-high-impedance;
};
conf-tx {
pins = "MIO24";
bias-disable;
};
};
};
&sdhci0 {
status = "okay";
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0_default>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};