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spi: spi-mem: Allow specifying the byte order in Octal DTR mode

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There are NOR flashes (Macronix) that swap the bytes on a 16-bit
boundary when configured in Octal DTR mode. The byte order of
16-bit words is swapped when read or written in Octal Double
Transfer Rate (DTR) mode compared to Single Transfer Rate (STR)
modes. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses
8D-8D-8D SPI mode for reading, it will read back D1 D0 D3 D2.
Swapping the bytes may introduce some endianness problems. It can
affect the boot sequence if the entire boot sequence is not handled
in either 8D-8D-8D mode or 1-1-1 mode. Therefore, it is necessary
to swap the bytes back to ensure the same byte order as in STR modes.
Fortunately there are controllers that could swap the bytes back at
runtime, addressing the flash's endianness requirements. Provide a
way for the upper layers to specify the byte order in Octal DTR mode.

Merge Tudor's patch and add modifications for suiting newer version
of Linux kernel.

Suggested-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
Signed-off-by: AlvinZhou <alvinzhou@mxic.com.tw>
Acked-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20240926141956.2386374-3-alvinzhou.tw@gmail.com
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
This commit is contained in:
Tudor Ambarus 2024-09-26 22:19:52 +08:00
parent 9852d85ec9
commit 030ace430a
No known key found for this signature in database
GPG Key ID: 4B554F47A58D14E9
2 changed files with 10 additions and 1 deletions
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3
drivers/spi/spi-mem.c
View File

@ -172,6 +172,9 @@ bool spi_mem_default_supports_op(struct spi_mem *mem,
if (!spi_mem_controller_is_capable(ctlr, dtr)) if (!spi_mem_controller_is_capable(ctlr, dtr))
return false; return false;
if (op->data.swap16 && !spi_mem_controller_is_capable(ctlr, swap16))
return false;
if (op->cmd.nbytes != 2) if (op->cmd.nbytes != 2)
return false; return false;
} else { } else {

8
include/linux/spi/spi-mem.h
View File

@ -90,6 +90,8 @@ enum spi_mem_data_dir {
* @data.buswidth: number of IO lanes used to send/receive the data * @data.buswidth: number of IO lanes used to send/receive the data
* @data.dtr: whether the data should be sent in DTR mode or not * @data.dtr: whether the data should be sent in DTR mode or not
* @data.ecc: whether error correction is required or not * @data.ecc: whether error correction is required or not
* @data.swap16: whether the byte order of 16-bit words is swapped when read
* or written in Octal DTR mode compared to STR mode.
* @data.dir: direction of the transfer * @data.dir: direction of the transfer
* @data.nbytes: number of data bytes to send/receive. Can be zero if the * @data.nbytes: number of data bytes to send/receive. Can be zero if the
* operation does not involve transferring data * operation does not involve transferring data
@ -124,7 +126,8 @@ struct spi_mem_op {
u8 buswidth; u8 buswidth;
u8 dtr : 1; u8 dtr : 1;
u8 ecc : 1; u8 ecc : 1;
u8 __pad : 6; u8 swap16 : 1;
u8 __pad : 5;
enum spi_mem_data_dir dir; enum spi_mem_data_dir dir;
unsigned int nbytes; unsigned int nbytes;
union { union {
@ -297,10 +300,13 @@ struct spi_controller_mem_ops {
* struct spi_controller_mem_caps - SPI memory controller capabilities * struct spi_controller_mem_caps - SPI memory controller capabilities
* @dtr: Supports DTR operations * @dtr: Supports DTR operations
* @ecc: Supports operations with error correction * @ecc: Supports operations with error correction
* @swap16: Supports swapping bytes on a 16 bit boundary when configured in
* Octal DTR
*/ */
struct spi_controller_mem_caps { struct spi_controller_mem_caps {
bool dtr; bool dtr;
bool ecc; bool ecc;
bool swap16;
}; };
#define spi_mem_controller_is_capable(ctlr, cap) \ #define spi_mem_controller_is_capable(ctlr, cap) \