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Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git

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This commit is contained in:
Stephen Rothwell 2024-12-20 10:41:22 +11:00
commit 1c96fc4c1d
29 changed files with 11888 additions and 79 deletions
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3
Documentation/devicetree/bindings/arm/qcom-soc.yaml
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@ -23,7 +23,7 @@ description: |
select:
properties:
compatible:
pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+.*$"
pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1e)[0-9]+.*$"
required:
- compatible
@ -32,6 +32,7 @@ properties:
oneOf:
# Preferred naming style for compatibles of SoC components:
- pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1e)[0-9]+(pro)?-.*$"
- pattern: "^qcom,sar[0-9]+[a-z]?-.*$"
- pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$"
# Legacy namings - variations of existing patterns/compatibles are OK,

41
Documentation/devicetree/bindings/arm/qcom.yaml
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@ -19,29 +19,41 @@ description: |
apq8016
apq8026
apq8064
apq8074
apq8084
apq8094
apq8096
ipq4018
ipq4019
ipq5018
ipq5332
ipq5424
ipq6018
ipq8064
ipq8074
ipq9574
mdm9615
msm8226
msm8660
msm8916
msm8926
msm8929
msm8939
msm8953
msm8956
msm8960
msm8974
msm8974pro
msm8976
msm8992
msm8994
msm8996
msm8996pro
msm8998
qcs404
qcs615
qcs8300
qcs8550
qcm2290
qcm6490
@ -53,6 +65,7 @@ description: |
sa8155p
sa8540p
sa8775p
sar2130p
sc7180
sc7280
sc8180x
@ -84,6 +97,7 @@ description: |
sm8450
sm8550
sm8650
x1e78100
x1e80100
There are many devices in the list below that run the standard ChromeOS
@ -352,6 +366,11 @@ properties:
- qcom,ipq5332-ap-mi01.9
- const: qcom,ipq5332
- items:
- enum:
- qcom,ipq5424-rdp466
- const: qcom,ipq5424
- items:
- enum:
- mikrotik,rb3011
@ -408,6 +427,12 @@ properties:
- qcom,qru1000-idp
- const: qcom,qru1000
- description: Qualcomm AR2 Gen1 platform
items:
- enum:
- qcom,qar2130p
- const: qcom,sar2130p
- items:
- enum:
- acer,aspire1
@ -898,6 +923,16 @@ properties:
- const: qcom,qcs404-evb
- const: qcom,qcs404
- items:
- enum:
- qcom,qcs8300-ride
- const: qcom,qcs8300
- items:
- enum:
- qcom,qcs615-ride
- const: qcom,qcs615
- items:
- enum:
- qcom,sa8155p-adp
@ -1064,6 +1099,12 @@ properties:
- qcom,sm8650-qrd
- const: qcom,sm8650
- items:
- enum:
- qcom,x1e001de-devkit
- const: qcom,x1e001de
- const: qcom,x1e80100
- items:
- enum:
- lenovo,thinkpad-t14s

59
Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml Normal file
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@ -0,0 +1,59 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on QCS615
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on QCS615.
See also: include/dt-bindings/clock/qcom,qcs615-gcc.h
properties:
compatible:
const: qcom,qcs615-gcc
clocks:
items:
- description: Board XO source
- description: Board active XO source
- description: Sleep clock source
clock-names:
items:
- const: bi_tcxo
- const: bi_tcxo_ao
- const: sleep_clk
required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,qcs615-gcc";
reg = <0x00100000 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...

27
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
View File

@ -18,12 +18,6 @@ description: |
include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h
properties:
clocks: true
clock-names: true
reg: true
compatible:
enum:
- qcom,sc7280-lpassaoncc
@ -31,12 +25,24 @@ properties:
- qcom,sc7280-lpasscorecc
- qcom,sc7280-lpasshm
power-domains:
maxItems: 1
reg:
minItems: 1
maxItems: 2
clocks:
minItems: 1
maxItems: 3
clock-names:
minItems: 1
maxItems: 3
'#clock-cells':
const: 1
power-domains:
maxItems: 1
'#power-domain-cells':
const: 1
@ -57,8 +63,6 @@ required:
- '#clock-cells'
- '#power-domain-cells'
additionalProperties: false
allOf:
- if:
properties:
@ -125,6 +129,9 @@ allOf:
reg:
maxItems: 1
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>

1
Documentation/devicetree/bindings/firmware/qcom,scm.yaml
View File

@ -42,6 +42,7 @@ properties:
- qcom,scm-msm8996
- qcom,scm-msm8998
- qcom,scm-qcm2290
- qcom,scm-qcs615
- qcom,scm-qcs8300
- qcom,scm-qdu1000
- qcom,scm-sa8255p

1
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
View File

@ -25,6 +25,7 @@ properties:
compatible:
items:
- enum:
- qcom,qcs615-aoss-qmp
- qcom,qcs8300-aoss-qmp
- qcom,qdu1000-aoss-qmp
- qcom,sa8255p-aoss-qmp

6
arch/arm64/boot/dts/qcom/Makefile
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@ -3,6 +3,8 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
apq8016-sbc-usb-host-dtbs := apq8016-sbc.dtb apq8016-sbc-usb-host.dtbo
dtb-$(CONFIG_ARCH_QCOM) += sar2130p-qar2130p.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-usb-host.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-d3-camera-mezzanine.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8016-schneider-hmibsc.dtb
@ -16,6 +18,7 @@ dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp441.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp442.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp468.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-rdp474.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5424-rdp466.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
@ -110,7 +113,9 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs615-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8300-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs9100-ride-r3.dtb
@ -278,6 +283,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk-display-card.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e001de-devkit.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e78100-lenovo-thinkpad-t14s.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-asus-vivobook-s15.dtb
dtb-$(CONFIG_ARCH_QCOM) += x1e80100-crd.dtb

59
arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts Normal file
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@ -0,0 +1,59 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* IPQ5424 RDP466 board device tree source
*
* Copyright (c) 2024 The Linux Foundation. All rights reserved.
*/
/dts-v1/;
#include "ipq5424.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ5424 RDP466";
compatible = "qcom,ipq5424-rdp466", "qcom,ipq5424";
aliases {
serial0 = &uart1;
};
};
&sleep_clk {
clock-frequency = <32000>;
};
&tlmm {
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio5";
function = "sdc_clk";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "gpio4";
function = "sdc_cmd";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "sdc_data";
drive-strength = <8>;
bias-pull-up;
};
};
};
&uart1 {
pinctrl-0 = <&uart1_pins>;
pinctrl-names = "default";
status = "okay";
};
&xo_board {
clock-frequency = <24000000>;
};

305
arch/arm64/boot/dts/qcom/ipq5424.dtsi Normal file
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@ -0,0 +1,305 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* IPQ5424 device tree source
*
* Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
#include <dt-bindings/gpio/gpio.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&intc>;
clocks {
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
xo_board: xo-board-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&l2_0>;
l2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
l3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
cpu1: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x100>;
next-level-cache = <&l2_100>;
l2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu2: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x200>;
next-level-cache = <&l2_200>;
l2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu3: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a55";
enable-method = "psci";
reg = <0x300>;
next-level-cache = <&l2_300>;
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0x0 0x80000000 0x0 0x0>;
};
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
pmu-dsu {
compatible = "arm,dsu-pmu";
interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
tz@8a600000 {
reg = <0x0 0x8a600000 0x0 0x200000>;
no-map;
};
smem@8a800000 {
compatible = "qcom,smem";
reg = <0x0 0x8a800000 0x0 0x32000>;
no-map;
hwlocks = <&tcsr_mutex 3>;
};
};
soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0 0x10 0>;
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5424-tlmm";
reg = <0 0x01000000 0 0x300000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 50>;
interrupt-controller;
#interrupt-cells = <2>;
uart1_pins: uart1-state {
pins = "gpio43", "gpio44";
function = "uart1";
drive-strength = <8>;
bias-pull-up;
};
};
gcc: clock-controller@1800000 {
compatible = "qcom,ipq5424-gcc";
reg = <0 0x01800000 0 0x40000>;
clocks = <&xo_board>,
<&sleep_clk>,
<0>,
<0>,
<0>,
<0>,
<0>;
#clock-cells = <1>;
#reset-cells = <1>;
#interconnect-cells = <1>;
};
tcsr_mutex: hwlock@1905000 {
compatible = "qcom,tcsr-mutex";
reg = <0 0x01905000 0 0x20000>;
#hwlock-cells = <1>;
};
qupv3: geniqup@1ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x01ac0000 0 0x2000>;
ranges;
clocks = <&gcc GCC_QUPV3_AHB_MST_CLK>,
<&gcc GCC_QUPV3_AHB_SLV_CLK>;
clock-names = "m-ahb", "s-ahb";
#address-cells = <2>;
#size-cells = <2>;
uart1: serial@1a84000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x01a84000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_UART1_CLK>;
clock-names = "se";
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
};
};
sdhc: mmc@7804000 {
compatible = "qcom,ipq5424-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x07804000 0 0x1000>, <0 0x07805000 0 0x1000>;
reg-names = "hc", "cqhci";
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board>;
clock-names = "iface", "core", "xo";
status = "disabled";
};
intc: interrupt-controller@f200000 {
compatible = "arm,gic-v3";
reg = <0 0xf200000 0 0x10000>, /* GICD */
<0 0xf240000 0 0x80000>; /* GICR * 4 regions */
#interrupt-cells = <0x3>;
interrupt-controller;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
mbi-ranges = <672 128>;
msi-controller;
};
timer@f420000 {
compatible = "arm,armv7-timer-mem";
reg = <0 0xf420000 0 0x1000>;
ranges = <0 0 0 0x10000000>;
#address-cells = <1>;
#size-cells = <1>;
frame@f421000 {
reg = <0xf421000 0x1000>,
<0xf422000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <0>;
};
frame@f423000 {
reg = <0xf423000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <1>;
status = "disabled";
};
frame@f425000 {
reg = <0xf425000 0x1000>,
<0xf426000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <2>;
status = "disabled";
};
frame@f427000 {
reg = <0xf427000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <3>;
status = "disabled";
};
frame@f429000 {
reg = <0xf429000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <4>;
status = "disabled";
};
frame@f42b000 {
reg = <0xf42b000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <5>;
status = "disabled";
};
frame@f42d000 {
reg = <0xf42d000 0x1000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <6>;
status = "disabled";
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
};
};

242
arch/arm64/boot/dts/qcom/qcs615-ride.dts Normal file
View File

@ -0,0 +1,242 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "qcs615.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS615 Ride";
compatible = "qcom,qcs615-ride", "qcom,qcs615";
chassis-type = "embedded";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
clocks {
sleep_clk: sleep-clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
#clock-cells = <0>;
};
xo_board_clk: xo-board-clk {
compatible = "fixed-clock";
clock-frequency = <38400000>;
#clock-cells = <0>;
};
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pm8150-rpmh-regulators";
qcom,pmic-id = "a";
vreg_s3a: smps3 {
regulator-name = "vreg_s3a";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <650000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s4a: smps4 {
regulator-name = "vreg_s4a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1829000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s5a: smps5 {
regulator-name = "vreg_s5a";
regulator-min-microvolt = <1896000>;
regulator-max-microvolt = <2040000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s6a: smps6 {
regulator-name = "vreg_s6a";
regulator-min-microvolt = <1304000>;
regulator-max-microvolt = <1404000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1a: ldo1 {
regulator-name = "vreg_l1a";
regulator-min-microvolt = <488000>;
regulator-max-microvolt = <852000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2a: ldo2 {
regulator-name = "vreg_l2a";
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <3100000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3a: ldo3 {
regulator-name = "vreg_l3a";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1248000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5a: ldo5 {
regulator-name = "vreg_l5a";
regulator-min-microvolt = <875000>;
regulator-max-microvolt = <975000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a: ldo7 {
regulator-name = "vreg_l7a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1900000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8a: ldo8 {
regulator-name = "vreg_l8a";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1350000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10a: ldo10 {
regulator-name = "vreg_l10a";
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11a: ldo11 {
regulator-name = "vreg_l11a";
regulator-min-microvolt = <1232000>;
regulator-max-microvolt = <1260000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12a: ldo12 {
regulator-name = "vreg_l12a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1890000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13a: ldo13 {
regulator-name = "vreg_l13a";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3230000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l15a: ldo15 {
regulator-name = "vreg_l15a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l16a: ldo16 {
regulator-name = "vreg_l16a";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l17a: ldo17 {
regulator-name = "vreg_l17a";
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
};
&gcc {
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
};
&qupv3_id_0 {
status = "okay";
};
&rpmhcc {
clocks = <&xo_board_clk>;
};
&uart0 {
status = "okay";
};
&usb_1_hsphy {
vdd-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l12a>;
vdda-phy-dpdm-supply = <&vreg_l13a>;
status = "okay";
};
&usb_qmpphy {
vdda-phy-supply = <&vreg_l5a>;
vdda-pll-supply = <&vreg_l12a>;
status = "okay";
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "peripheral";
};
&watchdog {
clocks = <&sleep_clk>;
};

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arch/arm64/boot/dts/qcom/qcs615.dtsi Normal file
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arch/arm64/boot/dts/qcom/qcs8300-ride.dts Normal file
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@ -0,0 +1,235 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "qcs8300.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QCS8300 Ride";
compatible = "qcom,qcs8300-ride", "qcom,qcs8300";
chassis-type = "embedded";
aliases {
serial0 = &uart7;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "a";
vreg_s4a: smps4 {
regulator-name = "vreg_s4a";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s9a: smps9 {
regulator-name = "vreg_s9a";
regulator-min-microvolt = <1352000>;
regulator-max-microvolt = <1352000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3a: ldo3 {
regulator-name = "vreg_l3a";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4a: ldo4 {
regulator-name = "vreg_l4a";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5a: ldo5 {
regulator-name = "vreg_l5a";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6a: ldo6 {
regulator-name = "vreg_l6a";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a: ldo7 {
regulator-name = "vreg_l7a";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8a: ldo8 {
regulator-name = "vreg_l8a";
regulator-min-microvolt = <2504000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9a: ldo9 {
regulator-name = "vreg_l9a";
regulator-min-microvolt = <2970000>;
regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
regulators-1 {
compatible = "qcom,pmm8654au-rpmh-regulators";
qcom,pmic-id = "c";
vreg_s5c: smps5 {
regulator-name = "vreg_s5c";
regulator-min-microvolt = <1104000>;
regulator-max-microvolt = <1104000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1c: ldo1 {
regulator-name = "vreg_l1c";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <500000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c: ldo2 {
regulator-name = "vreg_l2c";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c: ldo4 {
regulator-name = "vreg_l4c";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6c: ldo6 {
regulator-name = "vreg_l6c";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c: ldo7 {
regulator-name = "vreg_l7c";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8c: ldo8 {
regulator-name = "vreg_l8c";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9c: ldo9 {
regulator-name = "vreg_l9c";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-allow-set-load;
regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
RPMH_REGULATOR_MODE_HPM>;
};
};
};
&qupv3_id_0 {
status = "okay";
};
&remoteproc_adsp {
firmware-name = "qcom/qcs8300/adsp.mbn";
status = "okay";
};
&remoteproc_cdsp {
firmware-name = "qcom/qcs8300/cdsp0.mbn";
status = "okay";
};
&remoteproc_gpdsp {
firmware-name = "qcom/qcs8300/gpdsp0.mbn";
status = "okay";
};
&uart7 {
status = "okay";
};
&ufs_mem_hc {
reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l8a>;
vcc-max-microamp = <1100000>;
vccq-supply = <&vreg_l4c>;
vccq-max-microamp = <1200000>;
status = "okay";
};
&ufs_mem_phy {
vdda-phy-supply = <&vreg_l4a>;
vdda-pll-supply = <&vreg_l5a>;
status = "okay";
};

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arch/arm64/boot/dts/qcom/qcs8300.dtsi Normal file
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4
arch/arm64/boot/dts/qcom/sa8775p.dtsi
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@ -6092,7 +6092,7 @@
<0x0 0x40000000 0x0 0xf20>,
<0x0 0x40000f20 0x0 0xa8>,
<0x0 0x40001000 0x0 0x4000>,
<0x0 0x40200000 0x0 0x100000>,
<0x0 0x40200000 0x0 0x1fe00000>,
<0x0 0x01c03000 0x0 0x1000>,
<0x0 0x40005000 0x0 0x2000>;
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
@ -6250,7 +6250,7 @@
<0x0 0x60000000 0x0 0xf20>,
<0x0 0x60000f20 0x0 0xa8>,
<0x0 0x60001000 0x0 0x4000>,
<0x0 0x60200000 0x0 0x100000>,
<0x0 0x60200000 0x0 0x1fe00000>,
<0x0 0x01c13000 0x0 0x1000>,
<0x0 0x60005000 0x0 0x2000>;
reg-names = "parf", "dbi", "elbi", "atu", "addr_space",

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arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts Normal file
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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2024, Linaro Limited
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sar2130p.dtsi"
#include "pm8150.dtsi"
/ {
model = "Qualcomm Snapdragon AR2 Gen1 Smart Viewer Development Kit";
compatible = "qcom,qar2130p", "qcom,sar2130p";
chassis-type = "embedded";
aliases {
serial0 = &uart11;
serial1 = &uart7;
i2c0 = &i2c8;
i2c1 = &i2c10;
mmc1 = &sdhc_1;
spi0 = &spi0;
};
chosen {
stdout-path = "serial0:115200n8";
};
vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
};
/* pm3003a on I2C0, should not be controlled */
vreg_ext_1p3: regulator-ext-1p3 {
compatible = "regulator-fixed";
regulator-name = "vph_ext_1p3";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
vin-supply = <&vph_pwr>;
};
/* EBI rail, used as LDO input, can not be part of PMIC config */
vreg_s10a_0p89: regulator-s10a-0p89 {
compatible = "regulator-fixed";
regulator-name = "vph_s10a_0p89";
regulator-min-microvolt = <890000>;
regulator-max-microvolt = <890000>;
regulator-always-on;
vin-supply = <&vph_pwr>;
};
thermal-zones {
sar2130p-thermal {
thermal-sensors = <&pm8150_adc_tm 1>;
trips {
active-config0 {
temperature = <100000>;
hysteresis = <1000>;
type = "critical";
};
};
};
wifi-thermal {
thermal-sensors = <&pm8150_adc_tm 2>;
trips {
active-config0 {
temperature = <52000>;
hysteresis = <4000>;
type = "passive";
};
};
};
xo-thermal {
thermal-sensors = <&pm8150_adc_tm 0>;
trips {
active-config0 {
temperature = <50000>;
hysteresis = <4000>;
type = "passive";
};
};
};
};
wcn7850-pmu {
compatible = "qcom,wcn7850-pmu";
pinctrl-0 = <&wlan_en_state>, <&bt_en_state>;
pinctrl-names = "default";
wlan-enable-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>;
bt-enable-gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
vdd-supply = <&vreg_s4a_0p95>;
vddio-supply = <&vreg_l15a_1p8>;
vddaon-supply = <&vreg_s4a_0p95>;
vdddig-supply = <&vreg_s4a_0p95>;
vddrfa1p2-supply = <&vreg_s4a_0p95>;
vddrfa1p8-supply = <&vreg_s5a_1p88>;
regulators {
vreg_pmu_rfa_cmn: ldo0 {
regulator-name = "vreg_pmu_rfa_cmn";
};
vreg_pmu_aon_0p59: ldo1 {
regulator-name = "vreg_pmu_aon_0p59";
};
vreg_pmu_wlcx_0p8: ldo2 {
regulator-name = "vreg_pmu_wlcx_0p8";
};
vreg_pmu_wlmx_0p85: ldo3 {
regulator-name = "vreg_pmu_wlmx_0p85";
};
vreg_pmu_btcmx_0p85: ldo4 {
regulator-name = "vreg_pmu_btcmx_0p85";
};
vreg_pmu_rfa_0p8: ldo5 {
regulator-name = "vreg_pmu_rfa_0p8";
};
vreg_pmu_rfa_1p2: ldo6 {
regulator-name = "vreg_pmu_rfa_1p2";
};
vreg_pmu_rfa_1p8: ldo7 {
regulator-name = "vreg_pmu_rfa_1p8";
};
vreg_pmu_pcie_0p9: ldo8 {
regulator-name = "vreg_pmu_pcie_0p9";
};
vreg_pmu_pcie_1p8: ldo9 {
regulator-name = "vreg_pmu_pcie_1p8";
};
};
};
};
&apps_rsc {
regulators-0 {
compatible = "qcom,pm8150-rpmh-regulators";
qcom,pmic-id = "a";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-s9-supply = <&vph_pwr>;
vdd-s10-supply = <&vph_pwr>;
vdd-l1-l8-l11-supply = <&vreg_s4a_0p95>;
vdd-l3-l4-l5-l18-supply = <&vreg_ext_1p3>;
vdd-l6-l9-supply = <&vreg_s10a_0p89>;
vdd-l7-l12-l14-l15-supply = <&vreg_s5a_1p88>;
vreg_s4a_0p95: smps6 {
regulator-name = "vreg_s4a_0p95";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1170000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s5a_1p88: smps5 {
regulator-name = "vreg_s5a_1p88";
regulator-min-microvolt = <1856000>;
regulator-max-microvolt = <2040000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l1a_0p91: ldo1 {
regulator-name = "vreg_l1a_0p91";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2a_3p1: ldo2 {
regulator-name = "vreg_l2a_3p1";
regulator-min-microvolt = <3080000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3a_1p2: ldo3 {
regulator-name = "vreg_l3a_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
/* ldo4 1.26 - system ? */
vreg_l5a_1p13: ldo5 {
regulator-name = "vreg_l5a_1p13";
regulator-min-microvolt = <1128000>;
regulator-max-microvolt = <1170000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6a_0p6: ldo6 {
regulator-name = "vreg_l6a_0p6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <650000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a_1p8: ldo7 {
regulator-name = "vreg_l7a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8a_0p88: ldo8 {
regulator-name = "vreg_l8a_0p88";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
/* ldo9 - LCX */
vreg_l10a_2p95: ldo10 {
regulator-name = "vreg_l10a_2p95";
regulator-min-microvolt = <2952000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
/* ldo11 - LMX */
vreg_l12a_1p8: ldo12 {
regulator-name = "vreg_l12a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
/* no ldo13 */
vreg_l14a_1p8: ldo14 {
regulator-name = "vreg_l14a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l15a_1p8: ldo15 {
regulator-name = "vreg_l15a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
/* no ldo16 - system */
vreg_l17a_3p26: ldo17 {
regulator-name = "vreg_l17a_3p26";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l18a_1p2: ldo18 {
regulator-name = "vreg_l18a_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
};
&gpi_dma0 {
status = "okay";
};
&gpi_dma1 {
status = "okay";
};
&gpu {
status = "okay";
};
&gpu_zap_shader {
firmware-name = "qcom/sar2130p/a620_zap.mbn";
};
&pon_pwrkey {
status = "okay";
};
&pon_resin {
linux,code = <KEY_VOLUMEDOWN>;
status = "okay";
};
&qupv3_id_0 {
status = "okay";
};
&qupv3_id_1 {
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
status = "okay";
};
&i2c8 {
clock-frequency = <400000>;
status = "okay";
ptn3222: redriver@4f {
compatible = "nxp,ptn3222";
reg = <0x4f>;
reset-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>;
vdd3v3-supply = <&vreg_l2a_3p1>;
vdd1v8-supply = <&vreg_l15a_1p8>;
#phy-cells = <0>;
};
};
&i2c10 {
clock-frequency = <400000>;
status = "okay";
};
&pcie0 {
perst-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_default_state>;
pinctrl-names = "default";
status = "okay";
};
&pcieport0 {
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
vddaon-supply = <&vreg_pmu_aon_0p59>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
vddpcie0p9-supply = <&vreg_pmu_pcie_0p9>;
vddpcie1p8-supply = <&vreg_pmu_pcie_1p8>;
};
};
&pcie0_phy {
vdda-phy-supply = <&vreg_l8a_0p88>;
vdda-pll-supply = <&vreg_l3a_1p2>;
status = "okay";
};
&pm8150_adc {
channel@4c {
reg = <ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
label = "xo_therm";
};
channel@4d {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "skin_therm";
};
channel@4e {
/* msm-5.10 uses ADC5_AMUX_THM2 / 0x0e, although there is a pullup */
reg = <ADC5_AMUX_THM2_100K_PU>;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
label = "wifi_therm";
};
};
&pm8150_adc_tm {
status = "okay";
xo-therm@0 {
reg = <0>;
io-channels = <&pm8150_adc ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
skin-therm@1 {
reg = <1>;
io-channels = <&pm8150_adc ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time-us = <200>;
};
wifi-therm@2 {
reg = <2>;
/* msm-5.10 uses ADC5_AMUX_THM2, although there is a pullup */
io-channels = <&pm8150_adc ADC5_AMUX_THM2_100K_PU>;
qcom,hw-settle-time-us = <200>;
};
};
&remoteproc_adsp {
firmware-name = "qcom/sar2130p/adsp.mbn";
status = "okay";
};
&sdhc_1 {
vmmc-supply = <&vreg_l10a_2p95>;
vqmmc-supply = <&vreg_l7a_1p8>;
status = "okay";
};
&tlmm {
bt_en_state: bt-enable-state {
pins = "gpio46";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
pcie0_default_state: pcie0-default-state {
perst-pins {
pins = "gpio55";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq-pins {
pins = "gpio56";
function = "pcie0_clkreqn";
drive-strength = <2>;
bias-pull-up;
};
wake-pins {
pins = "gpio57";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie1_default_state: pcie1-default-state {
perst-pins {
pins = "gpio58";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
clkreq-pins {
pins = "gpio59";
function = "pcie1_clkreqn";
drive-strength = <2>;
bias-pull-up;
};
wake-pins {
pins = "gpio60";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
wlan_en_state: wlan-enable-state {
pins = "gpio45";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
};
&uart7 {
status = "okay";
bluetooth {
compatible = "qcom,wcn7850-bt";
vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
vddaon-supply = <&vreg_pmu_aon_0p59>;
vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;
vddwlmx-supply = <&vreg_pmu_wlmx_0p85>;
vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
vddrfa1p8-supply = <&vreg_pmu_rfa_1p8>;
max-speed = <3200000>;
};
};
&uart11 {
status = "okay";
};
&usb_1 {
status = "okay";
};
&usb_1_hsphy {
vdd-supply = <&vreg_l8a_0p88>;
vdda12-supply = <&vreg_l3a_1p2>;
phys = <&ptn3222>;
status = "okay";
};
&usb_dp_qmpphy {
vdda-phy-supply = <&vreg_l3a_1p2>;
vdda-pll-supply = <&vreg_l1a_0p91>;
status = "okay";
};

3123
arch/arm64/boot/dts/qcom/sar2130p.dtsi Normal file
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File diff suppressed because it is too large Load Diff

1351
arch/arm64/boot/dts/qcom/x1e001de-devkit.dts Normal file
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File diff suppressed because it is too large Load Diff

16
arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts
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@ -635,11 +635,19 @@
status = "okay";
};
&smb2360_0 {
status = "okay";
};
&smb2360_0_eusb2_repeater {
vdd18-supply = <&vreg_l3d_1p8>;
vdd3-supply = <&vreg_l2b_3p0>;
};
&smb2360_1 {
status = "okay";
};
&smb2360_1_eusb2_repeater {
vdd18-supply = <&vreg_l3d_1p8>;
vdd3-supply = <&vreg_l14b_3p0>;
@ -773,6 +781,10 @@
status = "okay";
};
&usb_1_ss0_dwc3 {
dr_mode = "host";
};
&usb_1_ss0_dwc3_hs {
remote-endpoint = <&pmic_glink_ss0_hs_in>;
};
@ -801,6 +813,10 @@
status = "okay";
};
&usb_1_ss1_dwc3 {
dr_mode = "host";
};
&usb_1_ss1_dwc3_hs {
remote-endpoint = <&pmic_glink_ss1_hs_in>;
};

16
arch/arm64/boot/dts/qcom/x1e80100-asus-vivobook-s15.dts
View File

@ -328,6 +328,14 @@
};
};
&gpu {
status = "okay";
zap-shader {
firmware-name = "qcom/x1e80100/ASUSTeK/vivobook-s15/qcdxkmsuc8380.mbn";
};
};
&i2c0 {
clock-frequency = <400000>;
status = "okay";
@ -493,11 +501,19 @@
status = "okay";
};
&smb2360_0 {
status = "okay";
};
&smb2360_0_eusb2_repeater {
vdd18-supply = <&vreg_l3d_1p8>;
vdd3-supply = <&vreg_l2b_3p0>;
};
&smb2360_1 {
status = "okay";
};
&smb2360_1_eusb2_repeater {
vdd18-supply = <&vreg_l3d_1p8>;
vdd3-supply = <&vreg_l14b_3p0>;

20
arch/arm64/boot/dts/qcom/x1e80100-crd.dts
View File

@ -932,11 +932,19 @@
status = "okay";
};
&smb2360_0 {
status = "okay";
};
&smb2360_0_eusb2_repeater {
vdd18-supply = <&vreg_l3d_1p8>;
vdd3-supply = <&vreg_l2b_3p0>;
};
&smb2360_1 {
status = "okay";
};
&smb2360_1_eusb2_repeater {
vdd18-supply = <&vreg_l3d_1p8>;
vdd3-supply = <&vreg_l14b_3p0>;
@ -1197,6 +1205,10 @@
status = "okay";
};
&usb_1_ss0_dwc3 {
dr_mode = "host";
};
&usb_1_ss0_dwc3_hs {
remote-endpoint = <&pmic_glink_ss0_hs_in>;
};
@ -1225,6 +1237,10 @@
status = "okay";
};
&usb_1_ss1_dwc3 {
dr_mode = "host";
};
&usb_1_ss1_dwc3_hs {
remote-endpoint = <&pmic_glink_ss1_hs_in>;
};
@ -1253,6 +1269,10 @@
status = "okay";
};
&usb_1_ss2_dwc3 {
dr_mode = "host";
};
&usb_1_ss2_dwc3_hs {
remote-endpoint = <&pmic_glink_ss2_hs_in>;
};

301
arch/arm64/boot/dts/qcom/x1e80100-dell-xps13-9345.dts
View File

@ -89,7 +89,15 @@
reg = <1>;
pmic_glink_ss0_ss_in: endpoint {
remote-endpoint = <&usb_1_ss0_qmpphy_out>;
remote-endpoint = <&retimer_ss0_ss_out>;
};
};
port@2 {
reg = <2>;
pmic_glink_ss0_con_sbu_in: endpoint {
remote-endpoint = <&retimer_ss0_con_sbu_out>;
};
};
};
@ -118,7 +126,15 @@
reg = <1>;
pmic_glink_ss1_ss_in: endpoint {
remote-endpoint = <&usb_1_ss1_qmpphy_out>;
remote-endpoint = <&retimer_ss1_ss_out>;
};
};
port@2 {
reg = <2>;
pmic_glink_ss1_con_sbu_in: endpoint {
remote-endpoint = <&retimer_ss1_con_sbu_out>;
};
};
};
@ -166,6 +182,102 @@
regulator-boot-on;
};
vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
compatible = "regulator-fixed";
regulator-name = "VREG_RTMR0_1P15";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&rtmr0_1p15_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_rtmr0_1p8: regulator-rtmr0-1p8 {
compatible = "regulator-fixed";
regulator-name = "VREG_RTMR0_1P8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&rtmr0_1p8_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_rtmr0_3p3: regulator-rtmr0-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_RTMR0_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&rtmr0_3p3_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_rtmr1_1p15: regulator-rtmr1-1p15 {
compatible = "regulator-fixed";
regulator-name = "VREG_RTMR1_1P15";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&rtmr1_1p15_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_rtmr1_1p8: regulator-rtmr1-1p8 {
compatible = "regulator-fixed";
regulator-name = "VREG_RTMR1_1P8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&rtmr1_1p8_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_rtmr1_3p3: regulator-rtmr1-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_RTMR1_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&rtmr1_3p3_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_vph_pwr: regulator-vph-pwr {
compatible = "regulator-fixed";
@ -492,9 +604,60 @@
&i2c3 {
clock-frequency = <400000>;
status = "disabled";
/* PS8830 Retimer @0x8 */
/* Unknown device @0x9 */
status = "okay";
/* Right-side USB Type-C port */
typec-mux@8 {
compatible = "parade,ps8830";
reg = <0x08>;
clocks = <&rpmhcc RPMH_RF_CLK3>;
clock-names = "xo";
vdd-supply = <&vreg_rtmr0_1p15>;
vdd33-supply = <&vreg_rtmr0_3p3>;
vdd33-cap-supply = <&vreg_rtmr0_3p3>;
vddar-supply = <&vreg_rtmr0_1p15>;
vddat-supply = <&vreg_rtmr0_1p15>;
vddio-supply = <&vreg_rtmr0_1p8>;
reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&rtmr0_default>;
pinctrl-names = "default";
retimer-switch;
orientation-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
retimer_ss0_ss_out: endpoint {
remote-endpoint = <&pmic_glink_ss0_ss_in>;
};
};
port@1 {
reg = <1>;
retimer_ss0_ss_in: endpoint {
remote-endpoint = <&usb_1_ss0_qmpphy_out>;
};
};
port@2 {
reg = <2>;
retimer_ss0_con_sbu_out: endpoint {
remote-endpoint = <&pmic_glink_ss0_con_sbu_in>;
};
};
};
};
};
&i2c5 {
@ -505,9 +668,61 @@
&i2c7 {
clock-frequency = <400000>;
status = "disabled";
/* PS8830 Retimer @0x8 */
/* Unknown device @0x9 */
status = "okay";
/* Left-side USB Type-C port */
typec-mux@8 {
compatible = "parade,ps8830";
reg = <0x8>;
clocks = <&rpmhcc RPMH_RF_CLK4>;
clock-names = "xo";
vdd-supply = <&vreg_rtmr1_1p15>;
vdd33-supply = <&vreg_rtmr1_3p3>;
vdd33-cap-supply = <&vreg_rtmr1_3p3>;
vddar-supply = <&vreg_rtmr1_1p15>;
vddat-supply = <&vreg_rtmr1_1p15>;
vddio-supply = <&vreg_rtmr1_1p8>;
reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&rtmr1_default>;
pinctrl-names = "default";
retimer-switch;
orientation-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
retimer_ss1_ss_out: endpoint {
remote-endpoint = <&pmic_glink_ss1_ss_in>;
};
};
port@1 {
reg = <1>;
retimer_ss1_ss_in: endpoint {
remote-endpoint = <&usb_1_ss1_qmpphy_out>;
};
};
port@2 {
reg = <2>;
retimer_ss1_con_sbu_out: endpoint {
remote-endpoint = <&pmic_glink_ss1_con_sbu_in>;
};
};
};
};
};
&i2c8 {
@ -634,6 +849,36 @@
status = "okay";
};
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";
function = "normal";
power-source = <1>; /* 1.8V */
};
rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state {
pins = "gpio11";
function = "normal";
power-source = <1>; /* 1.8V */
};
};
&pmc8380_5_gpios {
rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state {
pins = "gpio8";
function = "normal";
power-source = <1>; /* 1.8V */
};
};
&pm8550ve_9_gpios {
rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state {
pins = "gpio8";
function = "normal";
power-source = <1>; /* 1.8V */
};
};
&qupv3_0 {
status = "okay";
};
@ -660,11 +905,19 @@
status = "okay";
};
&smb2360_0 {
status = "okay";
};
&smb2360_0_eusb2_repeater {
vdd18-supply = <&vreg_l3d_1p8>;
vdd3-supply = <&vreg_l2b_3p0>;
};
&smb2360_1 {
status = "okay";
};
&smb2360_1_eusb2_repeater {
vdd18-supply = <&vreg_l3d_1p8>;
vdd3-supply = <&vreg_l14b_3p0>;
@ -762,6 +1015,34 @@
};
};
rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state {
pins = "gpio188";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state {
pins = "gpio175";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state {
pins = "gpio186";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
rtmr1_default: rtmr1-reset-n-active-state {
pins = "gpio176";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
tpad_default: tpad-default-state {
disable-pins {
pins = "gpio38";
@ -839,7 +1120,7 @@
};
&usb_1_ss0_qmpphy_out {
remote-endpoint = <&pmic_glink_ss0_ss_in>;
remote-endpoint = <&retimer_ss0_ss_in>;
};
&usb_1_ss1_hsphy {
@ -871,5 +1152,5 @@
};
&usb_1_ss1_qmpphy_out {
remote-endpoint = <&pmic_glink_ss1_ss_in>;
remote-endpoint = <&retimer_ss1_ss_in>;
};

8
arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts
View File

@ -717,11 +717,19 @@
status = "okay";
};
&smb2360_0 {
status = "okay";
};
&smb2360_0_eusb2_repeater {
vdd18-supply = <&vreg_l3d_1p8>;
vdd3-supply = <&vreg_l2b_3p0>;
};
&smb2360_1 {
status = "okay";
};
&smb2360_1_eusb2_repeater {
vdd18-supply = <&vreg_l3d_1p8>;
vdd3-supply = <&vreg_l14b_3p0>;

519
arch/arm64/boot/dts/qcom/x1e80100-microsoft-romulus.dtsi
View File

@ -22,6 +22,33 @@
i2c7 = &i2c7;
};
wcd938x: audio-codec {
compatible = "qcom,wcd9385-codec";
reset-gpios = <&tlmm 191 GPIO_ACTIVE_LOW>;
qcom,micbias1-microvolt = <1800000>;
qcom,micbias2-microvolt = <1800000>;
qcom,micbias3-microvolt = <1800000>;
qcom,micbias4-microvolt = <1800000>;
qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
qcom,rx-device = <&wcd_rx>;
qcom,tx-device = <&wcd_tx>;
vdd-buck-supply = <&vreg_l15b>;
vdd-rxtx-supply = <&vreg_l15b>;
vdd-io-supply = <&vreg_l15b>;
vdd-mic-bias-supply = <&vreg_bob1>;
pinctrl-0 = <&wcd_default>;
pinctrl-names = "default";
#sound-dai-cells = <1>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pmk8550_pwm 0 5000000>;
@ -97,7 +124,15 @@
reg = <1>;
pmic_glink_ss0_ss_in: endpoint {
remote-endpoint = <&usb_1_ss0_qmpphy_out>;
remote-endpoint = <&retimer_ss0_ss_out>;
};
};
port@2 {
reg = <2>;
pmic_glink_ss0_con_sbu_in: endpoint {
remote-endpoint = <&retimer_ss0_con_sbu_out>;
};
};
};
@ -126,7 +161,15 @@
reg = <1>;
pmic_glink_ss1_ss_in: endpoint {
remote-endpoint = <&usb_1_ss1_qmpphy_out>;
remote-endpoint = <&retimer_ss1_ss_out>;
};
};
port@2 {
reg = <2>;
pmic_glink_ss1_con_sbu_in: endpoint {
remote-endpoint = <&retimer_ss1_con_sbu_out>;
};
};
};
@ -158,6 +201,109 @@
regulator-boot-on;
};
vreg_rtmr0_1p15: regulator-rtmr0-1p15 {
compatible = "regulator-fixed";
regulator-name = "VREG_RTMR0_1P15";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
gpio = <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&rtmr0_1p15_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_rtmr0_1p8: regulator-rtmr0-1p8 {
compatible = "regulator-fixed";
regulator-name = "VREG_RTMR0_1P8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&rtmr0_1p8_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_rtmr0_3p3: regulator-rtmr0-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_RTMR0_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&rtmr0_3p3_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_rtmr1_1p15: regulator-rtmr1-1p15 {
compatible = "regulator-fixed";
regulator-name = "VREG_RTMR1_1P15";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
gpio = <&tlmm 188 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&rtmr1_1p15_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_rtmr1_1p8: regulator-rtmr1-1p8 {
compatible = "regulator-fixed";
regulator-name = "VREG_RTMR1_1P8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&tlmm 175 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&rtmr1_1p8_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_rtmr1_3p3: regulator-rtmr1-3p3 {
compatible = "regulator-fixed";
regulator-name = "VREG_RTMR1_3P3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&tlmm 186 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-0 = <&rtmr1_3p3_reg_en>;
pinctrl-names = "default";
regulator-boot-on;
};
vreg_nvme: regulator-nvme {
compatible = "regulator-fixed";
@ -184,6 +330,86 @@
regulator-always-on;
regulator-boot-on;
};
sound {
compatible = "qcom,x1e80100-sndcard";
model = "X1E80100-Romulus";
audio-routing = "SpkrLeft IN", "WSA WSA_SPK1 OUT",
"SpkrRight IN", "WSA WSA_SPK2 OUT",
"IN1_HPHL", "HPHL_OUT",
"IN2_HPHR", "HPHR_OUT",
"AMIC2", "MIC BIAS2",
"VA DMIC0", "MIC BIAS3",
"VA DMIC1", "MIC BIAS3",
"VA DMIC0", "VA MIC BIAS3",
"VA DMIC1", "VA MIC BIAS3",
"TX SWR_INPUT1", "ADC2_OUTPUT";
va-dai-link {
link-name = "VA Capture";
cpu {
sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
};
codec {
sound-dai = <&lpass_vamacro 0>;
};
platform {
sound-dai = <&q6apm>;
};
};
wcd-capture-dai-link {
link-name = "WCD Capture";
cpu {
sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
};
codec {
sound-dai = <&wcd938x 1>, <&swr2 1>, <&lpass_txmacro 0>;
};
platform {
sound-dai = <&q6apm>;
};
};
wcd-playback-dai-link {
link-name = "WCD Playback";
cpu {
sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>;
};
codec {
sound-dai = <&wcd938x 0>, <&swr1 0>, <&lpass_rxmacro 0>;
};
platform {
sound-dai = <&q6apm>;
};
};
wsa-dai-link {
link-name = "WSA Playback";
cpu {
sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>;
};
codec {
sound-dai = <&left_spkr>, <&right_spkr>,
<&swr0 0>, <&lpass_wsamacro 0>;
};
platform {
sound-dai = <&q6apm>;
};
};
};
};
&apps_rsc {
@ -558,7 +784,59 @@
status = "okay";
/* PS8830 USB retimer @8 */
/* Left-side rear port */
typec-mux@8 {
compatible = "parade,ps8830";
reg = <0x8>;
reset-gpios = <&pm8550_gpios 10 GPIO_ACTIVE_LOW>;
clocks = <&rpmhcc RPMH_RF_CLK3>;
clock-names = "xo";
vdd-supply = <&vreg_rtmr0_1p15>;
vdd33-supply = <&vreg_rtmr0_3p3>;
vdd33-cap-supply = <&vreg_rtmr0_3p3>;
vddar-supply = <&vreg_rtmr0_1p15>;
vddat-supply = <&vreg_rtmr0_1p15>;
vddio-supply = <&vreg_rtmr0_1p8>;
pinctrl-0 = <&rtmr0_default>;
pinctrl-names = "default";
retimer-switch;
orientation-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
retimer_ss0_ss_out: endpoint {
remote-endpoint = <&pmic_glink_ss0_ss_in>;
};
};
port@1 {
reg = <1>;
retimer_ss0_ss_in: endpoint {
remote-endpoint = <&usb_1_ss0_qmpphy_out>;
};
};
port@2 {
reg = <2>;
retimer_ss0_con_sbu_out: endpoint {
remote-endpoint = <&pmic_glink_ss0_con_sbu_in>;
};
};
};
};
};
&i2c4 {
@ -592,7 +870,74 @@
status = "okay";
/* PS8830 USB retimer @8 */
/* Left-side front port */
typec-mux@8 {
compatible = "parade,ps8830";
reg = <0x8>;
reset-gpios = <&tlmm 176 GPIO_ACTIVE_LOW>;
clocks = <&rpmhcc RPMH_RF_CLK4>;
clock-names = "xo";
vdd-supply = <&vreg_rtmr1_1p15>;
vdd33-supply = <&vreg_rtmr1_3p3>;
vdd33-cap-supply = <&vreg_rtmr1_3p3>;
vddar-supply = <&vreg_rtmr1_1p15>;
vddat-supply = <&vreg_rtmr1_1p15>;
vddio-supply = <&vreg_rtmr1_1p8>;
retimer-switch;
orientation-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
retimer_ss1_ss_out: endpoint {
remote-endpoint = <&pmic_glink_ss1_ss_in>;
};
};
port@1 {
reg = <1>;
retimer_ss1_ss_in: endpoint {
remote-endpoint = <&usb_1_ss1_qmpphy_out>;
};
};
port@2 {
reg = <2>;
retimer_ss1_con_sbu_out: endpoint {
remote-endpoint = <&pmic_glink_ss1_con_sbu_in>;
};
};
};
};
};
&lpass_tlmm {
spkr_01_sd_n_active: spkr-01-sd-n-active-state {
pins = "gpio12";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-low;
};
};
&lpass_vamacro {
qcom,dmic-sample-rate = <4800000>;
vdd-micb-supply = <&vreg_l1b>;
pinctrl-0 = <&dmic01_default>;
pinctrl-names = "default";
};
&mdss {
@ -641,6 +986,25 @@
status = "okay";
};
&pcie3 {
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie3_default>;
pinctrl-names = "default";
/* The RTS5261 chip on the other side only does Gen1x1 anyway */
max-link-speed = <1>;
status = "okay";
};
&pcie3_phy {
vdda-phy-supply = <&vreg_l3c>;
vdda-pll-supply = <&vreg_l3e>;
status = "okay";
};
&pcie4 {
status = "okay";
};
@ -671,6 +1035,28 @@
status = "okay";
};
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";
function = "normal";
power-source = <1>; /* 1.8V */
};
rtmr0_3p3_reg_en: rtmr0-3p3-reg-en-state {
pins = "gpio11";
function = "normal";
power-source = <1>; /* 1.8V */
};
};
&pm8550ve_9_gpios {
rtmr0_1p8_reg_en: rtmr0-1p8-reg-en-state {
pins = "gpio8";
function = "normal";
power-source = <1>; /* 1.8V */
};
};
&pmc8380_3_gpios {
edp_bl_en: edp-bl-en-state {
pins = "gpio4";
@ -681,6 +1067,14 @@
};
};
&pmc8380_5_gpios {
rtmr0_1p15_reg_en: rtmr0-1p15-reg-en-state {
pins = "gpio8";
function = "normal";
power-source = <1>; /* 1.8V */
};
};
&pmk8550_pwm {
status = "okay";
};
@ -718,11 +1112,19 @@
status = "okay";
};
&smb2360_0 {
status = "okay";
};
&smb2360_0_eusb2_repeater {
vdd18-supply = <&vreg_l3d>;
vdd3-supply = <&vreg_l2b>;
};
&smb2360_1 {
status = "okay";
};
&smb2360_1_eusb2_repeater {
vdd18-supply = <&vreg_l3d>;
vdd3-supply = <&vreg_l14b>;
@ -737,6 +1139,59 @@
vdd3-supply = <&vreg_l8b>;
};
&swr0 {
pinctrl-0 = <&wsa_swr_active>, <&spkr_01_sd_n_active>;
pinctrl-names = "default";
status = "okay";
/* WSA8845, Left speaker */
left_spkr: speaker@0,0 {
compatible = "sdw20217020400";
reg = <0 0>;
reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "SpkrLeft";
vdd-1p8-supply = <&vreg_l15b>;
vdd-io-supply = <&vreg_l12b>;
qcom,port-mapping = <1 2 3 7 10 13>;
};
/* WSA8845, Right speaker */
right_spkr: speaker@0,1 {
compatible = "sdw20217020400";
reg = <0 1>;
reset-gpios = <&lpass_tlmm 12 GPIO_ACTIVE_LOW>;
#sound-dai-cells = <0>;
sound-name-prefix = "SpkrRight";
vdd-1p8-supply = <&vreg_l15b>;
vdd-io-supply = <&vreg_l12b>;
qcom,port-mapping = <4 5 6 7 11 13>;
};
};
&swr1 {
status = "okay";
/* WCD9385 RX */
wcd_rx: codec@0,4 {
compatible = "sdw20217010d00";
reg = <0 4>;
qcom,rx-port-mapping = <1 2 3 4 5>;
};
};
&swr2 {
status = "okay";
/* WCD9385 TX */
wcd_tx: codec@0,3 {
compatible = "sdw20217010d00";
reg = <0 3>;
qcom,tx-port-mapping = <2 2 3 4>;
};
};
&tlmm {
gpio-reserved-ranges = <44 4>, /* SPI (TPM) */
<238 1>; /* UFS Reset */
@ -767,6 +1222,29 @@
bias-disable;
};
pcie3_default: pcie3-default-state {
perst-n-pins {
pins = "gpio143";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
clkreq-n-pins {
pins = "gpio144";
function = "pcie3_clk";
drive-strength = <2>;
bias-pull-up;
};
wake-n-pins {
pins = "gpio145";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
pcie6a_default: pcie6a-default-state {
perst-n-pins {
pins = "gpio152";
@ -790,6 +1268,35 @@
};
};
rtmr1_1p8_reg_en: rtmr1-1p8-reg-en-state {
pins = "gpio175";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
rtmr1_3p3_reg_en: rtmr1-3p3-reg-en-state {
pins = "gpio186";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
rtmr1_1p15_reg_en: rtmr1-1p15-reg-en-state {
pins = "gpio188";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
wcd_default: wcd-reset-n-active-state {
pins = "gpio191";
function = "gpio";
drive-strength = <16>;
bias-disable;
output-low;
};
cam_indicator_en: cam-indicator-en-state {
pins = "gpio225";
function = "gpio";
@ -842,7 +1349,7 @@
};
&usb_1_ss0_qmpphy_out {
remote-endpoint = <&pmic_glink_ss0_ss_in>;
remote-endpoint = <&retimer_ss0_ss_in>;
};
&usb_1_ss1_hsphy {
@ -874,7 +1381,7 @@
};
&usb_1_ss1_qmpphy_out {
remote-endpoint = <&pmic_glink_ss1_ss_in>;
remote-endpoint = <&retimer_ss1_ss_in>;
};
/* MP0 goes to the Surface Connector, MP1 goes to the USB-A port */

4
arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi
View File

@ -491,6 +491,8 @@
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
smb2360_0_eusb2_repeater: phy@fd00 {
compatible = "qcom,smb2360-eusb2-repeater";
reg = <0xfd00>;
@ -504,6 +506,8 @@
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
smb2360_1_eusb2_repeater: phy@fd00 {
compatible = "qcom,smb2360-eusb2-repeater";
reg = <0xfd00>;

8
arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
View File

@ -731,11 +731,19 @@
status = "okay";
};
&smb2360_0 {
status = "okay";
};
&smb2360_0_eusb2_repeater {
vdd18-supply = <&vreg_l3d_1p8>;
vdd3-supply = <&vreg_l2b_3p0>;
};
&smb2360_1 {
status = "okay";
};
&smb2360_1_eusb2_repeater {
vdd18-supply = <&vreg_l3d_1p8>;
vdd3-supply = <&vreg_l14b_3p0>;

212
arch/arm64/boot/dts/qcom/x1e80100.dtsi
View File

@ -743,7 +743,7 @@
clocks = <&bi_tcxo_div2>,
<&sleep_clk>,
<0>,
<&pcie3_phy>,
<&pcie4_phy>,
<&pcie5_phy>,
<&pcie6a_phy>,
@ -2906,6 +2906,208 @@
#interconnect-cells = <2>;
};
pcie3: pcie@1bd0000 {
device_type = "pci";
compatible = "qcom,pcie-x1e80100";
reg = <0x0 0x01bd0000 0x0 0x3000>,
<0x0 0x78000000 0x0 0xf1d>,
<0x0 0x78000f40 0x0 0xa8>,
<0x0 0x78001000 0x0 0x1000>,
<0x0 0x78100000 0x0 0x100000>,
<0x0 0x01bd3000 0x0 0x1000>;
reg-names = "parf",
"dbi",
"elbi",
"atu",
"config",
"mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>,
<0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>,
<0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>;
bus-range = <0x00 0xff>;
dma-coherent;
linux,pci-domain = <3>;
num-lanes = <8>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7",
"global";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
<&gcc GCC_PCIE_3_CFG_AHB_CLK>,
<&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_3_SLV_AXI_CLK>,
<&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
<&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
<&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
clock-names = "aux",
"cfg",
"bus_master",
"bus_slave",
"slave_q2a",
"noc_aggr",
"cnoc_sf_axi";
assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
assigned-clock-rates = <19200000>;
interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "pcie-mem",
"cpu-pcie";
resets = <&gcc GCC_PCIE_3_BCR>,
<&gcc GCC_PCIE_3_LINK_DOWN_BCR>;
reset-names = "pci",
"link_down";
power-domains = <&gcc GCC_PCIE_3_GDSC>;
phys = <&pcie3_phy>;
phy-names = "pciephy";
operating-points-v2 = <&pcie3_opp_table>;
status = "disabled";
pcie3_opp_table: opp-table {
compatible = "operating-points-v2";
/* GEN 1 x1 */
opp-2500000 {
opp-hz = /bits/ 64 <2500000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <250000 1>;
};
/* GEN 1 x2 and GEN 2 x1 */
opp-5000000 {
opp-hz = /bits/ 64 <5000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <500000 1>;
};
/* GEN 1 x4 and GEN 2 x2 */
opp-10000000 {
opp-hz = /bits/ 64 <10000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <1000000 1>;
};
/* GEN 1 x8 and GEN 2 x4 */
opp-20000000 {
opp-hz = /bits/ 64 <20000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <2000000 1>;
};
/* GEN 2 x8 */
opp-40000000 {
opp-hz = /bits/ 64 <40000000>;
required-opps = <&rpmhpd_opp_low_svs>;
opp-peak-kBps = <4000000 1>;
};
/* GEN 3 x1 */
opp-8000000 {
opp-hz = /bits/ 64 <8000000>;
required-opps = <&rpmhpd_opp_svs>;
opp-peak-kBps = <984500 1>;
};
/* GEN 3 x2 and GEN 4 x1 */
opp-16000000 {
opp-hz = /bits/ 64 <16000000>;
required-opps = <&rpmhpd_opp_svs>;
opp-peak-kBps = <1969000 1>;
};
/* GEN 3 x4 and GEN 4 x2 */
opp-32000000 {
opp-hz = /bits/ 64 <32000000>;
required-opps = <&rpmhpd_opp_svs>;
opp-peak-kBps = <3938000 1>;
};
/* GEN 3 x8 and GEN 4 x4 */
opp-64000000 {
opp-hz = /bits/ 64 <64000000>;
required-opps = <&rpmhpd_opp_svs>;
opp-peak-kBps = <7876000 1>;
};
/* GEN 4 x8 */
opp-128000000 {
opp-hz = /bits/ 64 <128000000>;
required-opps = <&rpmhpd_opp_svs>;
opp-peak-kBps = <15753000 1>;
};
};
};
pcie3_phy: phy@1be0000 {
compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
reg = <0 0x01be0000 0 0x10000>;
clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
<&gcc GCC_PCIE_3_CFG_AHB_CLK>,
<&tcsr TCSR_PCIE_8L_CLKREF_EN>,
<&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_3_PIPE_CLK>,
<&gcc GCC_PCIE_3_PIPEDIV2_CLK>;
clock-names = "aux",
"cfg_ahb",
"ref",
"rchng",
"pipe",
"pipediv2";
resets = <&gcc GCC_PCIE_3_PHY_BCR>,
<&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>;
reset-names = "phy",
"phy_nocsr";
assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>;
assigned-clock-rates = <100000000>;
power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>;
#clock-cells = <0>;
clock-output-names = "pcie3_pipe_clk";
#phy-cells = <0>;
status = "disabled";
};
pcie6a: pci@1bf8000 {
device_type = "pci";
compatible = "qcom,pcie-x1e80100";
@ -2924,7 +3126,7 @@
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>,
<0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x1d00000>;
<0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
bus-range = <0x00 0xff>;
dma-coherent;
@ -4066,8 +4268,6 @@
dma-coherent;
usb-role-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -4321,8 +4521,6 @@
dma-coherent;
usb-role-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;
@ -4421,8 +4619,6 @@
dma-coherent;
usb-role-switch;
ports {
#address-cells = <1>;
#size-cells = <0>;

3
arch/arm64/configs/defconfig
View File

@ -609,6 +609,7 @@ CONFIG_PINCTRL_MSM8996=y
CONFIG_PINCTRL_MSM8998=y
CONFIG_PINCTRL_QCM2290=y
CONFIG_PINCTRL_QCS404=y
CONFIG_PINCTRL_QCS615=y
CONFIG_PINCTRL_QDF2XXX=y
CONFIG_PINCTRL_QDU1000=y
CONFIG_PINCTRL_SA8775P=y
@ -1328,6 +1329,7 @@ CONFIG_MSM_MMCC_8998=m
CONFIG_QCM_GCC_2290=y
CONFIG_QCM_DISPCC_2290=m
CONFIG_QCS_GCC_404=y
CONFIG_QCS_GCC_615=y
CONFIG_SC_CAMCC_7280=m
CONFIG_QDU_GCC_1000=y
CONFIG_SC_CAMCC_8280XP=m
@ -1635,6 +1637,7 @@ CONFIG_INTERCONNECT_QCOM_MSM8996=y
CONFIG_INTERCONNECT_QCOM_OSM_L3=m
CONFIG_INTERCONNECT_QCOM_QCM2290=y
CONFIG_INTERCONNECT_QCOM_QCS404=m
CONFIG_INTERCONNECT_QCOM_QCS615=y
CONFIG_INTERCONNECT_QCOM_QDU1000=y
CONFIG_INTERCONNECT_QCOM_SA8775P=y
CONFIG_INTERCONNECT_QCOM_SC7180=y

72
drivers/soc/qcom/pmic_glink.c
View File

@ -4,6 +4,7 @@
* Copyright (c) 2022, Linaro Ltd
*/
#include <linux/auxiliary_bus.h>
#include <linux/cleanup.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/of.h>
@ -100,15 +101,13 @@ void pmic_glink_client_register(struct pmic_glink_client *client)
struct pmic_glink *pg = client->pg;
unsigned long flags;
mutex_lock(&pg->state_lock);
guard(mutex)(&pg->state_lock);
spin_lock_irqsave(&pg->client_lock, flags);
list_add(&client->node, &pg->clients);
client->pdr_notify(client->priv, pg->client_state);
spin_unlock_irqrestore(&pg->client_lock, flags);
mutex_unlock(&pg->state_lock);
}
EXPORT_SYMBOL_GPL(pmic_glink_client_register);
@ -119,26 +118,25 @@ int pmic_glink_send(struct pmic_glink_client *client, void *data, size_t len)
unsigned long start;
int ret;
mutex_lock(&pg->state_lock);
guard(mutex)(&pg->state_lock);
if (!pg->ept) {
ret = -ECONNRESET;
} else {
start = jiffies;
for (;;) {
ret = rpmsg_send(pg->ept, data, len);
if (ret != -EAGAIN)
break;
if (timeout_reached) {
ret = -ETIMEDOUT;
break;
}
usleep_range(1000, 5000);
timeout_reached = time_after(jiffies, start + PMIC_GLINK_SEND_TIMEOUT);
}
return -ECONNRESET;
}
start = jiffies;
for (;;) {
ret = rpmsg_send(pg->ept, data, len);
if (ret != -EAGAIN)
break;
if (timeout_reached) {
ret = -ETIMEDOUT;
break;
}
usleep_range(1000, 5000);
timeout_reached = time_after(jiffies, start + PMIC_GLINK_SEND_TIMEOUT);
}
mutex_unlock(&pg->state_lock);
return ret;
}
@ -227,51 +225,42 @@ static void pmic_glink_pdr_callback(int state, char *svc_path, void *priv)
{
struct pmic_glink *pg = priv;
mutex_lock(&pg->state_lock);
guard(mutex)(&pg->state_lock);
pg->pdr_state = state;
pmic_glink_state_notify_clients(pg);
mutex_unlock(&pg->state_lock);
}
static int pmic_glink_rpmsg_probe(struct rpmsg_device *rpdev)
{
struct pmic_glink *pg = __pmic_glink;
int ret = 0;
mutex_lock(&__pmic_glink_lock);
if (!pg) {
ret = dev_err_probe(&rpdev->dev, -ENODEV, "no pmic_glink device to attach to\n");
goto out_unlock;
}
guard(mutex)(&__pmic_glink_lock);
pg = __pmic_glink;
if (!pg)
return dev_err_probe(&rpdev->dev, -ENODEV, "no pmic_glink device to attach to\n");
dev_set_drvdata(&rpdev->dev, pg);
mutex_lock(&pg->state_lock);
guard(mutex)(&pg->state_lock);
pg->ept = rpdev->ept;
pmic_glink_state_notify_clients(pg);
mutex_unlock(&pg->state_lock);
out_unlock:
mutex_unlock(&__pmic_glink_lock);
return ret;
return 0;
}
static void pmic_glink_rpmsg_remove(struct rpmsg_device *rpdev)
{
struct pmic_glink *pg;
mutex_lock(&__pmic_glink_lock);
guard(mutex)(&__pmic_glink_lock);
pg = __pmic_glink;
if (!pg)
goto out_unlock;
return;
mutex_lock(&pg->state_lock);
guard(mutex)(&pg->state_lock);
pg->ept = NULL;
pmic_glink_state_notify_clients(pg);
mutex_unlock(&pg->state_lock);
out_unlock:
mutex_unlock(&__pmic_glink_lock);
}
static const struct rpmsg_device_id pmic_glink_rpmsg_id_match[] = {
@ -378,9 +367,8 @@ static void pmic_glink_remove(struct platform_device *pdev)
if (pg->client_mask & BIT(PMIC_GLINK_CLIENT_UCSI))
pmic_glink_del_aux_device(pg, &pg->ucsi_aux);
mutex_lock(&__pmic_glink_lock);
guard(mutex)(&__pmic_glink_lock);
__pmic_glink = NULL;
mutex_unlock(&__pmic_glink_lock);
}
static const unsigned long pmic_glink_sc8280xp_client_mask = BIT(PMIC_GLINK_CLIENT_BATT) |

211
include/dt-bindings/clock/qcom,qcs615-gcc.h Normal file
View File

@ -0,0 +1,211 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS615_H
#define _DT_BINDINGS_CLK_QCOM_GCC_QCS615_H
/* GCC clocks */
#define GPLL0_OUT_AUX2_DIV 0
#define GPLL3_OUT_AUX2_DIV 1
#define GPLL0 2
#define GPLL3 3
#define GPLL4 4
#define GPLL6 5
#define GPLL6_OUT_MAIN 6
#define GPLL7 7
#define GPLL8 8
#define GPLL8_OUT_MAIN 9
#define GCC_AGGRE_UFS_PHY_AXI_CLK 10
#define GCC_AGGRE_USB2_SEC_AXI_CLK 11
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 12
#define GCC_AHB2PHY_EAST_CLK 13
#define GCC_AHB2PHY_WEST_CLK 14
#define GCC_BOOT_ROM_AHB_CLK 15
#define GCC_CAMERA_AHB_CLK 16
#define GCC_CAMERA_HF_AXI_CLK 17
#define GCC_CAMERA_XO_CLK 18
#define GCC_CE1_AHB_CLK 19
#define GCC_CE1_AXI_CLK 20
#define GCC_CE1_CLK 21
#define GCC_CFG_NOC_USB2_SEC_AXI_CLK 22
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23
#define GCC_CPUSS_AHB_CLK 24
#define GCC_CPUSS_AHB_CLK_SRC 25
#define GCC_CPUSS_GNOC_CLK 26
#define GCC_DDRSS_GPU_AXI_CLK 27
#define GCC_DISP_AHB_CLK 28
#define GCC_DISP_GPLL0_DIV_CLK_SRC 29
#define GCC_DISP_HF_AXI_CLK 30
#define GCC_DISP_XO_CLK 31
#define GCC_EMAC_AXI_CLK 32
#define GCC_EMAC_PTP_CLK 33
#define GCC_EMAC_PTP_CLK_SRC 34
#define GCC_EMAC_RGMII_CLK 35
#define GCC_EMAC_RGMII_CLK_SRC 36
#define GCC_EMAC_SLV_AHB_CLK 37
#define GCC_GP1_CLK 38
#define GCC_GP1_CLK_SRC 39
#define GCC_GP2_CLK 40
#define GCC_GP2_CLK_SRC 41
#define GCC_GP3_CLK 42
#define GCC_GP3_CLK_SRC 43
#define GCC_GPU_CFG_AHB_CLK 44
#define GCC_GPU_GPLL0_CLK_SRC 45
#define GCC_GPU_GPLL0_DIV_CLK_SRC 46
#define GCC_GPU_IREF_CLK 47
#define GCC_GPU_MEMNOC_GFX_CLK 48
#define GCC_GPU_SNOC_DVM_GFX_CLK 49
#define GCC_PCIE0_PHY_REFGEN_CLK 50
#define GCC_PCIE_0_AUX_CLK 51
#define GCC_PCIE_0_AUX_CLK_SRC 52
#define GCC_PCIE_0_CFG_AHB_CLK 53
#define GCC_PCIE_0_CLKREF_CLK 54
#define GCC_PCIE_0_MSTR_AXI_CLK 55
#define GCC_PCIE_0_PIPE_CLK 56
#define GCC_PCIE_0_SLV_AXI_CLK 57
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 58
#define GCC_PCIE_PHY_AUX_CLK 59
#define GCC_PCIE_PHY_REFGEN_CLK_SRC 60
#define GCC_PDM2_CLK 61
#define GCC_PDM2_CLK_SRC 62
#define GCC_PDM_AHB_CLK 63
#define GCC_PDM_XO4_CLK 64
#define GCC_PRNG_AHB_CLK 65
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 66
#define GCC_QMIP_DISP_AHB_CLK 67
#define GCC_QMIP_PCIE_AHB_CLK 68
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 69
#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 70
#define GCC_QSPI_CORE_CLK 71
#define GCC_QSPI_CORE_CLK_SRC 72
#define GCC_QUPV3_WRAP0_CORE_2X_CLK 73
#define GCC_QUPV3_WRAP0_CORE_CLK 74
#define GCC_QUPV3_WRAP0_S0_CLK 75
#define GCC_QUPV3_WRAP0_S0_CLK_SRC 76
#define GCC_QUPV3_WRAP0_S1_CLK 77
#define GCC_QUPV3_WRAP0_S1_CLK_SRC 78
#define GCC_QUPV3_WRAP0_S2_CLK 79
#define GCC_QUPV3_WRAP0_S2_CLK_SRC 80
#define GCC_QUPV3_WRAP0_S3_CLK 81
#define GCC_QUPV3_WRAP0_S3_CLK_SRC 82
#define GCC_QUPV3_WRAP0_S4_CLK 83
#define GCC_QUPV3_WRAP0_S4_CLK_SRC 84
#define GCC_QUPV3_WRAP0_S5_CLK 85
#define GCC_QUPV3_WRAP0_S5_CLK_SRC 86
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 87
#define GCC_QUPV3_WRAP1_CORE_CLK 88
#define GCC_QUPV3_WRAP1_S0_CLK 89
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 90
#define GCC_QUPV3_WRAP1_S1_CLK 91
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 92
#define GCC_QUPV3_WRAP1_S2_CLK 93
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 94
#define GCC_QUPV3_WRAP1_S3_CLK 95
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 96
#define GCC_QUPV3_WRAP1_S4_CLK 97
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 98
#define GCC_QUPV3_WRAP1_S5_CLK 99
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 100
#define GCC_QUPV3_WRAP_0_M_AHB_CLK 101
#define GCC_QUPV3_WRAP_0_S_AHB_CLK 102
#define GCC_QUPV3_WRAP_1_M_AHB_CLK 103
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 104
#define GCC_RX1_USB2_CLKREF_CLK 105
#define GCC_RX3_USB2_CLKREF_CLK 106
#define GCC_SDCC1_AHB_CLK 107
#define GCC_SDCC1_APPS_CLK 108
#define GCC_SDCC1_APPS_CLK_SRC 109
#define GCC_SDCC1_ICE_CORE_CLK 110
#define GCC_SDCC1_ICE_CORE_CLK_SRC 111
#define GCC_SDCC2_AHB_CLK 112
#define GCC_SDCC2_APPS_CLK 113
#define GCC_SDCC2_APPS_CLK_SRC 114
#define GCC_SDR_CORE_CLK 115
#define GCC_SDR_CSR_HCLK 116
#define GCC_SDR_PRI_MI2S_CLK 117
#define GCC_SDR_SEC_MI2S_CLK 118
#define GCC_SDR_WR0_MEM_CLK 119
#define GCC_SDR_WR1_MEM_CLK 120
#define GCC_SDR_WR2_MEM_CLK 121
#define GCC_SYS_NOC_CPUSS_AHB_CLK 122
#define GCC_UFS_CARD_CLKREF_CLK 123
#define GCC_UFS_MEM_CLKREF_CLK 124
#define GCC_UFS_PHY_AHB_CLK 125
#define GCC_UFS_PHY_AXI_CLK 126
#define GCC_UFS_PHY_AXI_CLK_SRC 127
#define GCC_UFS_PHY_ICE_CORE_CLK 128
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 129
#define GCC_UFS_PHY_PHY_AUX_CLK 130
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 131
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 132
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 133
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 134
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 135
#define GCC_USB20_SEC_MASTER_CLK 136
#define GCC_USB20_SEC_MASTER_CLK_SRC 137
#define GCC_USB20_SEC_MOCK_UTMI_CLK 138
#define GCC_USB20_SEC_MOCK_UTMI_CLK_SRC 139
#define GCC_USB20_SEC_SLEEP_CLK 140
#define GCC_USB2_PRIM_CLKREF_CLK 141
#define GCC_USB2_SEC_CLKREF_CLK 142
#define GCC_USB2_SEC_PHY_AUX_CLK 143
#define GCC_USB2_SEC_PHY_AUX_CLK_SRC 144
#define GCC_USB2_SEC_PHY_COM_AUX_CLK 145
#define GCC_USB2_SEC_PHY_PIPE_CLK 146
#define GCC_USB30_PRIM_MASTER_CLK 147
#define GCC_USB30_PRIM_MASTER_CLK_SRC 148
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 149
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 150
#define GCC_USB30_PRIM_SLEEP_CLK 151
#define GCC_USB3_PRIM_CLKREF_CLK 152
#define GCC_USB3_PRIM_PHY_AUX_CLK 153
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 154
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 155
#define GCC_USB3_PRIM_PHY_PIPE_CLK 156
#define GCC_USB3_SEC_CLKREF_CLK 157
#define GCC_VIDEO_AHB_CLK 158
#define GCC_VIDEO_AXI0_CLK 159
#define GCC_VIDEO_XO_CLK 160
#define GCC_VSENSOR_CLK_SRC 161
#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 162
#define GCC_UFS_PHY_AXI_HW_CTL_CLK 163
#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 164
#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 165
#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 166
/* GCC Resets */
#define GCC_EMAC_BCR 0
#define GCC_QUSB2PHY_PRIM_BCR 1
#define GCC_QUSB2PHY_SEC_BCR 2
#define GCC_USB30_PRIM_BCR 3
#define GCC_USB2_PHY_SEC_BCR 4
#define GCC_USB3_DP_PHY_SEC_BCR 5
#define GCC_USB3PHY_PHY_SEC_BCR 6
#define GCC_PCIE_0_BCR 7
#define GCC_PCIE_0_PHY_BCR 8
#define GCC_PCIE_PHY_BCR 9
#define GCC_PCIE_PHY_COM_BCR 10
#define GCC_UFS_PHY_BCR 11
#define GCC_USB20_SEC_BCR 12
#define GCC_USB3_PHY_PRIM_SP0_BCR 13
#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 14
#define GCC_SDCC1_BCR 15
#define GCC_SDCC2_BCR 16
/* GCC power domains */
#define EMAC_GDSC 0
#define PCIE_0_GDSC 1
#define UFS_PHY_GDSC 2
#define USB20_SEC_GDSC 3
#define USB30_PRIM_GDSC 4
#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 5
#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 6
#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 7
#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 8
#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 9
#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 10
#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11
#endif