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EDAC/amd64: Add new register offset support and related changes
Introduce a "family flags" bitmask that can be used to indicate any special behavior needed on a per-family basis. Add a flag to indicate a system uses the new register offsets introduced with Family 19h Model 10h. Use this flag to account for register offset changes, a new bitfield indicating DDR5 use on a memory controller, and to set the proper number of chip select masks. Rework f17_addr_mask_to_cs_size() to properly handle the change in chip select masks. And update code comments to reflect the updated Chip Select, DIMM, and Mask relationships. [uninitialized variable warning] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Reviewed-by: William Roche <william.roche@oracle.com> Link: https://lore.kernel.org/r/20220202144307.2678405-3-yazen.ghannam@amd.com
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@ -15,6 +15,21 @@ static struct msr __percpu *msrs;
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static struct amd64_family_type *fam_type;
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static inline u32 get_umc_reg(u32 reg)
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{
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if (!fam_type->flags.zn_regs_v2)
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return reg;
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switch (reg) {
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case UMCCH_ADDR_CFG: return UMCCH_ADDR_CFG_DDR5;
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case UMCCH_ADDR_MASK_SEC: return UMCCH_ADDR_MASK_SEC_DDR5;
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case UMCCH_DIMM_CFG: return UMCCH_DIMM_CFG_DDR5;
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}
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WARN_ONCE(1, "%s: unknown register 0x%x", __func__, reg);
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return 0;
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}
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/* Per-node stuff */
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static struct ecc_settings **ecc_stngs;
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@ -1429,8 +1444,10 @@ static void __dump_misc_regs_df(struct amd64_pvt *pvt)
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edac_dbg(1, "UMC%d x16 DIMMs present: %s\n",
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i, (umc->dimm_cfg & BIT(7)) ? "yes" : "no");
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if (umc->dram_type == MEM_LRDDR4) {
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amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ADDR_CFG, &tmp);
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if (umc->dram_type == MEM_LRDDR4 || umc->dram_type == MEM_LRDDR5) {
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amd_smn_read(pvt->mc_node_id,
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umc_base + get_umc_reg(UMCCH_ADDR_CFG),
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&tmp);
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edac_dbg(1, "UMC%d LRDIMM %dx rank multiply\n",
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i, 1 << ((tmp >> 4) & 0x3));
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}
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@ -1505,7 +1522,7 @@ static void prep_chip_selects(struct amd64_pvt *pvt)
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for_each_umc(umc) {
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pvt->csels[umc].b_cnt = 4;
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pvt->csels[umc].m_cnt = 2;
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pvt->csels[umc].m_cnt = fam_type->flags.zn_regs_v2 ? 4 : 2;
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}
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} else {
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@ -1545,7 +1562,7 @@ static void read_umc_base_mask(struct amd64_pvt *pvt)
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}
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umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK;
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umc_mask_reg_sec = get_umc_base(umc) + UMCCH_ADDR_MASK_SEC;
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umc_mask_reg_sec = get_umc_base(umc) + get_umc_reg(UMCCH_ADDR_MASK_SEC);
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for_each_chip_select_mask(cs, umc, pvt) {
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mask = &pvt->csels[umc].csmasks[cs];
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@ -1629,12 +1646,25 @@ static void determine_memory_type_df(struct amd64_pvt *pvt)
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continue;
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}
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if (umc->dimm_cfg & BIT(5))
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umc->dram_type = MEM_LRDDR4;
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else if (umc->dimm_cfg & BIT(4))
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umc->dram_type = MEM_RDDR4;
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else
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umc->dram_type = MEM_DDR4;
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/*
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* Check if the system supports the "DDR Type" field in UMC Config
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* and has DDR5 DIMMs in use.
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*/
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if (fam_type->flags.zn_regs_v2 && ((umc->umc_cfg & GENMASK(2, 0)) == 0x1)) {
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if (umc->dimm_cfg & BIT(5))
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umc->dram_type = MEM_LRDDR5;
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else if (umc->dimm_cfg & BIT(4))
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umc->dram_type = MEM_RDDR5;
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else
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umc->dram_type = MEM_DDR5;
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} else {
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if (umc->dimm_cfg & BIT(5))
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umc->dram_type = MEM_LRDDR4;
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else if (umc->dimm_cfg & BIT(4))
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umc->dram_type = MEM_RDDR4;
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else
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umc->dram_type = MEM_DDR4;
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}
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edac_dbg(1, " UMC%d DIMM type: %s\n", i, edac_mem_types[umc->dram_type]);
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}
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@ -2166,6 +2196,7 @@ static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,
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{
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u32 addr_mask_orig, addr_mask_deinterleaved;
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u32 msb, weight, num_zero_bits;
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int cs_mask_nr = csrow_nr;
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int dimm, size = 0;
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/* No Chip Selects are enabled. */
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@ -2181,17 +2212,33 @@ static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,
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return size;
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/*
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* There is one mask per DIMM, and two Chip Selects per DIMM.
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* CS0 and CS1 -> DIMM0
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* CS2 and CS3 -> DIMM1
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* Family 17h introduced systems with one mask per DIMM,
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* and two Chip Selects per DIMM.
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*
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* CS0 and CS1 -> MASK0 / DIMM0
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* CS2 and CS3 -> MASK1 / DIMM1
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*
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* Family 19h Model 10h introduced systems with one mask per Chip Select,
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* and two Chip Selects per DIMM.
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*
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* CS0 -> MASK0 -> DIMM0
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* CS1 -> MASK1 -> DIMM0
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* CS2 -> MASK2 -> DIMM1
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* CS3 -> MASK3 -> DIMM1
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*
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* Keep the mask number equal to the Chip Select number for newer systems,
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* and shift the mask number for older systems.
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*/
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dimm = csrow_nr >> 1;
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if (!fam_type->flags.zn_regs_v2)
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cs_mask_nr >>= 1;
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/* Asymmetric dual-rank DIMM support. */
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if ((csrow_nr & 1) && (cs_mode & CS_ODD_SECONDARY))
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addr_mask_orig = pvt->csels[umc].csmasks_sec[dimm];
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addr_mask_orig = pvt->csels[umc].csmasks_sec[cs_mask_nr];
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else
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addr_mask_orig = pvt->csels[umc].csmasks[dimm];
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addr_mask_orig = pvt->csels[umc].csmasks[cs_mask_nr];
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/*
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* The number of zero bits in the mask is equal to the number of bits
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@ -2947,6 +2994,7 @@ static struct amd64_family_type family_types[] = {
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.f0_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F0,
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.f6_id = PCI_DEVICE_ID_AMD_19H_M10H_DF_F6,
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.max_mcs = 12,
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.flags.zn_regs_v2 = 1,
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.ops = {
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.early_channel_count = f17_early_channel_count,
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.dbam_to_cs = f17_addr_mask_to_cs_size,
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@ -3385,7 +3433,7 @@ static void __read_mc_regs_df(struct amd64_pvt *pvt)
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umc_base = get_umc_base(i);
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umc = &pvt->umc[i];
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amd_smn_read(nid, umc_base + UMCCH_DIMM_CFG, &umc->dimm_cfg);
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amd_smn_read(nid, umc_base + get_umc_reg(UMCCH_DIMM_CFG), &umc->dimm_cfg);
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amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg);
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amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl);
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amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl);
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@ -273,8 +273,11 @@
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#define UMCCH_BASE_ADDR_SEC 0x10
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#define UMCCH_ADDR_MASK 0x20
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#define UMCCH_ADDR_MASK_SEC 0x28
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#define UMCCH_ADDR_MASK_SEC_DDR5 0x30
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#define UMCCH_ADDR_CFG 0x30
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#define UMCCH_ADDR_CFG_DDR5 0x40
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#define UMCCH_DIMM_CFG 0x80
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#define UMCCH_DIMM_CFG_DDR5 0x90
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#define UMCCH_UMC_CFG 0x100
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#define UMCCH_SDP_CTRL 0x104
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#define UMCCH_ECC_CTRL 0x14C
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@ -488,11 +491,22 @@ struct low_ops {
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unsigned cs_mode, int cs_mask_nr);
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};
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struct amd64_family_flags {
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/*
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* Indicates that the system supports the new register offsets, etc.
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* first introduced with Family 19h Model 10h.
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*/
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__u64 zn_regs_v2 : 1,
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__reserved : 63;
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};
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struct amd64_family_type {
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const char *ctl_name;
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u16 f0_id, f1_id, f2_id, f6_id;
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/* Maximum number of memory controllers per die/node. */
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u8 max_mcs;
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struct amd64_family_flags flags;
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struct low_ops ops;
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};
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