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sh_eth: add sh_eth_cpu_data::xdfar_rw flag
The GEther-like controllers have writeable RDFAR/TDFAR, on the others they are read-only or just absent (on R-Car). Currently we are calling sh_eth_is_{gether|rz_fast_ether}() in order to check if these registers can be written to, however it would be simpler to check the new 'xdfar_rw' bitfield in the 'struct sh_eth_cpu_data'... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -611,6 +611,7 @@ static struct sh_eth_cpu_data r7s72100_data = {
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.rpadir_value = 2 << 16,
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.no_trimd = 1,
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.no_ade = 1,
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.xdfar_rw = 1,
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.hw_checksum = 1,
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.tsu = 1,
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};
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@ -659,6 +660,7 @@ static struct sh_eth_cpu_data r8a7740_data = {
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.rpadir_value = 2 << 16,
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.no_trimd = 1,
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.no_ade = 1,
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.xdfar_rw = 1,
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.hw_checksum = 1,
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.tsu = 1,
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.select_mii = 1,
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@ -918,6 +920,7 @@ static struct sh_eth_cpu_data sh7757_data_giga = {
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.rpadir_value = 2 << 16,
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.no_trimd = 1,
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.no_ade = 1,
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.xdfar_rw = 1,
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.tsu = 1,
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.dual_port = 1,
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};
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@ -955,6 +958,7 @@ static struct sh_eth_cpu_data sh7734_data = {
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.hw_swap = 1,
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.no_trimd = 1,
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.no_ade = 1,
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.xdfar_rw = 1,
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.tsu = 1,
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.hw_checksum = 1,
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.select_mii = 1,
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@ -993,6 +997,7 @@ static struct sh_eth_cpu_data sh7763_data = {
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.hw_swap = 1,
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.no_trimd = 1,
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.no_ade = 1,
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.xdfar_rw = 1,
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.tsu = 1,
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.irq_flags = IRQF_SHARED,
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.magic = 1,
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@ -1301,8 +1306,7 @@ static void sh_eth_ring_format(struct net_device *ndev)
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/* Rx descriptor address set */
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if (i == 0) {
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sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
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if (sh_eth_is_gether(mdp) ||
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sh_eth_is_rz_fast_ether(mdp))
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if (mdp->cd->xdfar_rw)
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sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
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}
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}
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@ -1324,8 +1328,7 @@ static void sh_eth_ring_format(struct net_device *ndev)
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if (i == 0) {
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/* Tx descriptor address set */
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sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
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if (sh_eth_is_gether(mdp) ||
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sh_eth_is_rz_fast_ether(mdp))
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if (mdp->cd->xdfar_rw)
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sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
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}
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}
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@ -508,6 +508,7 @@ struct sh_eth_cpu_data {
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unsigned rpadir:1; /* E-DMAC have RPADIR */
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unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */
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unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */
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unsigned xdfar_rw:1; /* E-DMAC has writeable RDFAR/TDFAR */
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unsigned hw_checksum:1; /* E-DMAC has CSMR */
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unsigned select_mii:1; /* EtherC have RMII_MII (MII select register) */
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unsigned rmiimode:1; /* EtherC has RMIIMODE register */
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