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efi/cper, cxl: Decode CXL Error Log

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Print the CXL Error Log field as found in CXL Protocol Error Section.

The CXL RAS Capability structure will be reused by OS First Handling
and the duplication/appropriate placement will be addressed eventually.

Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
This commit is contained in:
Smita Koralahalli 2022-10-28 20:09:50 +00:00 committed by Ard Biesheuvel
parent abdbf1a25d
commit 2fb6999dd0
2 changed files with 49 additions and 0 deletions
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27
drivers/firmware/efi/cper_cxl.c
View File

@ -9,6 +9,7 @@
#include <linux/cper.h>
#include "cper_cxl.h"
#include <linux/cxl_err.h>
#define PROT_ERR_VALID_AGENT_TYPE BIT_ULL(0)
#define PROT_ERR_VALID_AGENT_ADDRESS BIT_ULL(1)
@ -16,6 +17,7 @@
#define PROT_ERR_VALID_SERIAL_NUMBER BIT_ULL(3)
#define PROT_ERR_VALID_CAPABILITY BIT_ULL(4)
#define PROT_ERR_VALID_DVSEC BIT_ULL(5)
#define PROT_ERR_VALID_ERROR_LOG BIT_ULL(6)
static const char * const prot_err_agent_type_strs[] = {
"Restricted CXL Device",
@ -149,4 +151,29 @@ void cper_print_prot_err(const char *pfx, const struct cper_sec_prot_err *prot_e
print_hex_dump(pfx, "", DUMP_PREFIX_OFFSET, 16, 4, (prot_err + 1),
prot_err->dvsec_len, 0);
}
if (prot_err->valid_bits & PROT_ERR_VALID_ERROR_LOG) {
size_t size = sizeof(*prot_err) + prot_err->dvsec_len;
struct cxl_ras_capability_regs *cxl_ras;
pr_info("%s Error log length: 0x%04x\n", pfx, prot_err->err_len);
pr_info("%s CXL Error Log:\n", pfx);
cxl_ras = (struct cxl_ras_capability_regs *)((long)prot_err + size);
pr_info("%s cxl_ras_uncor_status: 0x%08x", pfx,
cxl_ras->uncor_status);
pr_info("%s cxl_ras_uncor_mask: 0x%08x\n", pfx,
cxl_ras->uncor_mask);
pr_info("%s cxl_ras_uncor_severity: 0x%08x\n", pfx,
cxl_ras->uncor_severity);
pr_info("%s cxl_ras_cor_status: 0x%08x", pfx,
cxl_ras->cor_status);
pr_info("%s cxl_ras_cor_mask: 0x%08x\n", pfx,
cxl_ras->cor_mask);
pr_info("%s cap_control: 0x%08x\n", pfx,
cxl_ras->cap_control);
pr_info("%s Header Log Registers:\n", pfx);
print_hex_dump(pfx, "", DUMP_PREFIX_OFFSET, 16, 4, cxl_ras->header_log,
sizeof(cxl_ras->header_log), 0);
}
}

22
include/linux/cxl_err.h Normal file
View File

@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2022 Advanced Micro Devices, Inc.
*
* Author: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
*/
#ifndef LINUX_CXL_ERR_H
#define LINUX_CXL_ERR_H
/* CXL RAS Capability Structure, CXL v3.1 sec 8.2.4.16 */
struct cxl_ras_capability_regs {
u32 uncor_status;
u32 uncor_mask;
u32 uncor_severity;
u32 cor_status;
u32 cor_mask;
u32 cap_control;
u32 header_log[16];
};
#endif //__CXL_ERR_