mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
synced 2025-01-11 16:29:05 +00:00
drm/nouveau/bar: convert to new-style nvkm_subdev
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
ef8bc5760b
commit
3293228174
@ -53,7 +53,7 @@ u64 nvif_device_time(struct nvif_device *);
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#define nvxx_bios(a) nvkm_bios(nvxx_device(a))
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#define nvxx_fb(a) nvkm_fb(nvxx_device(a))
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#define nvxx_mmu(a) nvkm_mmu(nvxx_device(a))
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#define nvxx_bar(a) nvkm_bar(nvxx_device(a))
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#define nvxx_bar(a) nvxx_device(a)->bar
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#define nvxx_gpio(a) nvkm_gpio(nvxx_device(a))
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#define nvxx_clk(a) nvkm_clk(nvxx_device(a))
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#define nvxx_i2c(a) nvkm_i2c(nvxx_device(a))
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@ -1,28 +1,24 @@
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#ifndef __NVKM_BAR_H__
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#define __NVKM_BAR_H__
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#include <core/subdev.h>
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struct nvkm_mem;
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struct nvkm_vma;
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struct nvkm_bar {
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const struct nvkm_bar_func *func;
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struct nvkm_subdev subdev;
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struct nvkm_vm *(*kmap)(struct nvkm_bar *);
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int (*umap)(struct nvkm_bar *, u64 size, int type, struct nvkm_vma *);
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void (*unmap)(struct nvkm_bar *, struct nvkm_vma *);
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void (*flush)(struct nvkm_bar *);
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spinlock_t lock;
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/* whether the BAR supports to be ioremapped WC or should be uncached */
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bool iomap_uncached;
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};
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static inline struct nvkm_bar *
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nvkm_bar(void *obj)
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{
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return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_BAR);
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}
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void nvkm_bar_flush(struct nvkm_bar *);
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struct nvkm_vm *nvkm_bar_kmap(struct nvkm_bar *);
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int nvkm_bar_umap(struct nvkm_bar *, u64 size, int type, struct nvkm_vma *);
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extern struct nvkm_oclass nv50_bar_oclass;
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extern struct nvkm_oclass gf100_bar_oclass;
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extern struct nvkm_oclass gk20a_bar_oclass;
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int nv50_bar_new(struct nvkm_device *, int, struct nvkm_bar **);
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int g84_bar_new(struct nvkm_device *, int, struct nvkm_bar **);
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int gf100_bar_new(struct nvkm_device *, int, struct nvkm_bar **);
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int gk20a_bar_new(struct nvkm_device *, int, struct nvkm_bar **);
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#endif
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@ -1392,8 +1392,8 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
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if (drm->device.info.family >= NV_DEVICE_INFO_V0_FERMI)
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page_shift = node->page_shift;
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ret = bar->umap(bar, node->size << 12, page_shift,
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&node->bar_vma);
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ret = nvkm_bar_umap(bar, node->size << 12, page_shift,
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&node->bar_vma);
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if (ret)
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return ret;
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@ -1410,14 +1410,13 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
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static void
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nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
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{
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struct nouveau_drm *drm = nouveau_bdev(bdev);
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struct nvkm_bar *bar = nvxx_bar(&drm->device);
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struct nvkm_mem *node = mem->mm_node;
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if (!node->bar_vma.node)
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return;
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bar->unmap(bar, &node->bar_vma);
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nvkm_vm_unmap(&node->bar_vma);
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nvkm_vm_put(&node->bar_vma);
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}
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static int
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@ -778,7 +778,7 @@ nv4e_chipset = {
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static const struct nvkm_device_chip
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nv50_chipset = {
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.name = "G80",
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// .bar = nv50_bar_new,
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.bar = nv50_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = nv50_bus_new,
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// .clk = nv50_clk_new,
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@ -881,7 +881,7 @@ nv68_chipset = {
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static const struct nvkm_device_chip
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nv84_chipset = {
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.name = "G84",
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// .bar = nv50_bar_new,
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.bar = g84_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = nv50_bus_new,
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// .clk = g84_clk_new,
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@ -912,7 +912,7 @@ nv84_chipset = {
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static const struct nvkm_device_chip
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nv86_chipset = {
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.name = "G86",
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// .bar = nv50_bar_new,
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.bar = g84_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = nv50_bus_new,
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// .clk = g84_clk_new,
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@ -943,7 +943,7 @@ nv86_chipset = {
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static const struct nvkm_device_chip
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nv92_chipset = {
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.name = "G92",
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// .bar = nv50_bar_new,
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.bar = g84_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = nv50_bus_new,
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// .clk = g84_clk_new,
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@ -974,7 +974,7 @@ nv92_chipset = {
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static const struct nvkm_device_chip
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nv94_chipset = {
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.name = "G94",
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// .bar = nv50_bar_new,
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.bar = g84_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = g94_bus_new,
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// .clk = g84_clk_new,
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@ -1019,7 +1019,7 @@ nv96_chipset = {
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// .fb = g84_fb_new,
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// .imem = nv50_instmem_new,
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// .mmu = nv50_mmu_new,
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// .bar = nv50_bar_new,
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.bar = g84_bar_new,
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// .volt = nv40_volt_new,
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// .dma = nv50_dma_new,
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// .fifo = g84_fifo_new,
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@ -1050,7 +1050,7 @@ nv98_chipset = {
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// .fb = g84_fb_new,
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// .imem = nv50_instmem_new,
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// .mmu = nv50_mmu_new,
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// .bar = nv50_bar_new,
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.bar = g84_bar_new,
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// .volt = nv40_volt_new,
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// .dma = nv50_dma_new,
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// .fifo = g84_fifo_new,
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@ -1067,7 +1067,7 @@ nv98_chipset = {
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static const struct nvkm_device_chip
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nva0_chipset = {
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.name = "GT200",
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// .bar = nv50_bar_new,
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.bar = g84_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = g94_bus_new,
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// .clk = g84_clk_new,
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@ -1098,7 +1098,7 @@ nva0_chipset = {
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static const struct nvkm_device_chip
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nva3_chipset = {
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.name = "GT215",
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// .bar = nv50_bar_new,
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.bar = g84_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = g94_bus_new,
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// .clk = gt215_clk_new,
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@ -1131,7 +1131,7 @@ nva3_chipset = {
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static const struct nvkm_device_chip
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nva5_chipset = {
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.name = "GT216",
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// .bar = nv50_bar_new,
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.bar = g84_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = g94_bus_new,
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// .clk = gt215_clk_new,
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@ -1163,7 +1163,7 @@ nva5_chipset = {
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static const struct nvkm_device_chip
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nva8_chipset = {
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.name = "GT218",
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// .bar = nv50_bar_new,
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.bar = g84_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = g94_bus_new,
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// .clk = gt215_clk_new,
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@ -1195,7 +1195,7 @@ nva8_chipset = {
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static const struct nvkm_device_chip
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nvaa_chipset = {
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.name = "MCP77/MCP78",
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// .bar = nv50_bar_new,
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.bar = g84_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = g94_bus_new,
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// .clk = mcp77_clk_new,
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@ -1226,7 +1226,7 @@ nvaa_chipset = {
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static const struct nvkm_device_chip
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nvac_chipset = {
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.name = "MCP79/MCP7A",
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// .bar = nv50_bar_new,
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.bar = g84_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = g94_bus_new,
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// .clk = mcp77_clk_new,
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@ -1257,7 +1257,7 @@ nvac_chipset = {
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static const struct nvkm_device_chip
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nvaf_chipset = {
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.name = "MCP89",
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// .bar = nv50_bar_new,
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.bar = g84_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = g94_bus_new,
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// .clk = gt215_clk_new,
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@ -1289,7 +1289,7 @@ nvaf_chipset = {
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static const struct nvkm_device_chip
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nvc0_chipset = {
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.name = "GF100",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .clk = gf100_clk_new,
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@ -1324,7 +1324,7 @@ nvc0_chipset = {
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static const struct nvkm_device_chip
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nvc1_chipset = {
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.name = "GF108",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .clk = gf100_clk_new,
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@ -1358,7 +1358,7 @@ nvc1_chipset = {
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static const struct nvkm_device_chip
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nvc3_chipset = {
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.name = "GF106",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .clk = gf100_clk_new,
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@ -1392,7 +1392,7 @@ nvc3_chipset = {
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static const struct nvkm_device_chip
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nvc4_chipset = {
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.name = "GF104",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .clk = gf100_clk_new,
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@ -1427,7 +1427,7 @@ nvc4_chipset = {
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static const struct nvkm_device_chip
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nvc8_chipset = {
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.name = "GF110",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .clk = gf100_clk_new,
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@ -1462,7 +1462,7 @@ nvc8_chipset = {
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static const struct nvkm_device_chip
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nvce_chipset = {
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.name = "GF114",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .clk = gf100_clk_new,
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@ -1497,7 +1497,7 @@ nvce_chipset = {
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static const struct nvkm_device_chip
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nvcf_chipset = {
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.name = "GF116",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .clk = gf100_clk_new,
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@ -1531,7 +1531,7 @@ nvcf_chipset = {
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static const struct nvkm_device_chip
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nvd7_chipset = {
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.name = "GF117",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .clk = gf100_clk_new,
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@ -1563,7 +1563,7 @@ nvd7_chipset = {
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static const struct nvkm_device_chip
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nvd9_chipset = {
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.name = "GF119",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .clk = gf100_clk_new,
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@ -1597,7 +1597,7 @@ nvd9_chipset = {
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static const struct nvkm_device_chip
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nve4_chipset = {
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.name = "GK104",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .clk = gk104_clk_new,
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@ -1633,7 +1633,7 @@ nve4_chipset = {
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static const struct nvkm_device_chip
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nve6_chipset = {
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.name = "GK106",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .clk = gk104_clk_new,
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@ -1669,7 +1669,7 @@ nve6_chipset = {
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static const struct nvkm_device_chip
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nve7_chipset = {
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.name = "GK107",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .clk = gk104_clk_new,
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@ -1705,7 +1705,7 @@ nve7_chipset = {
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static const struct nvkm_device_chip
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nvea_chipset = {
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.name = "GK20A",
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// .bar = gk20a_bar_new,
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.bar = gk20a_bar_new,
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// .bus = gf100_bus_new,
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// .clk = gk20a_clk_new,
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// .fb = gk20a_fb_new,
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@ -1729,7 +1729,7 @@ nvea_chipset = {
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static const struct nvkm_device_chip
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nvf0_chipset = {
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.name = "GK110",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .clk = gk104_clk_new,
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@ -1765,7 +1765,7 @@ nvf0_chipset = {
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static const struct nvkm_device_chip
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nvf1_chipset = {
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.name = "GK110B",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .clk = gk104_clk_new,
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@ -1801,7 +1801,7 @@ nvf1_chipset = {
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static const struct nvkm_device_chip
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nv106_chipset = {
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.name = "GK208B",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .clk = gk104_clk_new,
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@ -1836,7 +1836,7 @@ nv106_chipset = {
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static const struct nvkm_device_chip
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nv108_chipset = {
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.name = "GK208",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .clk = gk104_clk_new,
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@ -1871,7 +1871,7 @@ nv108_chipset = {
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static const struct nvkm_device_chip
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nv117_chipset = {
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.name = "GM107",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .clk = gk104_clk_new,
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@ -1901,7 +1901,7 @@ nv117_chipset = {
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static const struct nvkm_device_chip
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nv124_chipset = {
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.name = "GM204",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .devinit = gm204_devinit_new,
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@ -1930,7 +1930,7 @@ nv124_chipset = {
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static const struct nvkm_device_chip
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nv126_chipset = {
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.name = "GM206",
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// .bar = gf100_bar_new,
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.bar = gf100_bar_new,
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// .bios = nvkm_bios_new,
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// .bus = gf100_bus_new,
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// .devinit = gm204_devinit_new,
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@ -1959,7 +1959,7 @@ nv126_chipset = {
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static const struct nvkm_device_chip
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nv12b_chipset = {
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.name = "GM20B",
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// .bar = gk20a_bar_new,
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.bar = gk20a_bar_new,
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// .bus = gf100_bus_new,
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// .fb = gk20a_fb_new,
|
||||
// .fuse = gm107_fuse_new,
|
||||
|
||||
@ -44,7 +44,6 @@ gf100_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
|
||||
@ -76,7 +75,6 @@ gf100_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
|
||||
@ -108,7 +106,6 @@ gf100_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
|
||||
@ -139,7 +136,6 @@ gf100_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
|
||||
@ -171,7 +167,6 @@ gf100_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
|
||||
@ -202,7 +197,6 @@ gf100_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
|
||||
@ -233,7 +227,6 @@ gf100_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf100_dmaeng_oclass;
|
||||
@ -265,7 +258,6 @@ gf100_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
||||
@ -296,7 +288,6 @@ gf100_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;
|
||||
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
|
||||
|
||||
@ -44,7 +44,6 @@ gk104_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
||||
@ -77,7 +76,6 @@ gk104_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
||||
@ -110,7 +108,6 @@ gk104_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
||||
@ -137,7 +134,6 @@ gk104_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
|
||||
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
|
||||
@ -164,7 +160,6 @@ gk104_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
||||
@ -197,7 +192,6 @@ gk104_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
||||
@ -230,7 +224,6 @@ gk104_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
||||
@ -262,7 +255,6 @@ gk104_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
||||
|
||||
@ -44,7 +44,6 @@ gm100_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
|
||||
|
||||
#if 0
|
||||
@ -87,7 +86,6 @@ gm100_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
|
||||
#if 0
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
@ -127,7 +125,6 @@ gm100_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
|
||||
#if 0
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
@ -158,7 +155,6 @@ gm100_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass;
|
||||
device->oclass[NVDEV_ENGINE_SW ] = gf100_sw_oclass;
|
||||
|
||||
@ -42,7 +42,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
|
||||
@ -67,7 +66,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
||||
@ -95,7 +93,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
||||
@ -123,7 +120,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
||||
@ -151,7 +147,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
||||
@ -179,7 +174,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
||||
@ -207,7 +201,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
||||
@ -235,7 +228,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = g84_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
||||
@ -263,7 +255,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
||||
@ -291,7 +282,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = mcp77_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
device->oclass[NVDEV_ENGINE_FIFO ] = g84_fifo_oclass;
|
||||
@ -319,7 +309,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
@ -349,7 +338,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
@ -378,7 +366,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = gt215_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
@ -407,7 +394,6 @@ nv50_identify(struct nvkm_device *device)
|
||||
device->oclass[NVDEV_SUBDEV_FB ] = mcp89_fb_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
|
||||
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
|
||||
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
|
||||
|
||||
@ -632,7 +632,7 @@ gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = bar->umap(bar, 128 * 0x1000, 12, &fifo->user.bar);
|
||||
ret = nvkm_bar_umap(bar, 128 * 0x1000, 12, &fifo->user.bar);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
||||
@ -755,7 +755,7 @@ gk104_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = bar->umap(bar, impl->channels * 0x200, 12, &fifo->user.bar);
|
||||
ret = nvkm_bar_umap(bar, impl->channels * 0x200, 12, &fifo->user.bar);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
||||
@ -41,11 +41,10 @@ gf100_sw_chan_vblsem_release(struct nvkm_notify *notify)
|
||||
container_of(notify, typeof(*chan), vblank.notify[notify->index]);
|
||||
struct nvkm_sw *sw = chan->base.sw;
|
||||
struct nvkm_device *device = sw->engine.subdev.device;
|
||||
struct nvkm_bar *bar = device->bar;
|
||||
u32 inst = chan->base.fifo->inst->addr >> 12;
|
||||
|
||||
nvkm_wr32(device, 0x001718, 0x80000000 | inst);
|
||||
bar->flush(bar);
|
||||
nvkm_bar_flush(device->bar);
|
||||
nvkm_wr32(device, 0x06000c, upper_32_bits(chan->vblank.offset));
|
||||
nvkm_wr32(device, 0x060010, lower_32_bits(chan->vblank.offset));
|
||||
nvkm_wr32(device, 0x060014, chan->vblank.value);
|
||||
|
||||
@ -42,11 +42,10 @@ nv50_sw_chan_vblsem_release(struct nvkm_notify *notify)
|
||||
container_of(notify, typeof(*chan), vblank.notify[notify->index]);
|
||||
struct nvkm_sw *sw = chan->base.sw;
|
||||
struct nvkm_device *device = sw->engine.subdev.device;
|
||||
struct nvkm_bar *bar = device->bar;
|
||||
|
||||
nvkm_wr32(device, 0x001704, chan->base.fifo->inst->addr >> 12);
|
||||
nvkm_wr32(device, 0x001710, 0x80000000 | chan->vblank.ctxdma);
|
||||
bar->flush(bar);
|
||||
nvkm_bar_flush(device->bar);
|
||||
|
||||
if (nv_device(sw)->chipset == 0x50) {
|
||||
nvkm_wr32(device, 0x001570, chan->vblank.offset);
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
nvkm-y += nvkm/subdev/bar/base.o
|
||||
nvkm-y += nvkm/subdev/bar/nv50.o
|
||||
nvkm-y += nvkm/subdev/bar/g84.o
|
||||
nvkm-y += nvkm/subdev/bar/gf100.o
|
||||
nvkm-y += nvkm/subdev/bar/gk20a.o
|
||||
|
||||
@ -23,23 +23,61 @@
|
||||
*/
|
||||
#include "priv.h"
|
||||
|
||||
void
|
||||
nvkm_bar_flush(struct nvkm_bar *bar)
|
||||
{
|
||||
if (bar && bar->func->flush)
|
||||
bar->func->flush(bar);
|
||||
}
|
||||
|
||||
struct nvkm_vm *
|
||||
nvkm_bar_kmap(struct nvkm_bar *bar)
|
||||
{
|
||||
/* disallow kmap() until after vm has been bootstrapped */
|
||||
if (bar && bar->func->kmap && bar->subdev.oneinit)
|
||||
return bar->func->kmap(bar);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
int
|
||||
nvkm_bar_create_(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, int length, void **pobject)
|
||||
nvkm_bar_umap(struct nvkm_bar *bar, u64 size, int type, struct nvkm_vma *vma)
|
||||
{
|
||||
return nvkm_subdev_create_(parent, engine, oclass, 0, "BARCTL",
|
||||
"bar", length, pobject);
|
||||
return bar->func->umap(bar, size, type, vma);
|
||||
}
|
||||
|
||||
void
|
||||
nvkm_bar_destroy(struct nvkm_bar *bar)
|
||||
static int
|
||||
nvkm_bar_oneinit(struct nvkm_subdev *subdev)
|
||||
{
|
||||
nvkm_subdev_destroy(&bar->subdev);
|
||||
struct nvkm_bar *bar = nvkm_bar(subdev);
|
||||
return bar->func->oneinit(bar);
|
||||
}
|
||||
|
||||
void
|
||||
_nvkm_bar_dtor(struct nvkm_object *object)
|
||||
static int
|
||||
nvkm_bar_init(struct nvkm_subdev *subdev)
|
||||
{
|
||||
struct nvkm_bar *bar = (void *)object;
|
||||
nvkm_bar_destroy(bar);
|
||||
struct nvkm_bar *bar = nvkm_bar(subdev);
|
||||
return bar->func->init(bar);
|
||||
}
|
||||
|
||||
static void *
|
||||
nvkm_bar_dtor(struct nvkm_subdev *subdev)
|
||||
{
|
||||
struct nvkm_bar *bar = nvkm_bar(subdev);
|
||||
return bar->func->dtor(bar);
|
||||
}
|
||||
|
||||
static const struct nvkm_subdev_func
|
||||
nvkm_bar = {
|
||||
.dtor = nvkm_bar_dtor,
|
||||
.oneinit = nvkm_bar_oneinit,
|
||||
.init = nvkm_bar_init,
|
||||
};
|
||||
|
||||
void
|
||||
nvkm_bar_ctor(const struct nvkm_bar_func *func, struct nvkm_device *device,
|
||||
int index, struct nvkm_bar *bar)
|
||||
{
|
||||
nvkm_subdev_ctor(&nvkm_bar, device, index, 0, &bar->subdev);
|
||||
bar->func = func;
|
||||
spin_lock_init(&bar->lock);
|
||||
}
|
||||
|
||||
56
drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c
Normal file
56
drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.c
Normal file
@ -0,0 +1,56 @@
|
||||
/*
|
||||
* Copyright 2015 Red Hat Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: Ben Skeggs <bskeggs@redhat.com>
|
||||
*/
|
||||
#include "nv50.h"
|
||||
|
||||
#include <subdev/timer.h>
|
||||
|
||||
void
|
||||
g84_bar_flush(struct nvkm_bar *bar)
|
||||
{
|
||||
struct nvkm_device *device = bar->subdev.device;
|
||||
unsigned long flags;
|
||||
spin_lock_irqsave(&bar->lock, flags);
|
||||
nvkm_wr32(device, 0x070000, 0x00000001);
|
||||
nvkm_msec(device, 2000,
|
||||
if (!(nvkm_rd32(device, 0x070000) & 0x00000002))
|
||||
break;
|
||||
);
|
||||
spin_unlock_irqrestore(&bar->lock, flags);
|
||||
}
|
||||
|
||||
static const struct nvkm_bar_func
|
||||
g84_bar_func = {
|
||||
.dtor = nv50_bar_dtor,
|
||||
.oneinit = nv50_bar_oneinit,
|
||||
.init = nv50_bar_init,
|
||||
.kmap = nv50_bar_kmap,
|
||||
.umap = nv50_bar_umap,
|
||||
.flush = g84_bar_flush,
|
||||
};
|
||||
|
||||
int
|
||||
g84_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar)
|
||||
{
|
||||
return nv50_bar_new_(&g84_bar_func, device, index, 0x200, pbar);
|
||||
}
|
||||
@ -21,51 +21,30 @@
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "priv.h"
|
||||
#include "gf100.h"
|
||||
|
||||
#include <core/gpuobj.h>
|
||||
#include <subdev/fb.h>
|
||||
#include <subdev/mmu.h>
|
||||
|
||||
struct gf100_bar_vm {
|
||||
struct nvkm_memory *mem;
|
||||
struct nvkm_gpuobj *pgd;
|
||||
struct nvkm_vm *vm;
|
||||
};
|
||||
|
||||
struct gf100_bar {
|
||||
struct nvkm_bar base;
|
||||
spinlock_t lock;
|
||||
struct gf100_bar_vm bar[2];
|
||||
};
|
||||
|
||||
static struct nvkm_vm *
|
||||
gf100_bar_kmap(struct nvkm_bar *obj)
|
||||
gf100_bar_kmap(struct nvkm_bar *base)
|
||||
{
|
||||
struct gf100_bar *bar = container_of(obj, typeof(*bar), base);
|
||||
return bar->bar[0].vm;
|
||||
return gf100_bar(base)->bar[0].vm;
|
||||
}
|
||||
|
||||
static int
|
||||
gf100_bar_umap(struct nvkm_bar *obj, u64 size, int type, struct nvkm_vma *vma)
|
||||
int
|
||||
gf100_bar_umap(struct nvkm_bar *base, u64 size, int type, struct nvkm_vma *vma)
|
||||
{
|
||||
struct gf100_bar *bar = container_of(obj, typeof(*bar), base);
|
||||
struct gf100_bar *bar = gf100_bar(base);
|
||||
return nvkm_vm_get(bar->bar[1].vm, size, type, NV_MEM_ACCESS_RW, vma);
|
||||
}
|
||||
|
||||
static void
|
||||
gf100_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma)
|
||||
{
|
||||
nvkm_vm_unmap(vma);
|
||||
nvkm_vm_put(vma);
|
||||
}
|
||||
|
||||
|
||||
static int
|
||||
gf100_bar_ctor_vm(struct gf100_bar *bar, struct gf100_bar_vm *bar_vm,
|
||||
struct lock_class_key *key, int bar_nr)
|
||||
{
|
||||
struct nvkm_device *device = nv_device(&bar->base);
|
||||
struct nvkm_device *device = bar->base.subdev.device;
|
||||
struct nvkm_vm *vm;
|
||||
resource_size_t bar_len;
|
||||
int ret;
|
||||
@ -92,8 +71,10 @@ gf100_bar_ctor_vm(struct gf100_bar *bar, struct gf100_bar_vm *bar_vm,
|
||||
*/
|
||||
if (bar_nr == 3) {
|
||||
ret = nvkm_vm_boot(vm, bar_len);
|
||||
if (ret)
|
||||
if (ret) {
|
||||
nvkm_vm_ref(NULL, &vm, NULL);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ret = nvkm_vm_ref(vm, &bar_vm->vm, bar_vm->pgd);
|
||||
@ -111,28 +92,15 @@ gf100_bar_ctor_vm(struct gf100_bar *bar, struct gf100_bar_vm *bar_vm,
|
||||
}
|
||||
|
||||
int
|
||||
gf100_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
gf100_bar_oneinit(struct nvkm_bar *base)
|
||||
{
|
||||
static struct lock_class_key bar1_lock;
|
||||
static struct lock_class_key bar3_lock;
|
||||
struct nvkm_device *device = nv_device(parent);
|
||||
struct gf100_bar *bar;
|
||||
bool has_bar3 = nv_device_resource_len(device, 3) != 0;
|
||||
struct gf100_bar *bar = gf100_bar(base);
|
||||
int ret;
|
||||
|
||||
ret = nvkm_bar_create(parent, engine, oclass, &bar);
|
||||
*pobject = nv_object(bar);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
device->bar = &bar->base;
|
||||
bar->base.flush = g84_bar_flush;
|
||||
spin_lock_init(&bar->lock);
|
||||
|
||||
/* BAR3 */
|
||||
if (has_bar3) {
|
||||
if (bar->base.func->kmap) {
|
||||
ret = gf100_bar_ctor_vm(bar, &bar->bar[0], &bar3_lock, 3);
|
||||
if (ret)
|
||||
return ret;
|
||||
@ -143,43 +111,15 @@ gf100_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (has_bar3)
|
||||
bar->base.kmap = gf100_bar_kmap;
|
||||
bar->base.umap = gf100_bar_umap;
|
||||
bar->base.unmap = gf100_bar_unmap;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
gf100_bar_dtor(struct nvkm_object *object)
|
||||
{
|
||||
struct gf100_bar *bar = (void *)object;
|
||||
|
||||
nvkm_vm_ref(NULL, &bar->bar[1].vm, bar->bar[1].pgd);
|
||||
nvkm_gpuobj_del(&bar->bar[1].pgd);
|
||||
nvkm_memory_del(&bar->bar[1].mem);
|
||||
|
||||
if (bar->bar[0].vm) {
|
||||
nvkm_memory_del(&bar->bar[0].vm->pgt[0].mem[0]);
|
||||
nvkm_vm_ref(NULL, &bar->bar[0].vm, bar->bar[0].pgd);
|
||||
}
|
||||
nvkm_gpuobj_del(&bar->bar[0].pgd);
|
||||
nvkm_memory_del(&bar->bar[0].mem);
|
||||
|
||||
nvkm_bar_destroy(&bar->base);
|
||||
}
|
||||
|
||||
int
|
||||
gf100_bar_init(struct nvkm_object *object)
|
||||
gf100_bar_init(struct nvkm_bar *base)
|
||||
{
|
||||
struct gf100_bar *bar = (void *)object;
|
||||
struct gf100_bar *bar = gf100_bar(base);
|
||||
struct nvkm_device *device = bar->base.subdev.device;
|
||||
u32 addr;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_bar_init(&bar->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nvkm_mask(device, 0x000200, 0x00000100, 0x00000000);
|
||||
nvkm_mask(device, 0x000200, 0x00000100, 0x00000100);
|
||||
@ -195,13 +135,48 @@ gf100_bar_init(struct nvkm_object *object)
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct nvkm_oclass
|
||||
gf100_bar_oclass = {
|
||||
.handle = NV_SUBDEV(BAR, 0xc0),
|
||||
.ofuncs = &(struct nvkm_ofuncs) {
|
||||
.ctor = gf100_bar_ctor,
|
||||
.dtor = gf100_bar_dtor,
|
||||
.init = gf100_bar_init,
|
||||
.fini = _nvkm_bar_fini,
|
||||
},
|
||||
void *
|
||||
gf100_bar_dtor(struct nvkm_bar *base)
|
||||
{
|
||||
struct gf100_bar *bar = gf100_bar(base);
|
||||
|
||||
nvkm_vm_ref(NULL, &bar->bar[1].vm, bar->bar[1].pgd);
|
||||
nvkm_gpuobj_del(&bar->bar[1].pgd);
|
||||
nvkm_memory_del(&bar->bar[1].mem);
|
||||
|
||||
if (bar->bar[0].vm) {
|
||||
nvkm_memory_del(&bar->bar[0].vm->pgt[0].mem[0]);
|
||||
nvkm_vm_ref(NULL, &bar->bar[0].vm, bar->bar[0].pgd);
|
||||
}
|
||||
nvkm_gpuobj_del(&bar->bar[0].pgd);
|
||||
nvkm_memory_del(&bar->bar[0].mem);
|
||||
return bar;
|
||||
}
|
||||
|
||||
int
|
||||
gf100_bar_new_(const struct nvkm_bar_func *func, struct nvkm_device *device,
|
||||
int index, struct nvkm_bar **pbar)
|
||||
{
|
||||
struct gf100_bar *bar;
|
||||
if (!(bar = kzalloc(sizeof(*bar), GFP_KERNEL)))
|
||||
return -ENOMEM;
|
||||
nvkm_bar_ctor(func, device, index, &bar->base);
|
||||
*pbar = &bar->base;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct nvkm_bar_func
|
||||
gf100_bar_func = {
|
||||
.dtor = gf100_bar_dtor,
|
||||
.oneinit = gf100_bar_oneinit,
|
||||
.init = gf100_bar_init,
|
||||
.kmap = gf100_bar_kmap,
|
||||
.umap = gf100_bar_umap,
|
||||
.flush = g84_bar_flush,
|
||||
};
|
||||
|
||||
int
|
||||
gf100_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar)
|
||||
{
|
||||
return gf100_bar_new_(&gf100_bar_func, device, index, pbar);
|
||||
}
|
||||
|
||||
23
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h
Normal file
23
drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.h
Normal file
@ -0,0 +1,23 @@
|
||||
#ifndef __GF100_BAR_H__
|
||||
#define __GF100_BAR_H__
|
||||
#define gf100_bar(p) container_of((p), struct gf100_bar, base)
|
||||
#include "priv.h"
|
||||
|
||||
struct gf100_bar_vm {
|
||||
struct nvkm_memory *mem;
|
||||
struct nvkm_gpuobj *pgd;
|
||||
struct nvkm_vm *vm;
|
||||
};
|
||||
|
||||
struct gf100_bar {
|
||||
struct nvkm_bar base;
|
||||
struct gf100_bar_vm bar[2];
|
||||
};
|
||||
|
||||
int gf100_bar_new_(const struct nvkm_bar_func *, struct nvkm_device *,
|
||||
int, struct nvkm_bar **);
|
||||
void *gf100_bar_dtor(struct nvkm_bar *);
|
||||
int gf100_bar_oneinit(struct nvkm_bar *);
|
||||
int gf100_bar_init(struct nvkm_bar *);
|
||||
int gf100_bar_umap(struct nvkm_bar *, u64, int, struct nvkm_vma *);
|
||||
#endif
|
||||
@ -19,32 +19,22 @@
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#include "priv.h"
|
||||
#include "gf100.h"
|
||||
|
||||
static const struct nvkm_bar_func
|
||||
gk20a_bar_func = {
|
||||
.dtor = gf100_bar_dtor,
|
||||
.oneinit = gf100_bar_oneinit,
|
||||
.init = gf100_bar_init,
|
||||
.umap = gf100_bar_umap,
|
||||
.flush = g84_bar_flush,
|
||||
};
|
||||
|
||||
int
|
||||
gk20a_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
gk20a_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar)
|
||||
{
|
||||
struct nvkm_bar *bar;
|
||||
int ret;
|
||||
|
||||
ret = gf100_bar_ctor(parent, engine, oclass, data, size, pobject);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
bar = (struct nvkm_bar *)*pobject;
|
||||
bar->iomap_uncached = true;
|
||||
return 0;
|
||||
int ret = gf100_bar_new_(&gk20a_bar_func, device, index, pbar);
|
||||
if (ret == 0)
|
||||
(*pbar)->iomap_uncached = true;
|
||||
return ret;
|
||||
}
|
||||
|
||||
struct nvkm_oclass
|
||||
gk20a_bar_oclass = {
|
||||
.handle = NV_SUBDEV(BAR, 0xea),
|
||||
.ofuncs = &(struct nvkm_ofuncs) {
|
||||
.ctor = gk20a_bar_ctor,
|
||||
.dtor = gf100_bar_dtor,
|
||||
.init = gf100_bar_init,
|
||||
.fini = _nvkm_bar_fini,
|
||||
},
|
||||
};
|
||||
|
||||
@ -21,100 +21,57 @@
|
||||
*
|
||||
* Authors: Ben Skeggs
|
||||
*/
|
||||
#include "priv.h"
|
||||
#include "nv50.h"
|
||||
|
||||
#include <core/gpuobj.h>
|
||||
#include <subdev/fb.h>
|
||||
#include <subdev/mmu.h>
|
||||
#include <subdev/timer.h>
|
||||
|
||||
struct nv50_bar {
|
||||
struct nvkm_bar base;
|
||||
spinlock_t lock;
|
||||
struct nvkm_gpuobj *mem;
|
||||
struct nvkm_gpuobj *pad;
|
||||
struct nvkm_gpuobj *pgd;
|
||||
struct nvkm_vm *bar1_vm;
|
||||
struct nvkm_gpuobj *bar1;
|
||||
struct nvkm_vm *bar3_vm;
|
||||
struct nvkm_gpuobj *bar3;
|
||||
};
|
||||
|
||||
static struct nvkm_vm *
|
||||
nv50_bar_kmap(struct nvkm_bar *obj)
|
||||
struct nvkm_vm *
|
||||
nv50_bar_kmap(struct nvkm_bar *base)
|
||||
{
|
||||
struct nv50_bar *bar = container_of(obj, typeof(*bar), base);
|
||||
return bar->bar3_vm;
|
||||
return nv50_bar(base)->bar3_vm;
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_bar_umap(struct nvkm_bar *obj, u64 size, int type, struct nvkm_vma *vma)
|
||||
int
|
||||
nv50_bar_umap(struct nvkm_bar *base, u64 size, int type, struct nvkm_vma *vma)
|
||||
{
|
||||
struct nv50_bar *bar = container_of(obj, typeof(*bar), base);
|
||||
struct nv50_bar *bar = nv50_bar(base);
|
||||
return nvkm_vm_get(bar->bar1_vm, size, type, NV_MEM_ACCESS_RW, vma);
|
||||
}
|
||||
|
||||
static void
|
||||
nv50_bar_unmap(struct nvkm_bar *bar, struct nvkm_vma *vma)
|
||||
nv50_bar_flush(struct nvkm_bar *base)
|
||||
{
|
||||
nvkm_vm_unmap(vma);
|
||||
nvkm_vm_put(vma);
|
||||
}
|
||||
|
||||
static void
|
||||
nv50_bar_flush(struct nvkm_bar *obj)
|
||||
{
|
||||
struct nv50_bar *bar = container_of(obj, typeof(*bar), base);
|
||||
struct nv50_bar *bar = nv50_bar(base);
|
||||
struct nvkm_device *device = bar->base.subdev.device;
|
||||
unsigned long flags;
|
||||
spin_lock_irqsave(&bar->lock, flags);
|
||||
spin_lock_irqsave(&bar->base.lock, flags);
|
||||
nvkm_wr32(device, 0x00330c, 0x00000001);
|
||||
nvkm_msec(device, 2000,
|
||||
if (!(nvkm_rd32(device, 0x00330c) & 0x00000002))
|
||||
break;
|
||||
);
|
||||
spin_unlock_irqrestore(&bar->lock, flags);
|
||||
spin_unlock_irqrestore(&bar->base.lock, flags);
|
||||
}
|
||||
|
||||
void
|
||||
g84_bar_flush(struct nvkm_bar *obj)
|
||||
int
|
||||
nv50_bar_oneinit(struct nvkm_bar *base)
|
||||
{
|
||||
struct nv50_bar *bar = container_of(obj, typeof(*bar), base);
|
||||
struct nv50_bar *bar = nv50_bar(base);
|
||||
struct nvkm_device *device = bar->base.subdev.device;
|
||||
unsigned long flags;
|
||||
spin_lock_irqsave(&bar->lock, flags);
|
||||
nvkm_wr32(device, 0x070000, 0x00000001);
|
||||
nvkm_msec(device, 2000,
|
||||
if (!(nvkm_rd32(device, 0x070000) & 0x00000002))
|
||||
break;
|
||||
);
|
||||
spin_unlock_irqrestore(&bar->lock, flags);
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
struct nvkm_oclass *oclass, void *data, u32 size,
|
||||
struct nvkm_object **pobject)
|
||||
{
|
||||
static struct lock_class_key bar1_lock;
|
||||
static struct lock_class_key bar3_lock;
|
||||
struct nvkm_device *device = nv_device(parent);
|
||||
struct nvkm_vm *vm;
|
||||
struct nv50_bar *bar;
|
||||
u64 start, limit;
|
||||
int ret;
|
||||
|
||||
ret = nvkm_bar_create(parent, engine, oclass, &bar);
|
||||
*pobject = nv_object(bar);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = nvkm_gpuobj_new(device, 0x20000, 0, false, NULL, &bar->mem);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = nvkm_gpuobj_new(device, (device->chipset == 0x50) ?
|
||||
0x1400 : 0x200, 0, false, bar->mem,
|
||||
ret = nvkm_gpuobj_new(device, bar->pgd_addr, 0, false, bar->mem,
|
||||
&bar->pad);
|
||||
if (ret)
|
||||
return ret;
|
||||
@ -184,45 +141,15 @@ nv50_bar_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
|
||||
nvkm_wo32(bar->bar1, 0x10, 0x00000000);
|
||||
nvkm_wo32(bar->bar1, 0x14, 0x00000000);
|
||||
nvkm_done(bar->bar1);
|
||||
|
||||
bar->base.kmap = nv50_bar_kmap;
|
||||
bar->base.umap = nv50_bar_umap;
|
||||
bar->base.unmap = nv50_bar_unmap;
|
||||
if (device->chipset == 0x50)
|
||||
bar->base.flush = nv50_bar_flush;
|
||||
else
|
||||
bar->base.flush = g84_bar_flush;
|
||||
spin_lock_init(&bar->lock);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
nv50_bar_dtor(struct nvkm_object *object)
|
||||
int
|
||||
nv50_bar_init(struct nvkm_bar *base)
|
||||
{
|
||||
struct nv50_bar *bar = (void *)object;
|
||||
nvkm_gpuobj_del(&bar->bar1);
|
||||
nvkm_vm_ref(NULL, &bar->bar1_vm, bar->pgd);
|
||||
nvkm_gpuobj_del(&bar->bar3);
|
||||
if (bar->bar3_vm) {
|
||||
nvkm_memory_del(&bar->bar3_vm->pgt[0].mem[0]);
|
||||
nvkm_vm_ref(NULL, &bar->bar3_vm, bar->pgd);
|
||||
}
|
||||
nvkm_gpuobj_del(&bar->pgd);
|
||||
nvkm_gpuobj_del(&bar->pad);
|
||||
nvkm_gpuobj_del(&bar->mem);
|
||||
nvkm_bar_destroy(&bar->base);
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_bar_init(struct nvkm_object *object)
|
||||
{
|
||||
struct nv50_bar *bar = (void *)object;
|
||||
struct nv50_bar *bar = nv50_bar(base);
|
||||
struct nvkm_device *device = bar->base.subdev.device;
|
||||
int ret, i;
|
||||
|
||||
ret = nvkm_bar_init(&bar->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
int i;
|
||||
|
||||
nvkm_mask(device, 0x000200, 0x00000100, 0x00000000);
|
||||
nvkm_mask(device, 0x000200, 0x00000100, 0x00000100);
|
||||
@ -242,20 +169,48 @@ nv50_bar_init(struct nvkm_object *object)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
nv50_bar_fini(struct nvkm_object *object, bool suspend)
|
||||
void *
|
||||
nv50_bar_dtor(struct nvkm_bar *base)
|
||||
{
|
||||
struct nv50_bar *bar = (void *)object;
|
||||
return nvkm_bar_fini(&bar->base, suspend);
|
||||
struct nv50_bar *bar = nv50_bar(base);
|
||||
nvkm_gpuobj_del(&bar->bar1);
|
||||
nvkm_vm_ref(NULL, &bar->bar1_vm, bar->pgd);
|
||||
nvkm_gpuobj_del(&bar->bar3);
|
||||
if (bar->bar3_vm) {
|
||||
nvkm_memory_del(&bar->bar3_vm->pgt[0].mem[0]);
|
||||
nvkm_vm_ref(NULL, &bar->bar3_vm, bar->pgd);
|
||||
}
|
||||
nvkm_gpuobj_del(&bar->pgd);
|
||||
nvkm_gpuobj_del(&bar->pad);
|
||||
nvkm_gpuobj_del(&bar->mem);
|
||||
return bar;
|
||||
}
|
||||
|
||||
struct nvkm_oclass
|
||||
nv50_bar_oclass = {
|
||||
.handle = NV_SUBDEV(BAR, 0x50),
|
||||
.ofuncs = &(struct nvkm_ofuncs) {
|
||||
.ctor = nv50_bar_ctor,
|
||||
.dtor = nv50_bar_dtor,
|
||||
.init = nv50_bar_init,
|
||||
.fini = nv50_bar_fini,
|
||||
},
|
||||
int
|
||||
nv50_bar_new_(const struct nvkm_bar_func *func, struct nvkm_device *device,
|
||||
int index, u32 pgd_addr, struct nvkm_bar **pbar)
|
||||
{
|
||||
struct nv50_bar *bar;
|
||||
if (!(bar = kzalloc(sizeof(*bar), GFP_KERNEL)))
|
||||
return -ENOMEM;
|
||||
nvkm_bar_ctor(func, device, index, &bar->base);
|
||||
bar->pgd_addr = pgd_addr;
|
||||
*pbar = &bar->base;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct nvkm_bar_func
|
||||
nv50_bar_func = {
|
||||
.dtor = nv50_bar_dtor,
|
||||
.oneinit = nv50_bar_oneinit,
|
||||
.init = nv50_bar_init,
|
||||
.kmap = nv50_bar_kmap,
|
||||
.umap = nv50_bar_umap,
|
||||
.flush = nv50_bar_flush,
|
||||
};
|
||||
|
||||
int
|
||||
nv50_bar_new(struct nvkm_device *device, int index, struct nvkm_bar **pbar)
|
||||
{
|
||||
return nv50_bar_new_(&nv50_bar_func, device, index, 0x1400, pbar);
|
||||
}
|
||||
|
||||
26
drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h
Normal file
26
drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.h
Normal file
@ -0,0 +1,26 @@
|
||||
#ifndef __NV50_BAR_H__
|
||||
#define __NV50_BAR_H__
|
||||
#define nv50_bar(p) container_of((p), struct nv50_bar, base)
|
||||
#include "priv.h"
|
||||
|
||||
struct nv50_bar {
|
||||
struct nvkm_bar base;
|
||||
u32 pgd_addr;
|
||||
struct nvkm_gpuobj *mem;
|
||||
struct nvkm_gpuobj *pad;
|
||||
struct nvkm_gpuobj *pgd;
|
||||
struct nvkm_vm *bar1_vm;
|
||||
struct nvkm_gpuobj *bar1;
|
||||
struct nvkm_vm *bar3_vm;
|
||||
struct nvkm_gpuobj *bar3;
|
||||
};
|
||||
|
||||
int nv50_bar_new_(const struct nvkm_bar_func *, struct nvkm_device *,
|
||||
int, u32 pgd_addr, struct nvkm_bar **);
|
||||
void *nv50_bar_dtor(struct nvkm_bar *);
|
||||
int nv50_bar_oneinit(struct nvkm_bar *);
|
||||
int nv50_bar_init(struct nvkm_bar *);
|
||||
struct nvkm_vm *nv50_bar_kmap(struct nvkm_bar *);
|
||||
int nv50_bar_umap(struct nvkm_bar *, u64, int, struct nvkm_vma *);
|
||||
void nv50_bar_unmap(struct nvkm_bar *, struct nvkm_vma *);
|
||||
#endif
|
||||
@ -1,27 +1,19 @@
|
||||
#ifndef __NVKM_BAR_PRIV_H__
|
||||
#define __NVKM_BAR_PRIV_H__
|
||||
#define nvkm_bar(p) container_of((p), struct nvkm_bar, subdev)
|
||||
#include <subdev/bar.h>
|
||||
|
||||
#define nvkm_bar_create(p,e,o,d) \
|
||||
nvkm_bar_create_((p), (e), (o), sizeof(**d), (void **)d)
|
||||
#define nvkm_bar_init(p) \
|
||||
nvkm_subdev_init_old(&(p)->subdev)
|
||||
#define nvkm_bar_fini(p,s) \
|
||||
nvkm_subdev_fini_old(&(p)->subdev, (s))
|
||||
void nvkm_bar_ctor(const struct nvkm_bar_func *, struct nvkm_device *,
|
||||
int, struct nvkm_bar *);
|
||||
|
||||
int nvkm_bar_create_(struct nvkm_object *, struct nvkm_object *,
|
||||
struct nvkm_oclass *, int, void **);
|
||||
void nvkm_bar_destroy(struct nvkm_bar *);
|
||||
|
||||
void _nvkm_bar_dtor(struct nvkm_object *);
|
||||
#define _nvkm_bar_init _nvkm_subdev_init
|
||||
#define _nvkm_bar_fini _nvkm_subdev_fini
|
||||
struct nvkm_bar_func {
|
||||
void *(*dtor)(struct nvkm_bar *);
|
||||
int (*oneinit)(struct nvkm_bar *);
|
||||
int (*init)(struct nvkm_bar *);
|
||||
struct nvkm_vm *(*kmap)(struct nvkm_bar *);
|
||||
int (*umap)(struct nvkm_bar *, u64 size, int type, struct nvkm_vma *);
|
||||
void (*flush)(struct nvkm_bar *);
|
||||
};
|
||||
|
||||
void g84_bar_flush(struct nvkm_bar *);
|
||||
|
||||
int gf100_bar_ctor(struct nvkm_object *, struct nvkm_object *,
|
||||
struct nvkm_oclass *, void *, u32,
|
||||
struct nvkm_object **);
|
||||
void gf100_bar_dtor(struct nvkm_object *);
|
||||
int gf100_bar_init(struct nvkm_object *);
|
||||
#endif
|
||||
|
||||
@ -65,9 +65,7 @@ static void
|
||||
nvkm_instobj_release(struct nvkm_memory *memory)
|
||||
{
|
||||
struct nvkm_instobj *iobj = nvkm_instobj(memory);
|
||||
struct nvkm_bar *bar = iobj->imem->subdev.device->bar;
|
||||
if (bar && bar->flush)
|
||||
bar->flush(bar);
|
||||
nvkm_bar_flush(iobj->imem->subdev.device->bar);
|
||||
}
|
||||
|
||||
static void __iomem *
|
||||
|
||||
@ -111,7 +111,7 @@ nv50_instobj_acquire(struct nvkm_memory *memory)
|
||||
struct nvkm_vm *vm;
|
||||
unsigned long flags;
|
||||
|
||||
if (!iobj->map && bar && bar->kmap && (vm = bar->kmap(bar)))
|
||||
if (!iobj->map && (vm = nvkm_bar_kmap(bar)))
|
||||
nvkm_memory_boot(memory, vm);
|
||||
if (!IS_ERR_OR_NULL(iobj->map))
|
||||
return iobj->map;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user