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- Drop the __weak attribute from a function prototype as it otherwise
leads to the function getting replaced by a dummy stub - Fix the umask value setup of the frontend event as former is different on two Intel cores -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmSYChQACgkQEsHwGGHe VUq7cQ/7BSDauaiRGPvovvolPUarJ6Ezidrq0y24p92eHjqjfiZLZVR53AItTeFr 5Naib991Wy7PdqvEgBElNlWdTvhefdSXSOdII7Zo8bHRtJAFAgbIaIZN6W2qRlDO v9scHnwjIbkjIB6mOd4zn0Ttwjnk3cvArSgxhmIa5K1EY8C7LG8Npviadi6tkhxF /0Zw+K/X7mmLpnaKbvKu+hY+0IxJBnpO319xk28XxrugZLbdykjuhCiLwJ4P6QxY FbrDqMEp1PjLQQ725sJBwVYQ+bEfBGT7qt5A6gBjglFstsPsYOhyfSPfk4rh7mvK DdtW11mfLyAlKSlb6GtXWajFt2KeTclNHnrpgI7Qp11S0CyeXvl88okSjYvLNeJn PKT6fwDyhiE35hodkQGKQYqkOijTrwInIO8wsf3KbmyPLSbZINY0boNzjPp5eCZC lSNwUCPh/JiJewnmiLxbalpt/yLzQI/fII4ibBqxl7hAGwIb0KdjnZwM6tZ9AdoW M1PZtVZJr8j9N6yI7Y+Wbxj9oVoNmH5ie90lq0Di9niGpkytGoD2VSn5LIOVSZhR jmFbloTR+BUWh32e54NUKnVew2I1lkaklQK8OgECw2wRrFcNYx73tu0lOXJY1RwV zmsmQDnM56SxHFhpKcgy2c3vwKhR5HeuLd2MJtgtuB4KIje7row= =hJ0i -----END PGP SIGNATURE----- Merge tag 'perf_urgent_for_v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull perf fixes from Borislav Petkov: - Drop the __weak attribute from a function prototype as it otherwise leads to the function getting replaced by a dummy stub - Fix the umask value setup of the frontend event as former is different on two Intel cores * tag 'perf_urgent_for_v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/x86/intel: Fix the FRONTEND encoding on GNR and MTL perf/core: Drop __weak attribute from arch_perf_update_userpage() prototype
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commit
547cc9be86
@ -349,6 +349,16 @@ static struct event_constraint intel_spr_event_constraints[] = {
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EVENT_CONSTRAINT_END
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};
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static struct extra_reg intel_gnr_extra_regs[] __read_mostly = {
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INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
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INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
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INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
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INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),
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INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
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INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
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INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
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EVENT_EXTRA_END
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};
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EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
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EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
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@ -6496,6 +6506,7 @@ __init int intel_pmu_init(void)
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case INTEL_FAM6_SAPPHIRERAPIDS_X:
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case INTEL_FAM6_EMERALDRAPIDS_X:
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x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
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x86_pmu.extra_regs = intel_spr_extra_regs;
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fallthrough;
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case INTEL_FAM6_GRANITERAPIDS_X:
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case INTEL_FAM6_GRANITERAPIDS_D:
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@ -6506,7 +6517,8 @@ __init int intel_pmu_init(void)
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x86_pmu.event_constraints = intel_spr_event_constraints;
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x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;
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x86_pmu.extra_regs = intel_spr_extra_regs;
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if (!x86_pmu.extra_regs)
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x86_pmu.extra_regs = intel_gnr_extra_regs;
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x86_pmu.limit_period = spr_limit_period;
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x86_pmu.pebs_ept = 1;
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x86_pmu.pebs_aliases = NULL;
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@ -6650,6 +6662,7 @@ __init int intel_pmu_init(void)
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pmu->pebs_constraints = intel_grt_pebs_event_constraints;
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pmu->extra_regs = intel_grt_extra_regs;
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if (is_mtl(boot_cpu_data.x86_model)) {
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x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].extra_regs = intel_gnr_extra_regs;
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x86_pmu.pebs_latency_data = mtl_latency_data_small;
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extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
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mtl_hybrid_extra_attr_rtm : mtl_hybrid_extra_attr;
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@ -1845,9 +1845,9 @@ int perf_event_exit_cpu(unsigned int cpu);
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#define perf_event_exit_cpu NULL
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#endif
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extern void __weak arch_perf_update_userpage(struct perf_event *event,
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struct perf_event_mmap_page *userpg,
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u64 now);
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extern void arch_perf_update_userpage(struct perf_event *event,
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struct perf_event_mmap_page *userpg,
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u64 now);
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#ifdef CONFIG_MMU
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extern __weak u64 arch_perf_get_page_size(struct mm_struct *mm, unsigned long addr);
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