Kernel/linux-next
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git synced 2024-12-28 16:52:18 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

net: renesas: rswitch: enable only used MFWD features

Browse Source 
Currently, rswitch driver does not utilize most of MFWD forwarding
and processing features. It only uses port-based forwarding for ETHA
ports, and direct descriptor forwarding for GWCA port.

Update rswitch_fwd_init() to enable exactly that, and keep everything
else disabled.

Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Nikita Yushchenko 2024-12-09 11:24:11 +05:00 committed by David S. Miller
parent 65fb414c93
commit 54d3970548
2 changed files with 28 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
drivers/net/ethernet/renesas/rswitch.c
View File

@ -111,25 +111,35 @@ static void rswitch_top_init(struct rswitch_private *priv)
/* Forwarding engine block (MFWD) */
static void rswitch_fwd_init(struct rswitch_private *priv)
{
u32 all_ports_mask = GENMASK(RSWITCH_NUM_AGENTS - 1, 0);
unsigned int i;
/* For ETHA */
for (i = 0; i < RSWITCH_NUM_PORTS; i++) {
iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(i));
/* Start with empty configuration */
for (i = 0; i < RSWITCH_NUM_AGENTS; i++) {
/* Disable all port features */
iowrite32(0, priv->addr + FWPC0(i));
/* Disallow L3 forwarding and direct descriptor forwarding */
iowrite32(FIELD_PREP(FWCP1_LTHFW, all_ports_mask),
priv->addr + FWPC1(i));
/* Disallow L2 forwarding */
iowrite32(FIELD_PREP(FWCP2_LTWFW, all_ports_mask),
priv->addr + FWPC2(i));
/* Disallow port based forwarding */
iowrite32(0, priv->addr + FWPBFC(i));
}
for (i = 0; i < RSWITCH_NUM_PORTS; i++) {
/* For enabled ETHA ports, setup port based forwarding */
rswitch_for_each_enabled_port(priv, i) {
/* Port based forwarding from port i to GWCA port */
rswitch_modify(priv->addr, FWPBFC(i), FWPBFC_PBDV,
FIELD_PREP(FWPBFC_PBDV, BIT(priv->gwca.index)));
/* Within GWCA port, forward to Rx queue for port i */
iowrite32(priv->rdev[i]->rx_queue->index,
priv->addr + FWPBFCSDC(GWCA_INDEX, i));
iowrite32(BIT(priv->gwca.index), priv->addr + FWPBFC(i));
}
/* For GWCA */
iowrite32(FWPC0_DEFAULT, priv->addr + FWPC0(priv->gwca.index));
iowrite32(FWPC1_DDE, priv->addr + FWPC1(priv->gwca.index));
iowrite32(0, priv->addr + FWPBFC(priv->gwca.index));
iowrite32(GENMASK(RSWITCH_NUM_PORTS - 1, 0), priv->addr + FWPBFC(priv->gwca.index));
/* For GWCA port, allow direct descriptor forwarding */
rswitch_modify(priv->addr, FWPC1(priv->gwca.index), FWPC1_DDE, FWPC1_DDE);
}
/* Gateway CPU agent block (GWCA) */

14
drivers/net/ethernet/renesas/rswitch.h
View File

@ -12,6 +12,7 @@
#define RSWITCH_MAX_NUM_QUEUES 128
#define RSWITCH_NUM_AGENTS 5
#define RSWITCH_NUM_PORTS 3
#define rswitch_for_each_enabled_port(priv, i) \
for (i = 0; i < RSWITCH_NUM_PORTS; i++) \
@ -806,6 +807,7 @@ enum rswitch_gwca_mode {
#define CABPPFLC_INIT_VALUE 0x00800080
/* MFWD */
#define FWPC0(i) (FWPC00 + (i) * 0x10)
#define FWPC0_LTHTA BIT(0)
#define FWPC0_IP4UE BIT(3)
#define FWPC0_IP4TE BIT(4)
@ -819,15 +821,15 @@ enum rswitch_gwca_mode {
#define FWPC0_MACHMA BIT(27)
#define FWPC0_VLANSA BIT(28)
#define FWPC0(i) (FWPC00 + (i) * 0x10)
#define FWPC0_DEFAULT (FWPC0_LTHTA | FWPC0_IP4UE | FWPC0_IP4TE | \
FWPC0_IP4OE | FWPC0_L2SE | FWPC0_IP4EA | \
FWPC0_IPDSA | FWPC0_IPHLA | FWPC0_MACSDA | \
FWPC0_MACHLA | FWPC0_MACHMA | FWPC0_VLANSA)
#define FWPC1(i) (FWPC10 + (i) * 0x10)
#define FWCP1_LTHFW GENMASK(16 + (RSWITCH_NUM_AGENTS - 1), 16)
#define FWPC1_DDE BIT(0)
#define FWPBFC(i) (FWPBFC0 + (i) * 0x10)
#define FWPC2(i) (FWPC20 + (i) * 0x10)
#define FWCP2_LTWFW GENMASK(16 + (RSWITCH_NUM_AGENTS - 1), 16)
#define FWPBFC(i) (FWPBFC0 + (i) * 0x10)
#define FWPBFC_PBDV GENMASK(RSWITCH_NUM_AGENTS - 1, 0)
#define FWPBFCSDC(j, i) (FWPBFCSDC00 + (i) * 0x10 + (j) * 0x04)