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MIPS: Loongson 2 needs no hazard barriers.

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Quoting from Loongson2FUserGuide.pdf:

5.22.1 Hazards
The processor detects most of the pipeline hazards in hardware, including
CP0 hazards and load hazards. No NOP instructions are required to correct
instruction sequences.

Signed-off-by: Zhang Le <r0bertz@gentoo.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Zhang Le 2009-04-15 17:01:52 +08:00 committed by Ralf Baechle
parent 6cec2a0ac5
commit 5d57c31e57
1 changed files with 3 additions and 2 deletions
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5
arch/mips/include/asm/hazards.h
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@ -138,8 +138,9 @@ do { \
__instruction_hazard(); \
} while (0)
#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
defined(CONFIG_CPU_R5500) || defined(CONFIG_MACH_ALCHEMY)
#elif defined(CONFIG_MACH_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \
defined(CONFIG_CPU_R5500)
/*
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.