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arm64: perf: add support for Cortex-A72
Cortex-A72 has a PMUv3 implementation that is compatible with the PMU implemented by Cortex-A57. This patch hooks up the new compatible string so that the Cortex-A57 event mappings are used. Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -9,6 +9,7 @@ Required properties:
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- compatible : should be one of
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"apm,potenza-pmu"
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"arm,armv8-pmuv3"
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"arm,cortex-a72-pmu"
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"arm,cortex-a57-pmu"
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"arm,cortex-a53-pmu"
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"arm,cortex-a17-pmu"
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@ -90,7 +90,7 @@
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/* ARMv8 Cortex-A53 specific event types. */
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#define ARMV8_A53_PERFCTR_PREFETCH_LINEFILL 0xC2
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/* ARMv8 Cortex-A57 specific event types. */
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/* ARMv8 Cortex-A57 and Cortex-A72 specific event types. */
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#define ARMV8_A57_PERFCTR_L1_DCACHE_ACCESS_LD 0x40
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#define ARMV8_A57_PERFCTR_L1_DCACHE_ACCESS_ST 0x41
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#define ARMV8_A57_PERFCTR_L1_DCACHE_REFILL_LD 0x42
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@ -120,6 +120,7 @@ static const unsigned armv8_a53_perf_map[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
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};
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/* ARM Cortex-A57 and Cortex-A72 events mapping. */
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static const unsigned armv8_a57_perf_map[PERF_COUNT_HW_MAX] = {
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PERF_MAP_ALL_UNSUPPORTED,
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
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@ -801,10 +802,20 @@ static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
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return armv8pmu_probe_num_events(cpu_pmu);
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}
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static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
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{
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armv8_pmu_init(cpu_pmu);
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cpu_pmu->name = "armv8_cortex_a72";
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cpu_pmu->map_event = armv8_a57_map_event;
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cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups;
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return armv8pmu_probe_num_events(cpu_pmu);
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}
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static const struct of_device_id armv8_pmu_of_device_ids[] = {
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{.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init},
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{.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init},
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{.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init},
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{.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init},
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{},
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};
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