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watchdog: hpe-wdt: Introduce HPE GXP Watchdog
Add support for the HPE GXP Watchdog. The GXP asic contains a full complement of timers one of which is the watchdog timer. The watchdog timer is 16 bit and has 10ms resolution. The watchdog is created as a child device of timer since the same register range is used. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Guenter Roeck <linux@roeck-us.net>
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@ -1820,6 +1820,17 @@ config RALINK_WDT
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help
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Hardware driver for the Ralink SoC Watchdog Timer.
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config GXP_WATCHDOG
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tristate "HPE GXP watchdog support"
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depends on ARCH_HPE_GXP
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select WATCHDOG_CORE
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help
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Say Y here to include support for the watchdog timer
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in HPE GXP SoCs.
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To compile this driver as a module, choose M here.
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The module will be called gxp-wdt.
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config MT7621_WDT
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tristate "Mediatek SoC watchdog"
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select WATCHDOG_CORE
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@ -92,6 +92,7 @@ obj-$(CONFIG_RTD119X_WATCHDOG) += rtd119x_wdt.o
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obj-$(CONFIG_SPRD_WATCHDOG) += sprd_wdt.o
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obj-$(CONFIG_PM8916_WATCHDOG) += pm8916_wdt.o
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obj-$(CONFIG_ARM_SMC_WATCHDOG) += arm_smc_wdt.o
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obj-$(CONFIG_GXP_WATCHDOG) += gxp-wdt.o
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obj-$(CONFIG_VISCONTI_WATCHDOG) += visconti_wdt.o
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obj-$(CONFIG_MSC313E_WATCHDOG) += msc313e_wdt.o
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obj-$(CONFIG_APPLE_WATCHDOG) += apple_wdt.o
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174
drivers/watchdog/gxp-wdt.c
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174
drivers/watchdog/gxp-wdt.c
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@ -0,0 +1,174 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <linux/watchdog.h>
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#define MASK_WDGCS_ENABLE 0x01
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#define MASK_WDGCS_RELOAD 0x04
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#define MASK_WDGCS_NMIEN 0x08
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#define MASK_WDGCS_WARN 0x80
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#define WDT_MAX_TIMEOUT_MS 655350
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#define WDT_DEFAULT_TIMEOUT 30
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#define SECS_TO_WDOG_TICKS(x) ((x) * 100)
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#define WDOG_TICKS_TO_SECS(x) ((x) / 100)
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#define GXP_WDT_CNT_OFS 0x10
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#define GXP_WDT_CTRL_OFS 0x16
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struct gxp_wdt {
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void __iomem *base;
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struct watchdog_device wdd;
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};
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static void gxp_wdt_enable_reload(struct gxp_wdt *drvdata)
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{
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u8 val;
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val = readb(drvdata->base + GXP_WDT_CTRL_OFS);
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val |= (MASK_WDGCS_ENABLE | MASK_WDGCS_RELOAD);
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writeb(val, drvdata->base + GXP_WDT_CTRL_OFS);
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}
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static int gxp_wdt_start(struct watchdog_device *wdd)
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{
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struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
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writew(SECS_TO_WDOG_TICKS(wdd->timeout), drvdata->base + GXP_WDT_CNT_OFS);
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gxp_wdt_enable_reload(drvdata);
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return 0;
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}
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static int gxp_wdt_stop(struct watchdog_device *wdd)
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{
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struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
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u8 val;
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val = readb_relaxed(drvdata->base + GXP_WDT_CTRL_OFS);
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val &= ~MASK_WDGCS_ENABLE;
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writeb(val, drvdata->base + GXP_WDT_CTRL_OFS);
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return 0;
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}
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static int gxp_wdt_set_timeout(struct watchdog_device *wdd,
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unsigned int timeout)
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{
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struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
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u32 actual;
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wdd->timeout = timeout;
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actual = min(timeout * 100, wdd->max_hw_heartbeat_ms / 10);
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writew(actual, drvdata->base + GXP_WDT_CNT_OFS);
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return 0;
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}
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static unsigned int gxp_wdt_get_timeleft(struct watchdog_device *wdd)
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{
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struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
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u32 val = readw(drvdata->base + GXP_WDT_CNT_OFS);
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return WDOG_TICKS_TO_SECS(val);
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}
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static int gxp_wdt_ping(struct watchdog_device *wdd)
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{
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struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
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gxp_wdt_enable_reload(drvdata);
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return 0;
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}
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static int gxp_restart(struct watchdog_device *wdd, unsigned long action,
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void *data)
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{
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struct gxp_wdt *drvdata = watchdog_get_drvdata(wdd);
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writew(1, drvdata->base + GXP_WDT_CNT_OFS);
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gxp_wdt_enable_reload(drvdata);
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mdelay(100);
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return 0;
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}
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static const struct watchdog_ops gxp_wdt_ops = {
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.owner = THIS_MODULE,
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.start = gxp_wdt_start,
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.stop = gxp_wdt_stop,
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.ping = gxp_wdt_ping,
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.set_timeout = gxp_wdt_set_timeout,
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.get_timeleft = gxp_wdt_get_timeleft,
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.restart = gxp_restart,
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};
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static const struct watchdog_info gxp_wdt_info = {
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.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING,
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.identity = "HPE GXP Watchdog timer",
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};
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static int gxp_wdt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct gxp_wdt *drvdata;
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int err;
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u8 val;
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drvdata = devm_kzalloc(dev, sizeof(struct gxp_wdt), GFP_KERNEL);
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if (!drvdata)
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return -ENOMEM;
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/*
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* The register area where the timer and watchdog reside is disarranged.
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* Hence mapping individual register blocks for the timer and watchdog
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* is not recommended as they would have access to each others
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* registers. Based on feedback the watchdog is no longer part of the
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* device tree file and the timer driver now creates the watchdog as a
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* child device. During the watchdogs creation, the timer driver passes
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* the base address to the watchdog over the private interface.
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*/
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drvdata->base = (void __iomem *)dev->platform_data;
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drvdata->wdd.info = &gxp_wdt_info;
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drvdata->wdd.ops = &gxp_wdt_ops;
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drvdata->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
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drvdata->wdd.parent = dev;
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drvdata->wdd.timeout = WDT_DEFAULT_TIMEOUT;
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watchdog_set_drvdata(&drvdata->wdd, drvdata);
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watchdog_set_nowayout(&drvdata->wdd, WATCHDOG_NOWAYOUT);
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val = readb(drvdata->base + GXP_WDT_CTRL_OFS);
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if (val & MASK_WDGCS_ENABLE)
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set_bit(WDOG_HW_RUNNING, &drvdata->wdd.status);
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watchdog_set_restart_priority(&drvdata->wdd, 128);
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watchdog_stop_on_reboot(&drvdata->wdd);
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err = devm_watchdog_register_device(dev, &drvdata->wdd);
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if (err) {
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dev_err(dev, "Failed to register watchdog device");
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return err;
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}
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dev_info(dev, "HPE GXP watchdog timer");
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return 0;
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}
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static struct platform_driver gxp_wdt_driver = {
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.probe = gxp_wdt_probe,
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.driver = {
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.name = "gxp-wdt",
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},
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};
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module_platform_driver(gxp_wdt_driver);
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MODULE_AUTHOR("Nick Hawkins <nick.hawkins@hpe.com>");
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MODULE_AUTHOR("Jean-Marie Verdun <verdun@hpe.com>");
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MODULE_DESCRIPTION("Driver for GXP watchdog timer");
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