mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
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net: Add be2net driver.
Signed-off-by: Sathya Perla <sathyap@serverengines.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Sathya Perla
David S. Miller
parent
2c5849ea38
commit
6b7c5b947c
@ -3880,6 +3880,15 @@ L: linux-ide@vger.kernel.org
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T: git kernel.org:/pub/scm/linux/kernel/git/jgarzik/libata-dev.git
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S: Supported
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SERVER ENGINES 10Gbps NIC - BladeEngine 2 DRIVER
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P: Sathya Perla
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M: sathyap@serverengines.com
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P: Subbu Seetharaman
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M: subbus@serverengines.com
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L: netdev@vger.kernel.org
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W: http://www.serverengines.com
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S: Supported
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SFC NETWORK DRIVER
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P: Steve Hodgson
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P: Ben Hutchings
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@ -2630,6 +2630,8 @@ config QLGE
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source "drivers/net/sfc/Kconfig"
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source "drivers/net/benet/Kconfig"
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endif # NETDEV_10000
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source "drivers/net/tokenring/Kconfig"
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@ -22,6 +22,7 @@ obj-$(CONFIG_GIANFAR) += gianfar_driver.o
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obj-$(CONFIG_TEHUTI) += tehuti.o
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obj-$(CONFIG_ENIC) += enic/
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obj-$(CONFIG_JME) += jme.o
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obj-$(CONFIG_BE2NET) += benet/
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gianfar_driver-objs := gianfar.o \
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gianfar_ethtool.o \
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7
drivers/net/benet/Kconfig
Normal file
7
drivers/net/benet/Kconfig
Normal file
@ -0,0 +1,7 @@
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config BE2NET
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tristate "ServerEngines' 10Gbps NIC - BladeEngine 2"
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depends on PCI && INET
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select INET_LRO
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help
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This driver implements the NIC functionality for ServerEngines'
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10Gbps network adapter - BladeEngine 2.
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7
drivers/net/benet/Makefile
Normal file
7
drivers/net/benet/Makefile
Normal file
@ -0,0 +1,7 @@
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#
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# Makefile to build the network driver for ServerEngine's BladeEngine.
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#
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obj-$(CONFIG_BE2NET) += be2net.o
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be2net-y := be_main.o be_cmds.o be_ethtool.o
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327
drivers/net/benet/be.h
Normal file
327
drivers/net/benet/be.h
Normal file
@ -0,0 +1,327 @@
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/*
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* Copyright (C) 2005 - 2009 ServerEngines
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation. The full GNU General
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* Public License is included in this distribution in the file called COPYING.
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*
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* Contact Information:
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* linux-drivers@serverengines.com
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*
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* ServerEngines
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* 209 N. Fair Oaks Ave
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* Sunnyvale, CA 94085
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*/
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#ifndef BE_H
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#define BE_H
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#include <linux/pci.h>
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#include <linux/etherdevice.h>
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#include <linux/version.h>
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#include <linux/delay.h>
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#include <net/tcp.h>
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#include <net/ip.h>
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#include <net/ipv6.h>
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#include <linux/if_vlan.h>
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#include <linux/workqueue.h>
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#include <linux/interrupt.h>
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#include <linux/inet_lro.h>
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#include "be_hw.h"
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#define DRV_VER "2.0.348"
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#define DRV_NAME "be2net"
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#define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
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#define DRV_DESC BE_NAME "Driver"
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/* Number of bytes of an RX frame that are copied to skb->data */
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#define BE_HDR_LEN 64
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#define BE_MAX_JUMBO_FRAME_SIZE 9018
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#define BE_MIN_MTU 256
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#define BE_NUM_VLANS_SUPPORTED 64
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#define BE_MAX_EQD 96
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#define BE_MAX_TX_FRAG_COUNT 30
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#define EVNT_Q_LEN 1024
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#define TX_Q_LEN 2048
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#define TX_CQ_LEN 1024
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#define RX_Q_LEN 1024 /* Does not support any other value */
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#define RX_CQ_LEN 1024
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#define MCC_Q_LEN 64 /* total size not to exceed 8 pages */
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#define MCC_CQ_LEN 256
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#define BE_NAPI_WEIGHT 64
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#define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
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#define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
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#define BE_MAX_LRO_DESCRIPTORS 16
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#define BE_MAX_FRAGS_PER_FRAME 16
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struct be_dma_mem {
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void *va;
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dma_addr_t dma;
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u32 size;
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};
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struct be_queue_info {
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struct be_dma_mem dma_mem;
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u16 len;
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u16 entry_size; /* Size of an element in the queue */
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u16 id;
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u16 tail, head;
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bool created;
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atomic_t used; /* Number of valid elements in the queue */
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};
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struct be_ctrl_info {
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u8 __iomem *csr;
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u8 __iomem *db; /* Door Bell */
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u8 __iomem *pcicfg; /* PCI config space */
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int pci_func;
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/* Mbox used for cmd request/response */
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spinlock_t cmd_lock; /* For serializing cmds to BE card */
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struct be_dma_mem mbox_mem;
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/* Mbox mem is adjusted to align to 16 bytes. The allocated addr
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* is stored for freeing purpose */
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struct be_dma_mem mbox_mem_alloced;
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};
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#include "be_cmds.h"
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struct be_drvr_stats {
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u32 be_tx_reqs; /* number of TX requests initiated */
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u32 be_tx_stops; /* number of times TX Q was stopped */
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u32 be_fwd_reqs; /* number of send reqs through forwarding i/f */
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u32 be_tx_wrbs; /* number of tx WRBs used */
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u32 be_tx_events; /* number of tx completion events */
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u32 be_tx_compl; /* number of tx completion entries processed */
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u64 be_tx_jiffies;
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ulong be_tx_bytes;
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ulong be_tx_bytes_prev;
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u32 be_tx_rate;
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u32 cache_barrier[16];
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u32 be_ethrx_post_fail;/* number of ethrx buffer alloc failures */
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u32 be_polls; /* number of times NAPI called poll function */
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u32 be_rx_events; /* number of ucast rx completion events */
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u32 be_rx_compl; /* number of rx completion entries processed */
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u32 be_lro_hgram_data[8]; /* histogram of LRO data packets */
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u32 be_lro_hgram_ack[8]; /* histogram of LRO ACKs */
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u64 be_rx_jiffies;
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ulong be_rx_bytes;
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ulong be_rx_bytes_prev;
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u32 be_rx_rate;
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/* number of non ether type II frames dropped where
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* frame len > length field of Mac Hdr */
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u32 be_802_3_dropped_frames;
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/* number of non ether type II frames malformed where
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* in frame len < length field of Mac Hdr */
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u32 be_802_3_malformed_frames;
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u32 be_rxcp_err; /* Num rx completion entries w/ err set. */
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ulong rx_fps_jiffies; /* jiffies at last FPS calc */
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u32 be_rx_frags;
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u32 be_prev_rx_frags;
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u32 be_rx_fps; /* Rx frags per second */
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};
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struct be_stats_obj {
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struct be_drvr_stats drvr_stats;
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struct net_device_stats net_stats;
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struct be_dma_mem cmd;
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};
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struct be_eq_obj {
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struct be_queue_info q;
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char desc[32];
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/* Adaptive interrupt coalescing (AIC) info */
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bool enable_aic;
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u16 min_eqd; /* in usecs */
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u16 max_eqd; /* in usecs */
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u16 cur_eqd; /* in usecs */
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struct napi_struct napi;
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};
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struct be_tx_obj {
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struct be_queue_info q;
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struct be_queue_info cq;
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/* Remember the skbs that were transmitted */
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struct sk_buff *sent_skb_list[TX_Q_LEN];
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};
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/* Struct to remember the pages posted for rx frags */
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struct be_rx_page_info {
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struct page *page;
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dma_addr_t bus;
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u16 page_offset;
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bool last_page_user;
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};
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struct be_rx_obj {
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struct be_queue_info q;
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struct be_queue_info cq;
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struct be_rx_page_info page_info_tbl[RX_Q_LEN];
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struct net_lro_mgr lro_mgr;
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struct net_lro_desc lro_desc[BE_MAX_LRO_DESCRIPTORS];
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};
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#define BE_NUM_MSIX_VECTORS 2 /* 1 each for Tx and Rx */
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struct be_adapter {
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struct pci_dev *pdev;
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struct net_device *netdev;
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/* Mbox, pci config, csr address information */
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struct be_ctrl_info ctrl;
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struct msix_entry msix_entries[BE_NUM_MSIX_VECTORS];
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bool msix_enabled;
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bool isr_registered;
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/* TX Rings */
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struct be_eq_obj tx_eq;
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struct be_tx_obj tx_obj;
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u32 cache_line_break[8];
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/* Rx rings */
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struct be_eq_obj rx_eq;
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struct be_rx_obj rx_obj;
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u32 big_page_size; /* Compounded page size shared by rx wrbs */
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struct vlan_group *vlan_grp;
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u16 num_vlans;
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u8 vlan_tag[VLAN_GROUP_ARRAY_LEN];
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struct be_stats_obj stats;
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/* Work queue used to perform periodic tasks like getting statistics */
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struct delayed_work work;
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/* Ethtool knobs and info */
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bool rx_csum; /* BE card must perform rx-checksumming */
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u32 max_rx_coal;
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char fw_ver[FW_VER_LEN];
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u32 if_handle; /* Used to configure filtering */
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u32 pmac_id; /* MAC addr handle used by BE card */
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struct be_link_info link;
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u32 port_num;
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};
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extern struct ethtool_ops be_ethtool_ops;
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#define drvr_stats(adapter) (&adapter->stats.drvr_stats)
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#define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops)
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static inline u32 MODULO(u16 val, u16 limit)
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{
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BUG_ON(limit & (limit - 1));
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return val & (limit - 1);
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}
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static inline void index_adv(u16 *index, u16 val, u16 limit)
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{
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*index = MODULO((*index + val), limit);
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}
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static inline void index_inc(u16 *index, u16 limit)
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{
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*index = MODULO((*index + 1), limit);
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}
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#define PAGE_SHIFT_4K 12
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#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
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/* Returns number of pages spanned by the data starting at the given addr */
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#define PAGES_4K_SPANNED(_address, size) \
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((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
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(size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
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/* Byte offset into the page corresponding to given address */
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#define OFFSET_IN_PAGE(addr) \
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((size_t)(addr) & (PAGE_SIZE_4K-1))
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/* Returns bit offset within a DWORD of a bitfield */
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#define AMAP_BIT_OFFSET(_struct, field) \
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(((size_t)&(((_struct *)0)->field))%32)
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/* Returns the bit mask of the field that is NOT shifted into location. */
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static inline u32 amap_mask(u32 bitsize)
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{
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return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
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}
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static inline void
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amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
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{
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u32 *dw = (u32 *) ptr + dw_offset;
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*dw &= ~(mask << offset);
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*dw |= (mask & value) << offset;
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}
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#define AMAP_SET_BITS(_struct, field, ptr, val) \
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amap_set(ptr, \
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offsetof(_struct, field)/32, \
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amap_mask(sizeof(((_struct *)0)->field)), \
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AMAP_BIT_OFFSET(_struct, field), \
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val)
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static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
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{
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u32 *dw = (u32 *) ptr;
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return mask & (*(dw + dw_offset) >> offset);
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}
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#define AMAP_GET_BITS(_struct, field, ptr) \
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amap_get(ptr, \
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offsetof(_struct, field)/32, \
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amap_mask(sizeof(((_struct *)0)->field)), \
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AMAP_BIT_OFFSET(_struct, field))
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#define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
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#define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
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static inline void swap_dws(void *wrb, int len)
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{
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#ifdef __BIG_ENDIAN
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u32 *dw = wrb;
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BUG_ON(len % 4);
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do {
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*dw = cpu_to_le32(*dw);
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dw++;
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len -= 4;
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} while (len);
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#endif /* __BIG_ENDIAN */
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}
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static inline u8 is_tcp_pkt(struct sk_buff *skb)
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{
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u8 val = 0;
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if (ip_hdr(skb)->version == 4)
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val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
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else if (ip_hdr(skb)->version == 6)
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val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
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return val;
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}
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static inline u8 is_udp_pkt(struct sk_buff *skb)
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{
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u8 val = 0;
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if (ip_hdr(skb)->version == 4)
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val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
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else if (ip_hdr(skb)->version == 6)
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val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
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return val;
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}
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#endif /* BE_H */
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861
drivers/net/benet/be_cmds.c
Normal file
861
drivers/net/benet/be_cmds.c
Normal file
@ -0,0 +1,861 @@
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/*
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* Copyright (C) 2005 - 2009 ServerEngines
|
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* All rights reserved.
|
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation. The full GNU General
|
||||
* Public License is included in this distribution in the file called COPYING.
|
||||
*
|
||||
* Contact Information:
|
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* linux-drivers@serverengines.com
|
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*
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* ServerEngines
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* 209 N. Fair Oaks Ave
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* Sunnyvale, CA 94085
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*/
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#include "be.h"
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static int be_mbox_db_ready_wait(void __iomem *db)
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{
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int cnt = 0, wait = 5;
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u32 ready;
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do {
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ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK;
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if (ready)
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break;
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if (cnt > 200000) {
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printk(KERN_WARNING DRV_NAME
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": mbox_db poll timed out\n");
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return -1;
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}
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if (cnt > 50)
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wait = 200;
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cnt += wait;
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udelay(wait);
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} while (true);
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return 0;
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}
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/*
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* Insert the mailbox address into the doorbell in two steps
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*/
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static int be_mbox_db_ring(struct be_ctrl_info *ctrl)
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{
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int status;
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u16 compl_status, extd_status;
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u32 val = 0;
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void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
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struct be_dma_mem *mbox_mem = &ctrl->mbox_mem;
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struct be_mcc_mailbox *mbox = mbox_mem->va;
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struct be_mcc_cq_entry *cqe = &mbox->cqe;
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memset(cqe, 0, sizeof(*cqe));
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val &= ~MPU_MAILBOX_DB_RDY_MASK;
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val |= MPU_MAILBOX_DB_HI_MASK;
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/* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
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val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
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iowrite32(val, db);
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/* wait for ready to be set */
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status = be_mbox_db_ready_wait(db);
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if (status != 0)
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return status;
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val = 0;
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val &= ~MPU_MAILBOX_DB_RDY_MASK;
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val &= ~MPU_MAILBOX_DB_HI_MASK;
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/* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
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val |= (u32)(mbox_mem->dma >> 4) << 2;
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iowrite32(val, db);
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|
||||
status = be_mbox_db_ready_wait(db);
|
||||
if (status != 0)
|
||||
return status;
|
||||
|
||||
/* compl entry has been made now */
|
||||
be_dws_le_to_cpu(cqe, sizeof(*cqe));
|
||||
if (!(cqe->flags & CQE_FLAGS_VALID_MASK)) {
|
||||
printk(KERN_WARNING DRV_NAME ": ERROR invalid mbox compl\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
compl_status = (cqe->status >> CQE_STATUS_COMPL_SHIFT) &
|
||||
CQE_STATUS_COMPL_MASK;
|
||||
if (compl_status != MCC_STATUS_SUCCESS) {
|
||||
extd_status = (cqe->status >> CQE_STATUS_EXTD_SHIFT) &
|
||||
CQE_STATUS_EXTD_MASK;
|
||||
printk(KERN_WARNING DRV_NAME
|
||||
": ERROR in cmd compl. status(compl/extd)=%d/%d\n",
|
||||
compl_status, extd_status);
|
||||
}
|
||||
|
||||
return compl_status;
|
||||
}
|
||||
|
||||
static int be_POST_stage_get(struct be_ctrl_info *ctrl, u16 *stage)
|
||||
{
|
||||
u32 sem = ioread32(ctrl->csr + MPU_EP_SEMAPHORE_OFFSET);
|
||||
|
||||
*stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
|
||||
if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
|
||||
return -1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int be_POST_stage_poll(struct be_ctrl_info *ctrl, u16 poll_stage)
|
||||
{
|
||||
u16 stage, cnt, error;
|
||||
for (cnt = 0; cnt < 5000; cnt++) {
|
||||
error = be_POST_stage_get(ctrl, &stage);
|
||||
if (error)
|
||||
return -1;
|
||||
|
||||
if (stage == poll_stage)
|
||||
break;
|
||||
udelay(1000);
|
||||
}
|
||||
if (stage != poll_stage)
|
||||
return -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int be_cmd_POST(struct be_ctrl_info *ctrl)
|
||||
{
|
||||
u16 stage, error;
|
||||
|
||||
error = be_POST_stage_get(ctrl, &stage);
|
||||
if (error)
|
||||
goto err;
|
||||
|
||||
if (stage == POST_STAGE_ARMFW_RDY)
|
||||
return 0;
|
||||
|
||||
if (stage != POST_STAGE_AWAITING_HOST_RDY)
|
||||
goto err;
|
||||
|
||||
/* On awaiting host rdy, reset and again poll on awaiting host rdy */
|
||||
iowrite32(POST_STAGE_BE_RESET, ctrl->csr + MPU_EP_SEMAPHORE_OFFSET);
|
||||
error = be_POST_stage_poll(ctrl, POST_STAGE_AWAITING_HOST_RDY);
|
||||
if (error)
|
||||
goto err;
|
||||
|
||||
/* Now kickoff POST and poll on armfw ready */
|
||||
iowrite32(POST_STAGE_HOST_RDY, ctrl->csr + MPU_EP_SEMAPHORE_OFFSET);
|
||||
error = be_POST_stage_poll(ctrl, POST_STAGE_ARMFW_RDY);
|
||||
if (error)
|
||||
goto err;
|
||||
|
||||
return 0;
|
||||
err:
|
||||
printk(KERN_WARNING DRV_NAME ": ERROR, stage=%d\n", stage);
|
||||
return -1;
|
||||
}
|
||||
|
||||
static inline void *embedded_payload(struct be_mcc_wrb *wrb)
|
||||
{
|
||||
return wrb->payload.embedded_payload;
|
||||
}
|
||||
|
||||
static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
|
||||
{
|
||||
return &wrb->payload.sgl[0];
|
||||
}
|
||||
|
||||
/* Don't touch the hdr after it's prepared */
|
||||
static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
|
||||
bool embedded, u8 sge_cnt)
|
||||
{
|
||||
if (embedded)
|
||||
wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
|
||||
else
|
||||
wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
|
||||
MCC_WRB_SGE_CNT_SHIFT;
|
||||
wrb->payload_length = payload_len;
|
||||
be_dws_cpu_to_le(wrb, 20);
|
||||
}
|
||||
|
||||
/* Don't touch the hdr after it's prepared */
|
||||
static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
|
||||
u8 subsystem, u8 opcode, int cmd_len)
|
||||
{
|
||||
req_hdr->opcode = opcode;
|
||||
req_hdr->subsystem = subsystem;
|
||||
req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
|
||||
}
|
||||
|
||||
static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
|
||||
struct be_dma_mem *mem)
|
||||
{
|
||||
int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
|
||||
u64 dma = (u64)mem->dma;
|
||||
|
||||
for (i = 0; i < buf_pages; i++) {
|
||||
pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
|
||||
pages[i].hi = cpu_to_le32(upper_32_bits(dma));
|
||||
dma += PAGE_SIZE_4K;
|
||||
}
|
||||
}
|
||||
|
||||
/* Converts interrupt delay in microseconds to multiplier value */
|
||||
static u32 eq_delay_to_mult(u32 usec_delay)
|
||||
{
|
||||
#define MAX_INTR_RATE 651042
|
||||
const u32 round = 10;
|
||||
u32 multiplier;
|
||||
|
||||
if (usec_delay == 0)
|
||||
multiplier = 0;
|
||||
else {
|
||||
u32 interrupt_rate = 1000000 / usec_delay;
|
||||
/* Max delay, corresponding to the lowest interrupt rate */
|
||||
if (interrupt_rate == 0)
|
||||
multiplier = 1023;
|
||||
else {
|
||||
multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
|
||||
multiplier /= interrupt_rate;
|
||||
/* Round the multiplier to the closest value.*/
|
||||
multiplier = (multiplier + round/2) / round;
|
||||
multiplier = min(multiplier, (u32)1023);
|
||||
}
|
||||
}
|
||||
return multiplier;
|
||||
}
|
||||
|
||||
static inline struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem)
|
||||
{
|
||||
return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
|
||||
}
|
||||
|
||||
int be_cmd_eq_create(struct be_ctrl_info *ctrl,
|
||||
struct be_queue_info *eq, int eq_delay)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_eq_create *req = embedded_payload(wrb);
|
||||
struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
|
||||
struct be_dma_mem *q_mem = &eq->dma_mem;
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
||||
OPCODE_COMMON_EQ_CREATE, sizeof(*req));
|
||||
|
||||
req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
|
||||
|
||||
AMAP_SET_BITS(struct amap_eq_context, func, req->context,
|
||||
ctrl->pci_func);
|
||||
AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
|
||||
/* 4byte eqe*/
|
||||
AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
|
||||
AMAP_SET_BITS(struct amap_eq_context, count, req->context,
|
||||
__ilog2_u32(eq->len/256));
|
||||
AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
|
||||
eq_delay_to_mult(eq_delay));
|
||||
be_dws_cpu_to_le(req->context, sizeof(req->context));
|
||||
|
||||
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
if (!status) {
|
||||
eq->id = le16_to_cpu(resp->eq_id);
|
||||
eq->created = true;
|
||||
}
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
return status;
|
||||
}
|
||||
|
||||
int be_cmd_mac_addr_query(struct be_ctrl_info *ctrl, u8 *mac_addr,
|
||||
u8 type, bool permanent, u32 if_handle)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_mac_query *req = embedded_payload(wrb);
|
||||
struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
||||
OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
|
||||
|
||||
req->type = type;
|
||||
if (permanent) {
|
||||
req->permanent = 1;
|
||||
} else {
|
||||
req->if_id = cpu_to_le16((u16)if_handle);
|
||||
req->permanent = 0;
|
||||
}
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
if (!status)
|
||||
memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
|
||||
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
return status;
|
||||
}
|
||||
|
||||
int be_cmd_pmac_add(struct be_ctrl_info *ctrl, u8 *mac_addr,
|
||||
u32 if_id, u32 *pmac_id)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_pmac_add *req = embedded_payload(wrb);
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
||||
OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
|
||||
|
||||
req->if_id = cpu_to_le32(if_id);
|
||||
memcpy(req->mac_address, mac_addr, ETH_ALEN);
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
if (!status) {
|
||||
struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
|
||||
*pmac_id = le32_to_cpu(resp->pmac_id);
|
||||
}
|
||||
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
return status;
|
||||
}
|
||||
|
||||
int be_cmd_pmac_del(struct be_ctrl_info *ctrl, u32 if_id, u32 pmac_id)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_pmac_del *req = embedded_payload(wrb);
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
||||
OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
|
||||
|
||||
req->if_id = cpu_to_le32(if_id);
|
||||
req->pmac_id = cpu_to_le32(pmac_id);
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
int be_cmd_cq_create(struct be_ctrl_info *ctrl,
|
||||
struct be_queue_info *cq, struct be_queue_info *eq,
|
||||
bool sol_evts, bool no_delay, int coalesce_wm)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_cq_create *req = embedded_payload(wrb);
|
||||
struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
|
||||
struct be_dma_mem *q_mem = &cq->dma_mem;
|
||||
void *ctxt = &req->context;
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
||||
OPCODE_COMMON_CQ_CREATE, sizeof(*req));
|
||||
|
||||
req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
|
||||
|
||||
AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
|
||||
AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
|
||||
AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
|
||||
__ilog2_u32(cq->len/256));
|
||||
AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
|
||||
AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
|
||||
AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
|
||||
AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
|
||||
AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 0);
|
||||
AMAP_SET_BITS(struct amap_cq_context, func, ctxt, ctrl->pci_func);
|
||||
be_dws_cpu_to_le(ctxt, sizeof(req->context));
|
||||
|
||||
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
if (!status) {
|
||||
cq->id = le16_to_cpu(resp->cq_id);
|
||||
cq->created = true;
|
||||
}
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
int be_cmd_txq_create(struct be_ctrl_info *ctrl,
|
||||
struct be_queue_info *txq,
|
||||
struct be_queue_info *cq)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_eth_tx_create *req = embedded_payload(wrb);
|
||||
struct be_dma_mem *q_mem = &txq->dma_mem;
|
||||
void *ctxt = &req->context;
|
||||
int status;
|
||||
u32 len_encoded;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
|
||||
sizeof(*req));
|
||||
|
||||
req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
|
||||
req->ulp_num = BE_ULP1_NUM;
|
||||
req->type = BE_ETH_TX_RING_TYPE_STANDARD;
|
||||
|
||||
len_encoded = fls(txq->len); /* log2(len) + 1 */
|
||||
if (len_encoded == 16)
|
||||
len_encoded = 0;
|
||||
AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt, len_encoded);
|
||||
AMAP_SET_BITS(struct amap_tx_context, pci_func_id, ctxt,
|
||||
ctrl->pci_func);
|
||||
AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
|
||||
AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
|
||||
|
||||
be_dws_cpu_to_le(ctxt, sizeof(req->context));
|
||||
|
||||
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
if (!status) {
|
||||
struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
|
||||
txq->id = le16_to_cpu(resp->cid);
|
||||
txq->created = true;
|
||||
}
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
int be_cmd_rxq_create(struct be_ctrl_info *ctrl,
|
||||
struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
|
||||
u16 max_frame_size, u32 if_id, u32 rss)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_eth_rx_create *req = embedded_payload(wrb);
|
||||
struct be_dma_mem *q_mem = &rxq->dma_mem;
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
|
||||
sizeof(*req));
|
||||
|
||||
req->cq_id = cpu_to_le16(cq_id);
|
||||
req->frag_size = fls(frag_size) - 1;
|
||||
req->num_pages = 2;
|
||||
be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
|
||||
req->interface_id = cpu_to_le32(if_id);
|
||||
req->max_frame_size = cpu_to_le16(max_frame_size);
|
||||
req->rss_queue = cpu_to_le32(rss);
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
if (!status) {
|
||||
struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
|
||||
rxq->id = le16_to_cpu(resp->id);
|
||||
rxq->created = true;
|
||||
}
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Generic destroyer function for all types of queues */
|
||||
int be_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
|
||||
int queue_type)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_q_destroy *req = embedded_payload(wrb);
|
||||
u8 subsys = 0, opcode = 0;
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
switch (queue_type) {
|
||||
case QTYPE_EQ:
|
||||
subsys = CMD_SUBSYSTEM_COMMON;
|
||||
opcode = OPCODE_COMMON_EQ_DESTROY;
|
||||
break;
|
||||
case QTYPE_CQ:
|
||||
subsys = CMD_SUBSYSTEM_COMMON;
|
||||
opcode = OPCODE_COMMON_CQ_DESTROY;
|
||||
break;
|
||||
case QTYPE_TXQ:
|
||||
subsys = CMD_SUBSYSTEM_ETH;
|
||||
opcode = OPCODE_ETH_TX_DESTROY;
|
||||
break;
|
||||
case QTYPE_RXQ:
|
||||
subsys = CMD_SUBSYSTEM_ETH;
|
||||
opcode = OPCODE_ETH_RX_DESTROY;
|
||||
break;
|
||||
default:
|
||||
printk(KERN_WARNING DRV_NAME ":bad Q type in Q destroy cmd\n");
|
||||
status = -1;
|
||||
goto err;
|
||||
}
|
||||
be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
|
||||
req->id = cpu_to_le16(q->id);
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
err:
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Create an rx filtering policy configuration on an i/f */
|
||||
int be_cmd_if_create(struct be_ctrl_info *ctrl, u32 flags, u8 *mac,
|
||||
bool pmac_invalid, u32 *if_handle, u32 *pmac_id)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_if_create *req = embedded_payload(wrb);
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
||||
OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
|
||||
|
||||
req->capability_flags = cpu_to_le32(flags);
|
||||
req->enable_flags = cpu_to_le32(flags);
|
||||
if (!pmac_invalid)
|
||||
memcpy(req->mac_addr, mac, ETH_ALEN);
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
if (!status) {
|
||||
struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
|
||||
*if_handle = le32_to_cpu(resp->interface_id);
|
||||
if (!pmac_invalid)
|
||||
*pmac_id = le32_to_cpu(resp->pmac_id);
|
||||
}
|
||||
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
return status;
|
||||
}
|
||||
|
||||
int be_cmd_if_destroy(struct be_ctrl_info *ctrl, u32 interface_id)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_if_destroy *req = embedded_payload(wrb);
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
||||
OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
|
||||
|
||||
req->interface_id = cpu_to_le32(interface_id);
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/* Get stats is a non embedded command: the request is not embedded inside
|
||||
* WRB but is a separate dma memory block
|
||||
*/
|
||||
int be_cmd_get_stats(struct be_ctrl_info *ctrl, struct be_dma_mem *nonemb_cmd)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_get_stats *req = nonemb_cmd->va;
|
||||
struct be_sge *sge = nonembedded_sgl(wrb);
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
memset(req, 0, sizeof(*req));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
|
||||
OPCODE_ETH_GET_STATISTICS, sizeof(*req));
|
||||
sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
|
||||
sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
|
||||
sge->len = cpu_to_le32(nonemb_cmd->size);
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
if (!status) {
|
||||
struct be_cmd_resp_get_stats *resp = nonemb_cmd->va;
|
||||
be_dws_le_to_cpu(&resp->hw_stats, sizeof(resp->hw_stats));
|
||||
}
|
||||
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
return status;
|
||||
}
|
||||
|
||||
int be_cmd_link_status_query(struct be_ctrl_info *ctrl,
|
||||
struct be_link_info *link)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_link_status *req = embedded_payload(wrb);
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
||||
OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
if (!status) {
|
||||
struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
|
||||
link->speed = resp->mac_speed;
|
||||
link->duplex = resp->mac_duplex;
|
||||
link->fault = resp->mac_fault;
|
||||
} else {
|
||||
link->speed = PHY_LINK_SPEED_ZERO;
|
||||
}
|
||||
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
return status;
|
||||
}
|
||||
|
||||
int be_cmd_get_fw_ver(struct be_ctrl_info *ctrl, char *fw_ver)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_get_fw_version *req = embedded_payload(wrb);
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
||||
OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
if (!status) {
|
||||
struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
|
||||
strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
|
||||
}
|
||||
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
return status;
|
||||
}
|
||||
|
||||
/* set the EQ delay interval of an EQ to specified value */
|
||||
int be_cmd_modify_eqd(struct be_ctrl_info *ctrl, u32 eq_id, u32 eqd)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_modify_eq_delay *req = embedded_payload(wrb);
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
||||
OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
|
||||
|
||||
req->num_eq = cpu_to_le32(1);
|
||||
req->delay[0].eq_id = cpu_to_le32(eq_id);
|
||||
req->delay[0].phase = 0;
|
||||
req->delay[0].delay_multiplier = cpu_to_le32(eqd);
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
return status;
|
||||
}
|
||||
|
||||
int be_cmd_vlan_config(struct be_ctrl_info *ctrl, u32 if_id, u16 *vtag_array,
|
||||
u32 num, bool untagged, bool promiscuous)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_vlan_config *req = embedded_payload(wrb);
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
||||
OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
|
||||
|
||||
req->interface_id = if_id;
|
||||
req->promiscuous = promiscuous;
|
||||
req->untagged = untagged;
|
||||
req->num_vlan = num;
|
||||
if (!promiscuous) {
|
||||
memcpy(req->normal_vlan, vtag_array,
|
||||
req->num_vlan * sizeof(vtag_array[0]));
|
||||
}
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
return status;
|
||||
}
|
||||
|
||||
int be_cmd_promiscuous_config(struct be_ctrl_info *ctrl, u8 port_num, bool en)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_promiscuous_config *req = embedded_payload(wrb);
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
|
||||
OPCODE_ETH_PROMISCUOUS, sizeof(*req));
|
||||
|
||||
if (port_num)
|
||||
req->port1_promiscuous = en;
|
||||
else
|
||||
req->port0_promiscuous = en;
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
return status;
|
||||
}
|
||||
|
||||
int be_cmd_mcast_mac_set(struct be_ctrl_info *ctrl, u32 if_id, u8 *mac_table,
|
||||
u32 num, bool promiscuous)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_mcast_mac_config *req = embedded_payload(wrb);
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
||||
OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
|
||||
|
||||
req->interface_id = if_id;
|
||||
req->promiscuous = promiscuous;
|
||||
if (!promiscuous) {
|
||||
req->num_mac = cpu_to_le16(num);
|
||||
if (num)
|
||||
memcpy(req->mac, mac_table, ETH_ALEN * num);
|
||||
}
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
return status;
|
||||
}
|
||||
|
||||
int be_cmd_set_flow_control(struct be_ctrl_info *ctrl, u32 tx_fc, u32 rx_fc)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_set_flow_control *req = embedded_payload(wrb);
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
||||
OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
|
||||
|
||||
req->tx_flow_control = cpu_to_le16((u16)tx_fc);
|
||||
req->rx_flow_control = cpu_to_le16((u16)rx_fc);
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
return status;
|
||||
}
|
||||
|
||||
int be_cmd_get_flow_control(struct be_ctrl_info *ctrl, u32 *tx_fc, u32 *rx_fc)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_get_flow_control *req = embedded_payload(wrb);
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
||||
OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
if (!status) {
|
||||
struct be_cmd_resp_get_flow_control *resp =
|
||||
embedded_payload(wrb);
|
||||
*tx_fc = le16_to_cpu(resp->tx_flow_control);
|
||||
*rx_fc = le16_to_cpu(resp->rx_flow_control);
|
||||
}
|
||||
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
return status;
|
||||
}
|
||||
|
||||
int be_cmd_query_fw_cfg(struct be_ctrl_info *ctrl, u32 *port_num)
|
||||
{
|
||||
struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
|
||||
struct be_cmd_req_query_fw_cfg *req = embedded_payload(wrb);
|
||||
int status;
|
||||
|
||||
spin_lock(&ctrl->cmd_lock);
|
||||
|
||||
memset(wrb, 0, sizeof(*wrb));
|
||||
|
||||
be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
|
||||
|
||||
be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
|
||||
OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
|
||||
|
||||
status = be_mbox_db_ring(ctrl);
|
||||
if (!status) {
|
||||
struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
|
||||
*port_num = le32_to_cpu(resp->phys_port);
|
||||
}
|
||||
|
||||
spin_unlock(&ctrl->cmd_lock);
|
||||
return status;
|
||||
}
|
||||
688
drivers/net/benet/be_cmds.h
Normal file
688
drivers/net/benet/be_cmds.h
Normal file
@ -0,0 +1,688 @@
|
||||
/*
|
||||
* Copyright (C) 2005 - 2009 ServerEngines
|
||||
* All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation. The full GNU General
|
||||
* Public License is included in this distribution in the file called COPYING.
|
||||
*
|
||||
* Contact Information:
|
||||
* linux-drivers@serverengines.com
|
||||
*
|
||||
* ServerEngines
|
||||
* 209 N. Fair Oaks Ave
|
||||
* Sunnyvale, CA 94085
|
||||
*/
|
||||
|
||||
/*
|
||||
* The driver sends configuration and managements command requests to the
|
||||
* firmware in the BE. These requests are communicated to the processor
|
||||
* using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
|
||||
* WRB inside a MAILBOX.
|
||||
* The commands are serviced by the ARM processor in the BladeEngine's MPU.
|
||||
*/
|
||||
|
||||
struct be_sge {
|
||||
u32 pa_lo;
|
||||
u32 pa_hi;
|
||||
u32 len;
|
||||
};
|
||||
|
||||
#define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
|
||||
#define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
|
||||
#define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
|
||||
struct be_mcc_wrb {
|
||||
u32 embedded; /* dword 0 */
|
||||
u32 payload_length; /* dword 1 */
|
||||
u32 tag0; /* dword 2 */
|
||||
u32 tag1; /* dword 3 */
|
||||
u32 rsvd; /* dword 4 */
|
||||
union {
|
||||
u8 embedded_payload[236]; /* used by embedded cmds */
|
||||
struct be_sge sgl[19]; /* used by non-embedded cmds */
|
||||
} payload;
|
||||
};
|
||||
|
||||
#define CQE_FLAGS_VALID_MASK (1 << 31)
|
||||
#define CQE_FLAGS_ASYNC_MASK (1 << 30)
|
||||
#define CQE_FLAGS_COMPLETED_MASK (1 << 28)
|
||||
#define CQE_FLAGS_CONSUMED_MASK (1 << 27)
|
||||
|
||||
/* Completion Status */
|
||||
enum {
|
||||
MCC_STATUS_SUCCESS = 0x0,
|
||||
/* The client does not have sufficient privileges to execute the command */
|
||||
MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
|
||||
/* A parameter in the command was invalid. */
|
||||
MCC_STATUS_INVALID_PARAMETER = 0x2,
|
||||
/* There are insufficient chip resources to execute the command */
|
||||
MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
|
||||
/* The command is completing because the queue was getting flushed */
|
||||
MCC_STATUS_QUEUE_FLUSHING = 0x4,
|
||||
/* The command is completing with a DMA error */
|
||||
MCC_STATUS_DMA_FAILED = 0x5
|
||||
};
|
||||
|
||||
#define CQE_STATUS_COMPL_MASK 0xFFFF
|
||||
#define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
|
||||
#define CQE_STATUS_EXTD_MASK 0xFFFF
|
||||
#define CQE_STATUS_EXTD_SHIFT 0 /* bits 0 - 15 */
|
||||
|
||||
struct be_mcc_cq_entry {
|
||||
u32 status; /* dword 0 */
|
||||
u32 tag0; /* dword 1 */
|
||||
u32 tag1; /* dword 2 */
|
||||
u32 flags; /* dword 3 */
|
||||
};
|
||||
|
||||
struct be_mcc_mailbox {
|
||||
struct be_mcc_wrb wrb;
|
||||
struct be_mcc_cq_entry cqe;
|
||||
};
|
||||
|
||||
#define CMD_SUBSYSTEM_COMMON 0x1
|
||||
#define CMD_SUBSYSTEM_ETH 0x3
|
||||
|
||||
#define OPCODE_COMMON_NTWK_MAC_QUERY 1
|
||||
#define OPCODE_COMMON_NTWK_MAC_SET 2
|
||||
#define OPCODE_COMMON_NTWK_MULTICAST_SET 3
|
||||
#define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
|
||||
#define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
|
||||
#define OPCODE_COMMON_CQ_CREATE 12
|
||||
#define OPCODE_COMMON_EQ_CREATE 13
|
||||
#define OPCODE_COMMON_MCC_CREATE 21
|
||||
#define OPCODE_COMMON_NTWK_RX_FILTER 34
|
||||
#define OPCODE_COMMON_GET_FW_VERSION 35
|
||||
#define OPCODE_COMMON_SET_FLOW_CONTROL 36
|
||||
#define OPCODE_COMMON_GET_FLOW_CONTROL 37
|
||||
#define OPCODE_COMMON_SET_FRAME_SIZE 39
|
||||
#define OPCODE_COMMON_MODIFY_EQ_DELAY 41
|
||||
#define OPCODE_COMMON_FIRMWARE_CONFIG 42
|
||||
#define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
|
||||
#define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
|
||||
#define OPCODE_COMMON_CQ_DESTROY 54
|
||||
#define OPCODE_COMMON_EQ_DESTROY 55
|
||||
#define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
|
||||
#define OPCODE_COMMON_NTWK_PMAC_ADD 59
|
||||
#define OPCODE_COMMON_NTWK_PMAC_DEL 60
|
||||
|
||||
#define OPCODE_ETH_ACPI_CONFIG 2
|
||||
#define OPCODE_ETH_PROMISCUOUS 3
|
||||
#define OPCODE_ETH_GET_STATISTICS 4
|
||||
#define OPCODE_ETH_TX_CREATE 7
|
||||
#define OPCODE_ETH_RX_CREATE 8
|
||||
#define OPCODE_ETH_TX_DESTROY 9
|
||||
#define OPCODE_ETH_RX_DESTROY 10
|
||||
|
||||
struct be_cmd_req_hdr {
|
||||
u8 opcode; /* dword 0 */
|
||||
u8 subsystem; /* dword 0 */
|
||||
u8 port_number; /* dword 0 */
|
||||
u8 domain; /* dword 0 */
|
||||
u32 timeout; /* dword 1 */
|
||||
u32 request_length; /* dword 2 */
|
||||
u32 rsvd; /* dword 3 */
|
||||
};
|
||||
|
||||
#define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
|
||||
#define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
|
||||
struct be_cmd_resp_hdr {
|
||||
u32 info; /* dword 0 */
|
||||
u32 status; /* dword 1 */
|
||||
u32 response_length; /* dword 2 */
|
||||
u32 actual_resp_len; /* dword 3 */
|
||||
};
|
||||
|
||||
struct phys_addr {
|
||||
u32 lo;
|
||||
u32 hi;
|
||||
};
|
||||
|
||||
/**************************
|
||||
* BE Command definitions *
|
||||
**************************/
|
||||
|
||||
/* Pseudo amap definition in which each bit of the actual structure is defined
|
||||
* as a byte: used to calculate offset/shift/mask of each field */
|
||||
struct amap_eq_context {
|
||||
u8 cidx[13]; /* dword 0*/
|
||||
u8 rsvd0[3]; /* dword 0*/
|
||||
u8 epidx[13]; /* dword 0*/
|
||||
u8 valid; /* dword 0*/
|
||||
u8 rsvd1; /* dword 0*/
|
||||
u8 size; /* dword 0*/
|
||||
u8 pidx[13]; /* dword 1*/
|
||||
u8 rsvd2[3]; /* dword 1*/
|
||||
u8 pd[10]; /* dword 1*/
|
||||
u8 count[3]; /* dword 1*/
|
||||
u8 solevent; /* dword 1*/
|
||||
u8 stalled; /* dword 1*/
|
||||
u8 armed; /* dword 1*/
|
||||
u8 rsvd3[4]; /* dword 2*/
|
||||
u8 func[8]; /* dword 2*/
|
||||
u8 rsvd4; /* dword 2*/
|
||||
u8 delaymult[10]; /* dword 2*/
|
||||
u8 rsvd5[2]; /* dword 2*/
|
||||
u8 phase[2]; /* dword 2*/
|
||||
u8 nodelay; /* dword 2*/
|
||||
u8 rsvd6[4]; /* dword 2*/
|
||||
u8 rsvd7[32]; /* dword 3*/
|
||||
} __packed;
|
||||
|
||||
struct be_cmd_req_eq_create {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u16 num_pages; /* sword */
|
||||
u16 rsvd0; /* sword */
|
||||
u8 context[sizeof(struct amap_eq_context) / 8];
|
||||
struct phys_addr pages[8];
|
||||
} __packed;
|
||||
|
||||
struct be_cmd_resp_eq_create {
|
||||
struct be_cmd_resp_hdr resp_hdr;
|
||||
u16 eq_id; /* sword */
|
||||
u16 rsvd0; /* sword */
|
||||
} __packed;
|
||||
|
||||
/******************** Mac query ***************************/
|
||||
enum {
|
||||
MAC_ADDRESS_TYPE_STORAGE = 0x0,
|
||||
MAC_ADDRESS_TYPE_NETWORK = 0x1,
|
||||
MAC_ADDRESS_TYPE_PD = 0x2,
|
||||
MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
|
||||
};
|
||||
|
||||
struct mac_addr {
|
||||
u16 size_of_struct;
|
||||
u8 addr[ETH_ALEN];
|
||||
} __packed;
|
||||
|
||||
struct be_cmd_req_mac_query {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u8 type;
|
||||
u8 permanent;
|
||||
u16 if_id;
|
||||
} __packed;
|
||||
|
||||
struct be_cmd_resp_mac_query {
|
||||
struct be_cmd_resp_hdr hdr;
|
||||
struct mac_addr mac;
|
||||
};
|
||||
|
||||
/******************** PMac Add ***************************/
|
||||
struct be_cmd_req_pmac_add {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u32 if_id;
|
||||
u8 mac_address[ETH_ALEN];
|
||||
u8 rsvd0[2];
|
||||
} __packed;
|
||||
|
||||
struct be_cmd_resp_pmac_add {
|
||||
struct be_cmd_resp_hdr hdr;
|
||||
u32 pmac_id;
|
||||
};
|
||||
|
||||
/******************** PMac Del ***************************/
|
||||
struct be_cmd_req_pmac_del {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u32 if_id;
|
||||
u32 pmac_id;
|
||||
};
|
||||
|
||||
/******************** Create CQ ***************************/
|
||||
/* Pseudo amap definition in which each bit of the actual structure is defined
|
||||
* as a byte: used to calculate offset/shift/mask of each field */
|
||||
struct amap_cq_context {
|
||||
u8 cidx[11]; /* dword 0*/
|
||||
u8 rsvd0; /* dword 0*/
|
||||
u8 coalescwm[2]; /* dword 0*/
|
||||
u8 nodelay; /* dword 0*/
|
||||
u8 epidx[11]; /* dword 0*/
|
||||
u8 rsvd1; /* dword 0*/
|
||||
u8 count[2]; /* dword 0*/
|
||||
u8 valid; /* dword 0*/
|
||||
u8 solevent; /* dword 0*/
|
||||
u8 eventable; /* dword 0*/
|
||||
u8 pidx[11]; /* dword 1*/
|
||||
u8 rsvd2; /* dword 1*/
|
||||
u8 pd[10]; /* dword 1*/
|
||||
u8 eqid[8]; /* dword 1*/
|
||||
u8 stalled; /* dword 1*/
|
||||
u8 armed; /* dword 1*/
|
||||
u8 rsvd3[4]; /* dword 2*/
|
||||
u8 func[8]; /* dword 2*/
|
||||
u8 rsvd4[20]; /* dword 2*/
|
||||
u8 rsvd5[32]; /* dword 3*/
|
||||
} __packed;
|
||||
|
||||
struct be_cmd_req_cq_create {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u16 num_pages;
|
||||
u16 rsvd0;
|
||||
u8 context[sizeof(struct amap_cq_context) / 8];
|
||||
struct phys_addr pages[8];
|
||||
} __packed;
|
||||
|
||||
struct be_cmd_resp_cq_create {
|
||||
struct be_cmd_resp_hdr hdr;
|
||||
u16 cq_id;
|
||||
u16 rsvd0;
|
||||
} __packed;
|
||||
|
||||
/******************** Create TxQ ***************************/
|
||||
#define BE_ETH_TX_RING_TYPE_STANDARD 2
|
||||
#define BE_ULP1_NUM 1
|
||||
|
||||
/* Pseudo amap definition in which each bit of the actual structure is defined
|
||||
* as a byte: used to calculate offset/shift/mask of each field */
|
||||
struct amap_tx_context {
|
||||
u8 rsvd0[16]; /* dword 0 */
|
||||
u8 tx_ring_size[4]; /* dword 0 */
|
||||
u8 rsvd1[26]; /* dword 0 */
|
||||
u8 pci_func_id[8]; /* dword 1 */
|
||||
u8 rsvd2[9]; /* dword 1 */
|
||||
u8 ctx_valid; /* dword 1 */
|
||||
u8 cq_id_send[16]; /* dword 2 */
|
||||
u8 rsvd3[16]; /* dword 2 */
|
||||
u8 rsvd4[32]; /* dword 3 */
|
||||
u8 rsvd5[32]; /* dword 4 */
|
||||
u8 rsvd6[32]; /* dword 5 */
|
||||
u8 rsvd7[32]; /* dword 6 */
|
||||
u8 rsvd8[32]; /* dword 7 */
|
||||
u8 rsvd9[32]; /* dword 8 */
|
||||
u8 rsvd10[32]; /* dword 9 */
|
||||
u8 rsvd11[32]; /* dword 10 */
|
||||
u8 rsvd12[32]; /* dword 11 */
|
||||
u8 rsvd13[32]; /* dword 12 */
|
||||
u8 rsvd14[32]; /* dword 13 */
|
||||
u8 rsvd15[32]; /* dword 14 */
|
||||
u8 rsvd16[32]; /* dword 15 */
|
||||
} __packed;
|
||||
|
||||
struct be_cmd_req_eth_tx_create {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u8 num_pages;
|
||||
u8 ulp_num;
|
||||
u8 type;
|
||||
u8 bound_port;
|
||||
u8 context[sizeof(struct amap_tx_context) / 8];
|
||||
struct phys_addr pages[8];
|
||||
} __packed;
|
||||
|
||||
struct be_cmd_resp_eth_tx_create {
|
||||
struct be_cmd_resp_hdr hdr;
|
||||
u16 cid;
|
||||
u16 rsvd0;
|
||||
} __packed;
|
||||
|
||||
/******************** Create RxQ ***************************/
|
||||
struct be_cmd_req_eth_rx_create {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u16 cq_id;
|
||||
u8 frag_size;
|
||||
u8 num_pages;
|
||||
struct phys_addr pages[2];
|
||||
u32 interface_id;
|
||||
u16 max_frame_size;
|
||||
u16 rsvd0;
|
||||
u32 rss_queue;
|
||||
} __packed;
|
||||
|
||||
struct be_cmd_resp_eth_rx_create {
|
||||
struct be_cmd_resp_hdr hdr;
|
||||
u16 id;
|
||||
u8 cpu_id;
|
||||
u8 rsvd0;
|
||||
} __packed;
|
||||
|
||||
/******************** Q Destroy ***************************/
|
||||
/* Type of Queue to be destroyed */
|
||||
enum {
|
||||
QTYPE_EQ = 1,
|
||||
QTYPE_CQ,
|
||||
QTYPE_TXQ,
|
||||
QTYPE_RXQ
|
||||
};
|
||||
|
||||
struct be_cmd_req_q_destroy {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u16 id;
|
||||
u16 bypass_flush; /* valid only for rx q destroy */
|
||||
} __packed;
|
||||
|
||||
/************ I/f Create (it's actually I/f Config Create)**********/
|
||||
|
||||
/* Capability flags for the i/f */
|
||||
enum be_if_flags {
|
||||
BE_IF_FLAGS_RSS = 0x4,
|
||||
BE_IF_FLAGS_PROMISCUOUS = 0x8,
|
||||
BE_IF_FLAGS_BROADCAST = 0x10,
|
||||
BE_IF_FLAGS_UNTAGGED = 0x20,
|
||||
BE_IF_FLAGS_ULP = 0x40,
|
||||
BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
|
||||
BE_IF_FLAGS_VLAN = 0x100,
|
||||
BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
|
||||
BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
|
||||
BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
|
||||
};
|
||||
|
||||
/* An RX interface is an object with one or more MAC addresses and
|
||||
* filtering capabilities. */
|
||||
struct be_cmd_req_if_create {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u32 version; /* ignore currntly */
|
||||
u32 capability_flags;
|
||||
u32 enable_flags;
|
||||
u8 mac_addr[ETH_ALEN];
|
||||
u8 rsvd0;
|
||||
u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
|
||||
u32 vlan_tag; /* not used currently */
|
||||
} __packed;
|
||||
|
||||
struct be_cmd_resp_if_create {
|
||||
struct be_cmd_resp_hdr hdr;
|
||||
u32 interface_id;
|
||||
u32 pmac_id;
|
||||
};
|
||||
|
||||
/****** I/f Destroy(it's actually I/f Config Destroy )**********/
|
||||
struct be_cmd_req_if_destroy {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u32 interface_id;
|
||||
};
|
||||
|
||||
/*************** HW Stats Get **********************************/
|
||||
struct be_port_rxf_stats {
|
||||
u32 rx_bytes_lsd; /* dword 0*/
|
||||
u32 rx_bytes_msd; /* dword 1*/
|
||||
u32 rx_total_frames; /* dword 2*/
|
||||
u32 rx_unicast_frames; /* dword 3*/
|
||||
u32 rx_multicast_frames; /* dword 4*/
|
||||
u32 rx_broadcast_frames; /* dword 5*/
|
||||
u32 rx_crc_errors; /* dword 6*/
|
||||
u32 rx_alignment_symbol_errors; /* dword 7*/
|
||||
u32 rx_pause_frames; /* dword 8*/
|
||||
u32 rx_control_frames; /* dword 9*/
|
||||
u32 rx_in_range_errors; /* dword 10*/
|
||||
u32 rx_out_range_errors; /* dword 11*/
|
||||
u32 rx_frame_too_long; /* dword 12*/
|
||||
u32 rx_address_match_errors; /* dword 13*/
|
||||
u32 rx_vlan_mismatch; /* dword 14*/
|
||||
u32 rx_dropped_too_small; /* dword 15*/
|
||||
u32 rx_dropped_too_short; /* dword 16*/
|
||||
u32 rx_dropped_header_too_small; /* dword 17*/
|
||||
u32 rx_dropped_tcp_length; /* dword 18*/
|
||||
u32 rx_dropped_runt; /* dword 19*/
|
||||
u32 rx_64_byte_packets; /* dword 20*/
|
||||
u32 rx_65_127_byte_packets; /* dword 21*/
|
||||
u32 rx_128_256_byte_packets; /* dword 22*/
|
||||
u32 rx_256_511_byte_packets; /* dword 23*/
|
||||
u32 rx_512_1023_byte_packets; /* dword 24*/
|
||||
u32 rx_1024_1518_byte_packets; /* dword 25*/
|
||||
u32 rx_1519_2047_byte_packets; /* dword 26*/
|
||||
u32 rx_2048_4095_byte_packets; /* dword 27*/
|
||||
u32 rx_4096_8191_byte_packets; /* dword 28*/
|
||||
u32 rx_8192_9216_byte_packets; /* dword 29*/
|
||||
u32 rx_ip_checksum_errs; /* dword 30*/
|
||||
u32 rx_tcp_checksum_errs; /* dword 31*/
|
||||
u32 rx_udp_checksum_errs; /* dword 32*/
|
||||
u32 rx_non_rss_packets; /* dword 33*/
|
||||
u32 rx_ipv4_packets; /* dword 34*/
|
||||
u32 rx_ipv6_packets; /* dword 35*/
|
||||
u32 rx_ipv4_bytes_lsd; /* dword 36*/
|
||||
u32 rx_ipv4_bytes_msd; /* dword 37*/
|
||||
u32 rx_ipv6_bytes_lsd; /* dword 38*/
|
||||
u32 rx_ipv6_bytes_msd; /* dword 39*/
|
||||
u32 rx_chute1_packets; /* dword 40*/
|
||||
u32 rx_chute2_packets; /* dword 41*/
|
||||
u32 rx_chute3_packets; /* dword 42*/
|
||||
u32 rx_management_packets; /* dword 43*/
|
||||
u32 rx_switched_unicast_packets; /* dword 44*/
|
||||
u32 rx_switched_multicast_packets; /* dword 45*/
|
||||
u32 rx_switched_broadcast_packets; /* dword 46*/
|
||||
u32 tx_bytes_lsd; /* dword 47*/
|
||||
u32 tx_bytes_msd; /* dword 48*/
|
||||
u32 tx_unicastframes; /* dword 49*/
|
||||
u32 tx_multicastframes; /* dword 50*/
|
||||
u32 tx_broadcastframes; /* dword 51*/
|
||||
u32 tx_pauseframes; /* dword 52*/
|
||||
u32 tx_controlframes; /* dword 53*/
|
||||
u32 tx_64_byte_packets; /* dword 54*/
|
||||
u32 tx_65_127_byte_packets; /* dword 55*/
|
||||
u32 tx_128_256_byte_packets; /* dword 56*/
|
||||
u32 tx_256_511_byte_packets; /* dword 57*/
|
||||
u32 tx_512_1023_byte_packets; /* dword 58*/
|
||||
u32 tx_1024_1518_byte_packets; /* dword 59*/
|
||||
u32 tx_1519_2047_byte_packets; /* dword 60*/
|
||||
u32 tx_2048_4095_byte_packets; /* dword 61*/
|
||||
u32 tx_4096_8191_byte_packets; /* dword 62*/
|
||||
u32 tx_8192_9216_byte_packets; /* dword 63*/
|
||||
u32 rx_fifo_overflow; /* dword 64*/
|
||||
u32 rx_input_fifo_overflow; /* dword 65*/
|
||||
};
|
||||
|
||||
struct be_rxf_stats {
|
||||
struct be_port_rxf_stats port[2];
|
||||
u32 rx_drops_no_pbuf; /* dword 132*/
|
||||
u32 rx_drops_no_txpb; /* dword 133*/
|
||||
u32 rx_drops_no_erx_descr; /* dword 134*/
|
||||
u32 rx_drops_no_tpre_descr; /* dword 135*/
|
||||
u32 management_rx_port_packets; /* dword 136*/
|
||||
u32 management_rx_port_bytes; /* dword 137*/
|
||||
u32 management_rx_port_pause_frames; /* dword 138*/
|
||||
u32 management_rx_port_errors; /* dword 139*/
|
||||
u32 management_tx_port_packets; /* dword 140*/
|
||||
u32 management_tx_port_bytes; /* dword 141*/
|
||||
u32 management_tx_port_pause; /* dword 142*/
|
||||
u32 management_rx_port_rxfifo_overflow; /* dword 143*/
|
||||
u32 rx_drops_too_many_frags; /* dword 144*/
|
||||
u32 rx_drops_invalid_ring; /* dword 145*/
|
||||
u32 forwarded_packets; /* dword 146*/
|
||||
u32 rx_drops_mtu; /* dword 147*/
|
||||
u32 rsvd0[15];
|
||||
};
|
||||
|
||||
struct be_erx_stats {
|
||||
u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
|
||||
u32 debug_wdma_sent_hold; /* dword 44*/
|
||||
u32 debug_wdma_pbfree_sent_hold; /* dword 45*/
|
||||
u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
|
||||
u32 debug_pmem_pbuf_dealloc; /* dword 47*/
|
||||
};
|
||||
|
||||
struct be_hw_stats {
|
||||
struct be_rxf_stats rxf;
|
||||
u32 rsvd[48];
|
||||
struct be_erx_stats erx;
|
||||
};
|
||||
|
||||
struct be_cmd_req_get_stats {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u8 rsvd[sizeof(struct be_hw_stats)];
|
||||
};
|
||||
|
||||
struct be_cmd_resp_get_stats {
|
||||
struct be_cmd_resp_hdr hdr;
|
||||
struct be_hw_stats hw_stats;
|
||||
};
|
||||
|
||||
struct be_cmd_req_vlan_config {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u8 interface_id;
|
||||
u8 promiscuous;
|
||||
u8 untagged;
|
||||
u8 num_vlan;
|
||||
u16 normal_vlan[64];
|
||||
} __packed;
|
||||
|
||||
struct be_cmd_req_promiscuous_config {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u8 port0_promiscuous;
|
||||
u8 port1_promiscuous;
|
||||
u16 rsvd0;
|
||||
} __packed;
|
||||
|
||||
struct macaddr {
|
||||
u8 byte[ETH_ALEN];
|
||||
};
|
||||
|
||||
struct be_cmd_req_mcast_mac_config {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u16 num_mac;
|
||||
u8 promiscuous;
|
||||
u8 interface_id;
|
||||
struct macaddr mac[32];
|
||||
} __packed;
|
||||
|
||||
static inline struct be_hw_stats *
|
||||
hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
|
||||
{
|
||||
return &cmd->hw_stats;
|
||||
}
|
||||
|
||||
/******************** Link Status Query *******************/
|
||||
struct be_cmd_req_link_status {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u32 rsvd;
|
||||
};
|
||||
|
||||
struct be_link_info {
|
||||
u8 duplex;
|
||||
u8 speed;
|
||||
u8 fault;
|
||||
};
|
||||
|
||||
enum {
|
||||
PHY_LINK_DUPLEX_NONE = 0x0,
|
||||
PHY_LINK_DUPLEX_HALF = 0x1,
|
||||
PHY_LINK_DUPLEX_FULL = 0x2
|
||||
};
|
||||
|
||||
enum {
|
||||
PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
|
||||
PHY_LINK_SPEED_10MBPS = 0x1,
|
||||
PHY_LINK_SPEED_100MBPS = 0x2,
|
||||
PHY_LINK_SPEED_1GBPS = 0x3,
|
||||
PHY_LINK_SPEED_10GBPS = 0x4
|
||||
};
|
||||
|
||||
struct be_cmd_resp_link_status {
|
||||
struct be_cmd_resp_hdr hdr;
|
||||
u8 physical_port;
|
||||
u8 mac_duplex;
|
||||
u8 mac_speed;
|
||||
u8 mac_fault;
|
||||
u8 mgmt_mac_duplex;
|
||||
u8 mgmt_mac_speed;
|
||||
u16 rsvd0;
|
||||
} __packed;
|
||||
|
||||
/******************** Get FW Version *******************/
|
||||
#define FW_VER_LEN 32
|
||||
struct be_cmd_req_get_fw_version {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u8 rsvd0[FW_VER_LEN];
|
||||
u8 rsvd1[FW_VER_LEN];
|
||||
} __packed;
|
||||
|
||||
struct be_cmd_resp_get_fw_version {
|
||||
struct be_cmd_resp_hdr hdr;
|
||||
u8 firmware_version_string[FW_VER_LEN];
|
||||
u8 fw_on_flash_version_string[FW_VER_LEN];
|
||||
} __packed;
|
||||
|
||||
/******************** Set Flow Contrl *******************/
|
||||
struct be_cmd_req_set_flow_control {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u16 tx_flow_control;
|
||||
u16 rx_flow_control;
|
||||
} __packed;
|
||||
|
||||
/******************** Get Flow Contrl *******************/
|
||||
struct be_cmd_req_get_flow_control {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u32 rsvd;
|
||||
};
|
||||
|
||||
struct be_cmd_resp_get_flow_control {
|
||||
struct be_cmd_resp_hdr hdr;
|
||||
u16 tx_flow_control;
|
||||
u16 rx_flow_control;
|
||||
} __packed;
|
||||
|
||||
/******************** Modify EQ Delay *******************/
|
||||
struct be_cmd_req_modify_eq_delay {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u32 num_eq;
|
||||
struct {
|
||||
u32 eq_id;
|
||||
u32 phase;
|
||||
u32 delay_multiplier;
|
||||
} delay[8];
|
||||
} __packed;
|
||||
|
||||
struct be_cmd_resp_modify_eq_delay {
|
||||
struct be_cmd_resp_hdr hdr;
|
||||
u32 rsvd0;
|
||||
} __packed;
|
||||
|
||||
/******************** Get FW Config *******************/
|
||||
struct be_cmd_req_query_fw_cfg {
|
||||
struct be_cmd_req_hdr hdr;
|
||||
u32 rsvd[30];
|
||||
};
|
||||
|
||||
struct be_cmd_resp_query_fw_cfg {
|
||||
struct be_cmd_resp_hdr hdr;
|
||||
u32 be_config_number;
|
||||
u32 asic_revision;
|
||||
u32 phys_port;
|
||||
u32 function_mode;
|
||||
u32 rsvd[26];
|
||||
};
|
||||
|
||||
extern int be_pci_fnum_get(struct be_ctrl_info *ctrl);
|
||||
extern int be_cmd_POST(struct be_ctrl_info *ctrl);
|
||||
extern int be_cmd_mac_addr_query(struct be_ctrl_info *ctrl, u8 *mac_addr,
|
||||
u8 type, bool permanent, u32 if_handle);
|
||||
extern int be_cmd_pmac_add(struct be_ctrl_info *ctrl, u8 *mac_addr,
|
||||
u32 if_id, u32 *pmac_id);
|
||||
extern int be_cmd_pmac_del(struct be_ctrl_info *ctrl, u32 if_id, u32 pmac_id);
|
||||
extern int be_cmd_if_create(struct be_ctrl_info *ctrl, u32 if_flags, u8 *mac,
|
||||
bool pmac_invalid, u32 *if_handle, u32 *pmac_id);
|
||||
extern int be_cmd_if_destroy(struct be_ctrl_info *ctrl, u32 if_handle);
|
||||
extern int be_cmd_eq_create(struct be_ctrl_info *ctrl,
|
||||
struct be_queue_info *eq, int eq_delay);
|
||||
extern int be_cmd_cq_create(struct be_ctrl_info *ctrl,
|
||||
struct be_queue_info *cq, struct be_queue_info *eq,
|
||||
bool sol_evts, bool no_delay,
|
||||
int num_cqe_dma_coalesce);
|
||||
extern int be_cmd_txq_create(struct be_ctrl_info *ctrl,
|
||||
struct be_queue_info *txq,
|
||||
struct be_queue_info *cq);
|
||||
extern int be_cmd_rxq_create(struct be_ctrl_info *ctrl,
|
||||
struct be_queue_info *rxq, u16 cq_id,
|
||||
u16 frag_size, u16 max_frame_size, u32 if_id,
|
||||
u32 rss);
|
||||
extern int be_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
|
||||
int type);
|
||||
extern int be_cmd_link_status_query(struct be_ctrl_info *ctrl,
|
||||
struct be_link_info *link);
|
||||
extern int be_cmd_reset(struct be_ctrl_info *ctrl);
|
||||
extern int be_cmd_get_stats(struct be_ctrl_info *ctrl,
|
||||
struct be_dma_mem *nonemb_cmd);
|
||||
extern int be_cmd_get_fw_ver(struct be_ctrl_info *ctrl, char *fw_ver);
|
||||
|
||||
extern int be_cmd_modify_eqd(struct be_ctrl_info *ctrl, u32 eq_id, u32 eqd);
|
||||
extern int be_cmd_vlan_config(struct be_ctrl_info *ctrl, u32 if_id,
|
||||
u16 *vtag_array, u32 num, bool untagged,
|
||||
bool promiscuous);
|
||||
extern int be_cmd_promiscuous_config(struct be_ctrl_info *ctrl,
|
||||
u8 port_num, bool en);
|
||||
extern int be_cmd_mcast_mac_set(struct be_ctrl_info *ctrl, u32 if_id,
|
||||
u8 *mac_table, u32 num, bool promiscuous);
|
||||
extern int be_cmd_set_flow_control(struct be_ctrl_info *ctrl,
|
||||
u32 tx_fc, u32 rx_fc);
|
||||
extern int be_cmd_get_flow_control(struct be_ctrl_info *ctrl,
|
||||
u32 *tx_fc, u32 *rx_fc);
|
||||
extern int be_cmd_query_fw_cfg(struct be_ctrl_info *ctrl, u32 *port_num);
|
||||
362
drivers/net/benet/be_ethtool.c
Normal file
362
drivers/net/benet/be_ethtool.c
Normal file
@ -0,0 +1,362 @@
|
||||
/*
|
||||
* Copyright (C) 2005 - 2009 ServerEngines
|
||||
* All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation. The full GNU General
|
||||
* Public License is included in this distribution in the file called COPYING.
|
||||
*
|
||||
* Contact Information:
|
||||
* linux-drivers@serverengines.com
|
||||
*
|
||||
* ServerEngines
|
||||
* 209 N. Fair Oaks Ave
|
||||
* Sunnyvale, CA 94085
|
||||
*/
|
||||
|
||||
#include "be.h"
|
||||
#include <linux/ethtool.h>
|
||||
|
||||
struct be_ethtool_stat {
|
||||
char desc[ETH_GSTRING_LEN];
|
||||
int type;
|
||||
int size;
|
||||
int offset;
|
||||
};
|
||||
|
||||
enum {NETSTAT, PORTSTAT, MISCSTAT, DRVSTAT, ERXSTAT};
|
||||
#define FIELDINFO(_struct, field) FIELD_SIZEOF(_struct, field), \
|
||||
offsetof(_struct, field)
|
||||
#define NETSTAT_INFO(field) #field, NETSTAT,\
|
||||
FIELDINFO(struct net_device_stats,\
|
||||
field)
|
||||
#define DRVSTAT_INFO(field) #field, DRVSTAT,\
|
||||
FIELDINFO(struct be_drvr_stats, field)
|
||||
#define MISCSTAT_INFO(field) #field, MISCSTAT,\
|
||||
FIELDINFO(struct be_rxf_stats, field)
|
||||
#define PORTSTAT_INFO(field) #field, PORTSTAT,\
|
||||
FIELDINFO(struct be_port_rxf_stats, \
|
||||
field)
|
||||
#define ERXSTAT_INFO(field) #field, ERXSTAT,\
|
||||
FIELDINFO(struct be_erx_stats, field)
|
||||
|
||||
static const struct be_ethtool_stat et_stats[] = {
|
||||
{NETSTAT_INFO(rx_packets)},
|
||||
{NETSTAT_INFO(tx_packets)},
|
||||
{NETSTAT_INFO(rx_bytes)},
|
||||
{NETSTAT_INFO(tx_bytes)},
|
||||
{NETSTAT_INFO(rx_errors)},
|
||||
{NETSTAT_INFO(tx_errors)},
|
||||
{NETSTAT_INFO(rx_dropped)},
|
||||
{NETSTAT_INFO(tx_dropped)},
|
||||
{DRVSTAT_INFO(be_tx_reqs)},
|
||||
{DRVSTAT_INFO(be_tx_stops)},
|
||||
{DRVSTAT_INFO(be_fwd_reqs)},
|
||||
{DRVSTAT_INFO(be_tx_wrbs)},
|
||||
{DRVSTAT_INFO(be_polls)},
|
||||
{DRVSTAT_INFO(be_tx_events)},
|
||||
{DRVSTAT_INFO(be_rx_events)},
|
||||
{DRVSTAT_INFO(be_tx_compl)},
|
||||
{DRVSTAT_INFO(be_rx_compl)},
|
||||
{DRVSTAT_INFO(be_ethrx_post_fail)},
|
||||
{DRVSTAT_INFO(be_802_3_dropped_frames)},
|
||||
{DRVSTAT_INFO(be_802_3_malformed_frames)},
|
||||
{DRVSTAT_INFO(be_tx_rate)},
|
||||
{DRVSTAT_INFO(be_rx_rate)},
|
||||
{PORTSTAT_INFO(rx_unicast_frames)},
|
||||
{PORTSTAT_INFO(rx_multicast_frames)},
|
||||
{PORTSTAT_INFO(rx_broadcast_frames)},
|
||||
{PORTSTAT_INFO(rx_crc_errors)},
|
||||
{PORTSTAT_INFO(rx_alignment_symbol_errors)},
|
||||
{PORTSTAT_INFO(rx_pause_frames)},
|
||||
{PORTSTAT_INFO(rx_control_frames)},
|
||||
{PORTSTAT_INFO(rx_in_range_errors)},
|
||||
{PORTSTAT_INFO(rx_out_range_errors)},
|
||||
{PORTSTAT_INFO(rx_frame_too_long)},
|
||||
{PORTSTAT_INFO(rx_address_match_errors)},
|
||||
{PORTSTAT_INFO(rx_vlan_mismatch)},
|
||||
{PORTSTAT_INFO(rx_dropped_too_small)},
|
||||
{PORTSTAT_INFO(rx_dropped_too_short)},
|
||||
{PORTSTAT_INFO(rx_dropped_header_too_small)},
|
||||
{PORTSTAT_INFO(rx_dropped_tcp_length)},
|
||||
{PORTSTAT_INFO(rx_dropped_runt)},
|
||||
{PORTSTAT_INFO(rx_fifo_overflow)},
|
||||
{PORTSTAT_INFO(rx_input_fifo_overflow)},
|
||||
{PORTSTAT_INFO(rx_ip_checksum_errs)},
|
||||
{PORTSTAT_INFO(rx_tcp_checksum_errs)},
|
||||
{PORTSTAT_INFO(rx_udp_checksum_errs)},
|
||||
{PORTSTAT_INFO(rx_non_rss_packets)},
|
||||
{PORTSTAT_INFO(rx_ipv4_packets)},
|
||||
{PORTSTAT_INFO(rx_ipv6_packets)},
|
||||
{PORTSTAT_INFO(tx_unicastframes)},
|
||||
{PORTSTAT_INFO(tx_multicastframes)},
|
||||
{PORTSTAT_INFO(tx_broadcastframes)},
|
||||
{PORTSTAT_INFO(tx_pauseframes)},
|
||||
{PORTSTAT_INFO(tx_controlframes)},
|
||||
{MISCSTAT_INFO(rx_drops_no_pbuf)},
|
||||
{MISCSTAT_INFO(rx_drops_no_txpb)},
|
||||
{MISCSTAT_INFO(rx_drops_no_erx_descr)},
|
||||
{MISCSTAT_INFO(rx_drops_no_tpre_descr)},
|
||||
{MISCSTAT_INFO(rx_drops_too_many_frags)},
|
||||
{MISCSTAT_INFO(rx_drops_invalid_ring)},
|
||||
{MISCSTAT_INFO(forwarded_packets)},
|
||||
{MISCSTAT_INFO(rx_drops_mtu)},
|
||||
{ERXSTAT_INFO(rx_drops_no_fragments)},
|
||||
};
|
||||
#define ETHTOOL_STATS_NUM ARRAY_SIZE(et_stats)
|
||||
|
||||
static void
|
||||
be_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo)
|
||||
{
|
||||
struct be_adapter *adapter = netdev_priv(netdev);
|
||||
|
||||
strcpy(drvinfo->driver, DRV_NAME);
|
||||
strcpy(drvinfo->version, DRV_VER);
|
||||
strncpy(drvinfo->fw_version, adapter->fw_ver, FW_VER_LEN);
|
||||
strcpy(drvinfo->bus_info, pci_name(adapter->pdev));
|
||||
drvinfo->testinfo_len = 0;
|
||||
drvinfo->regdump_len = 0;
|
||||
drvinfo->eedump_len = 0;
|
||||
}
|
||||
|
||||
static int
|
||||
be_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce)
|
||||
{
|
||||
struct be_adapter *adapter = netdev_priv(netdev);
|
||||
struct be_eq_obj *rx_eq = &adapter->rx_eq;
|
||||
struct be_eq_obj *tx_eq = &adapter->tx_eq;
|
||||
|
||||
coalesce->rx_max_coalesced_frames = adapter->max_rx_coal;
|
||||
|
||||
coalesce->rx_coalesce_usecs = rx_eq->cur_eqd;
|
||||
coalesce->rx_coalesce_usecs_high = rx_eq->max_eqd;
|
||||
coalesce->rx_coalesce_usecs_low = rx_eq->min_eqd;
|
||||
|
||||
coalesce->tx_coalesce_usecs = tx_eq->cur_eqd;
|
||||
coalesce->tx_coalesce_usecs_high = tx_eq->max_eqd;
|
||||
coalesce->tx_coalesce_usecs_low = tx_eq->min_eqd;
|
||||
|
||||
coalesce->use_adaptive_rx_coalesce = rx_eq->enable_aic;
|
||||
coalesce->use_adaptive_tx_coalesce = tx_eq->enable_aic;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* This routine is used to set interrup coalescing delay *as well as*
|
||||
* the number of pkts to coalesce for LRO.
|
||||
*/
|
||||
static int
|
||||
be_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce)
|
||||
{
|
||||
struct be_adapter *adapter = netdev_priv(netdev);
|
||||
struct be_ctrl_info *ctrl = &adapter->ctrl;
|
||||
struct be_eq_obj *rx_eq = &adapter->rx_eq;
|
||||
struct be_eq_obj *tx_eq = &adapter->tx_eq;
|
||||
u32 tx_max, tx_min, tx_cur;
|
||||
u32 rx_max, rx_min, rx_cur;
|
||||
int status = 0;
|
||||
|
||||
if (coalesce->use_adaptive_tx_coalesce == 1)
|
||||
return -EINVAL;
|
||||
|
||||
adapter->max_rx_coal = coalesce->rx_max_coalesced_frames;
|
||||
if (adapter->max_rx_coal > MAX_SKB_FRAGS)
|
||||
adapter->max_rx_coal = MAX_SKB_FRAGS - 1;
|
||||
|
||||
/* if AIC is being turned on now, start with an EQD of 0 */
|
||||
if (rx_eq->enable_aic == 0 &&
|
||||
coalesce->use_adaptive_rx_coalesce == 1) {
|
||||
rx_eq->cur_eqd = 0;
|
||||
}
|
||||
rx_eq->enable_aic = coalesce->use_adaptive_rx_coalesce;
|
||||
|
||||
rx_max = coalesce->rx_coalesce_usecs_high;
|
||||
rx_min = coalesce->rx_coalesce_usecs_low;
|
||||
rx_cur = coalesce->rx_coalesce_usecs;
|
||||
|
||||
tx_max = coalesce->tx_coalesce_usecs_high;
|
||||
tx_min = coalesce->tx_coalesce_usecs_low;
|
||||
tx_cur = coalesce->tx_coalesce_usecs;
|
||||
|
||||
if (tx_cur > BE_MAX_EQD)
|
||||
tx_cur = BE_MAX_EQD;
|
||||
if (tx_eq->cur_eqd != tx_cur) {
|
||||
status = be_cmd_modify_eqd(ctrl, tx_eq->q.id, tx_cur);
|
||||
if (!status)
|
||||
tx_eq->cur_eqd = tx_cur;
|
||||
}
|
||||
|
||||
if (rx_eq->enable_aic) {
|
||||
if (rx_max > BE_MAX_EQD)
|
||||
rx_max = BE_MAX_EQD;
|
||||
if (rx_min > rx_max)
|
||||
rx_min = rx_max;
|
||||
rx_eq->max_eqd = rx_max;
|
||||
rx_eq->min_eqd = rx_min;
|
||||
if (rx_eq->cur_eqd > rx_max)
|
||||
rx_eq->cur_eqd = rx_max;
|
||||
if (rx_eq->cur_eqd < rx_min)
|
||||
rx_eq->cur_eqd = rx_min;
|
||||
} else {
|
||||
if (rx_cur > BE_MAX_EQD)
|
||||
rx_cur = BE_MAX_EQD;
|
||||
if (rx_eq->cur_eqd != rx_cur) {
|
||||
status = be_cmd_modify_eqd(ctrl, rx_eq->q.id, rx_cur);
|
||||
if (!status)
|
||||
rx_eq->cur_eqd = rx_cur;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 be_get_rx_csum(struct net_device *netdev)
|
||||
{
|
||||
struct be_adapter *adapter = netdev_priv(netdev);
|
||||
|
||||
return adapter->rx_csum;
|
||||
}
|
||||
|
||||
static int be_set_rx_csum(struct net_device *netdev, uint32_t data)
|
||||
{
|
||||
struct be_adapter *adapter = netdev_priv(netdev);
|
||||
|
||||
if (data)
|
||||
adapter->rx_csum = true;
|
||||
else
|
||||
adapter->rx_csum = false;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
be_get_ethtool_stats(struct net_device *netdev,
|
||||
struct ethtool_stats *stats, uint64_t *data)
|
||||
{
|
||||
struct be_adapter *adapter = netdev_priv(netdev);
|
||||
struct be_drvr_stats *drvr_stats = &adapter->stats.drvr_stats;
|
||||
struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
|
||||
struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
|
||||
struct be_port_rxf_stats *port_stats =
|
||||
&rxf_stats->port[adapter->port_num];
|
||||
struct net_device_stats *net_stats = &adapter->stats.net_stats;
|
||||
struct be_erx_stats *erx_stats = &hw_stats->erx;
|
||||
void *p = NULL;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ETHTOOL_STATS_NUM; i++) {
|
||||
switch (et_stats[i].type) {
|
||||
case NETSTAT:
|
||||
p = net_stats;
|
||||
break;
|
||||
case DRVSTAT:
|
||||
p = drvr_stats;
|
||||
break;
|
||||
case PORTSTAT:
|
||||
p = port_stats;
|
||||
break;
|
||||
case MISCSTAT:
|
||||
p = rxf_stats;
|
||||
break;
|
||||
case ERXSTAT: /* Currently only one ERX stat is provided */
|
||||
p = (u32 *)erx_stats + adapter->rx_obj.q.id;
|
||||
break;
|
||||
}
|
||||
|
||||
p = (u8 *)p + et_stats[i].offset;
|
||||
data[i] = (et_stats[i].size == sizeof(u64)) ?
|
||||
*(u64 *)p: *(u32 *)p;
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
static void
|
||||
be_get_stat_strings(struct net_device *netdev, uint32_t stringset,
|
||||
uint8_t *data)
|
||||
{
|
||||
int i;
|
||||
switch (stringset) {
|
||||
case ETH_SS_STATS:
|
||||
for (i = 0; i < ETHTOOL_STATS_NUM; i++) {
|
||||
memcpy(data, et_stats[i].desc, ETH_GSTRING_LEN);
|
||||
data += ETH_GSTRING_LEN;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int be_get_stats_count(struct net_device *netdev)
|
||||
{
|
||||
return ETHTOOL_STATS_NUM;
|
||||
}
|
||||
|
||||
static int be_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
|
||||
{
|
||||
ecmd->speed = SPEED_10000;
|
||||
ecmd->duplex = DUPLEX_FULL;
|
||||
ecmd->autoneg = AUTONEG_DISABLE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
be_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring)
|
||||
{
|
||||
struct be_adapter *adapter = netdev_priv(netdev);
|
||||
|
||||
ring->rx_max_pending = adapter->rx_obj.q.len;
|
||||
ring->tx_max_pending = adapter->tx_obj.q.len;
|
||||
|
||||
ring->rx_pending = atomic_read(&adapter->rx_obj.q.used);
|
||||
ring->tx_pending = atomic_read(&adapter->tx_obj.q.used);
|
||||
}
|
||||
|
||||
static void
|
||||
be_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *ecmd)
|
||||
{
|
||||
struct be_adapter *adapter = netdev_priv(netdev);
|
||||
|
||||
be_cmd_get_flow_control(&adapter->ctrl, &ecmd->tx_pause,
|
||||
&ecmd->rx_pause);
|
||||
ecmd->autoneg = AUTONEG_ENABLE;
|
||||
}
|
||||
|
||||
static int
|
||||
be_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *ecmd)
|
||||
{
|
||||
struct be_adapter *adapter = netdev_priv(netdev);
|
||||
int status;
|
||||
|
||||
if (ecmd->autoneg != AUTONEG_ENABLE)
|
||||
return -EINVAL;
|
||||
|
||||
status = be_cmd_set_flow_control(&adapter->ctrl, ecmd->tx_pause,
|
||||
ecmd->rx_pause);
|
||||
if (!status)
|
||||
dev_warn(&adapter->pdev->dev, "Pause param set failed.\n");
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
struct ethtool_ops be_ethtool_ops = {
|
||||
.get_settings = be_get_settings,
|
||||
.get_drvinfo = be_get_drvinfo,
|
||||
.get_link = ethtool_op_get_link,
|
||||
.get_coalesce = be_get_coalesce,
|
||||
.set_coalesce = be_set_coalesce,
|
||||
.get_ringparam = be_get_ringparam,
|
||||
.get_pauseparam = be_get_pauseparam,
|
||||
.set_pauseparam = be_set_pauseparam,
|
||||
.get_rx_csum = be_get_rx_csum,
|
||||
.set_rx_csum = be_set_rx_csum,
|
||||
.get_tx_csum = ethtool_op_get_tx_csum,
|
||||
.set_tx_csum = ethtool_op_set_tx_csum,
|
||||
.get_sg = ethtool_op_get_sg,
|
||||
.set_sg = ethtool_op_set_sg,
|
||||
.get_tso = ethtool_op_get_tso,
|
||||
.set_tso = ethtool_op_set_tso,
|
||||
.get_strings = be_get_stat_strings,
|
||||
.get_stats_count = be_get_stats_count,
|
||||
.get_ethtool_stats = be_get_ethtool_stats,
|
||||
};
|
||||
211
drivers/net/benet/be_hw.h
Normal file
211
drivers/net/benet/be_hw.h
Normal file
@ -0,0 +1,211 @@
|
||||
/*
|
||||
* Copyright (C) 2005 - 2009 ServerEngines
|
||||
* All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License version 2
|
||||
* as published by the Free Software Foundation. The full GNU General
|
||||
* Public License is included in this distribution in the file called COPYING.
|
||||
*
|
||||
* Contact Information:
|
||||
* linux-drivers@serverengines.com
|
||||
*
|
||||
* ServerEngines
|
||||
* 209 N. Fair Oaks Ave
|
||||
* Sunnyvale, CA 94085
|
||||
*/
|
||||
|
||||
/********* Mailbox door bell *************/
|
||||
/* Used for driver communication with the FW.
|
||||
* The software must write this register twice to post any command. First,
|
||||
* it writes the register with hi=1 and the upper bits of the physical address
|
||||
* for the MAILBOX structure. Software must poll the ready bit until this
|
||||
* is acknowledged. Then, sotware writes the register with hi=0 with the lower
|
||||
* bits in the address. It must poll the ready bit until the command is
|
||||
* complete. Upon completion, the MAILBOX will contain a valid completion
|
||||
* queue entry.
|
||||
*/
|
||||
#define MPU_MAILBOX_DB_OFFSET 0x160
|
||||
#define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
|
||||
#define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
|
||||
|
||||
#define MPU_EP_CONTROL 0
|
||||
|
||||
/********** MPU semphore ******************/
|
||||
#define MPU_EP_SEMAPHORE_OFFSET 0xac
|
||||
#define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF
|
||||
#define EP_SEMAPHORE_POST_ERR_MASK 0x1
|
||||
#define EP_SEMAPHORE_POST_ERR_SHIFT 31
|
||||
/* MPU semphore POST stage values */
|
||||
#define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
|
||||
#define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
|
||||
#define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
|
||||
#define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
|
||||
|
||||
/********* Memory BAR register ************/
|
||||
#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
|
||||
/* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
|
||||
* Disable" may still globally block interrupts in addition to individual
|
||||
* interrupt masks; a mechanism for the device driver to block all interrupts
|
||||
* atomically without having to arbitrate for the PCI Interrupt Disable bit
|
||||
* with the OS.
|
||||
*/
|
||||
#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
|
||||
/* PCI physical function number */
|
||||
#define MEMBAR_CTRL_INT_CTRL_PFUNC_MASK 0x7 /* bits 26 - 28 */
|
||||
#define MEMBAR_CTRL_INT_CTRL_PFUNC_SHIFT 26
|
||||
|
||||
/********* Event Q door bell *************/
|
||||
#define DB_EQ_OFFSET DB_CQ_OFFSET
|
||||
#define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
|
||||
/* Clear the interrupt for this eq */
|
||||
#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
|
||||
/* Must be 1 */
|
||||
#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
|
||||
/* Number of event entries processed */
|
||||
#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
|
||||
/* Rearm bit */
|
||||
#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
|
||||
|
||||
/********* Compl Q door bell *************/
|
||||
#define DB_CQ_OFFSET 0x120
|
||||
#define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
|
||||
/* Number of event entries processed */
|
||||
#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
|
||||
/* Rearm bit */
|
||||
#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
|
||||
|
||||
/********** TX ULP door bell *************/
|
||||
#define DB_TXULP1_OFFSET 0x60
|
||||
#define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
|
||||
/* Number of tx entries posted */
|
||||
#define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
|
||||
#define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
|
||||
|
||||
/********** RQ(erx) door bell ************/
|
||||
#define DB_RQ_OFFSET 0x100
|
||||
#define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
|
||||
/* Number of rx frags posted */
|
||||
#define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
|
||||
|
||||
/*
|
||||
* BE descriptors: host memory data structures whose formats
|
||||
* are hardwired in BE silicon.
|
||||
*/
|
||||
/* Event Queue Descriptor */
|
||||
#define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */
|
||||
#define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
|
||||
#define EQ_ENTRY_RES_ID_SHIFT 16
|
||||
struct be_eq_entry {
|
||||
u32 evt;
|
||||
};
|
||||
|
||||
/* TX Queue Descriptor */
|
||||
#define ETH_WRB_FRAG_LEN_MASK 0xFFFF
|
||||
struct be_eth_wrb {
|
||||
u32 frag_pa_hi; /* dword 0 */
|
||||
u32 frag_pa_lo; /* dword 1 */
|
||||
u32 rsvd0; /* dword 2 */
|
||||
u32 frag_len; /* dword 3: bits 0 - 15 */
|
||||
} __packed;
|
||||
|
||||
/* Pseudo amap definition for eth_hdr_wrb in which each bit of the
|
||||
* actual structure is defined as a byte : used to calculate
|
||||
* offset/shift/mask of each field */
|
||||
struct amap_eth_hdr_wrb {
|
||||
u8 rsvd0[32]; /* dword 0 */
|
||||
u8 rsvd1[32]; /* dword 1 */
|
||||
u8 complete; /* dword 2 */
|
||||
u8 event;
|
||||
u8 crc;
|
||||
u8 forward;
|
||||
u8 ipsec;
|
||||
u8 mgmt;
|
||||
u8 ipcs;
|
||||
u8 udpcs;
|
||||
u8 tcpcs;
|
||||
u8 lso;
|
||||
u8 vlan;
|
||||
u8 gso[2];
|
||||
u8 num_wrb[5];
|
||||
u8 lso_mss[14];
|
||||
u8 len[16]; /* dword 3 */
|
||||
u8 vlan_tag[16];
|
||||
} __packed;
|
||||
|
||||
struct be_eth_hdr_wrb {
|
||||
u32 dw[4];
|
||||
};
|
||||
|
||||
/* TX Compl Queue Descriptor */
|
||||
|
||||
/* Pseudo amap definition for eth_tx_compl in which each bit of the
|
||||
* actual structure is defined as a byte: used to calculate
|
||||
* offset/shift/mask of each field */
|
||||
struct amap_eth_tx_compl {
|
||||
u8 wrb_index[16]; /* dword 0 */
|
||||
u8 ct[2]; /* dword 0 */
|
||||
u8 port[2]; /* dword 0 */
|
||||
u8 rsvd0[8]; /* dword 0 */
|
||||
u8 status[4]; /* dword 0 */
|
||||
u8 user_bytes[16]; /* dword 1 */
|
||||
u8 nwh_bytes[8]; /* dword 1 */
|
||||
u8 lso; /* dword 1 */
|
||||
u8 cast_enc[2]; /* dword 1 */
|
||||
u8 rsvd1[5]; /* dword 1 */
|
||||
u8 rsvd2[32]; /* dword 2 */
|
||||
u8 pkts[16]; /* dword 3 */
|
||||
u8 ringid[11]; /* dword 3 */
|
||||
u8 hash_val[4]; /* dword 3 */
|
||||
u8 valid; /* dword 3 */
|
||||
} __packed;
|
||||
|
||||
struct be_eth_tx_compl {
|
||||
u32 dw[4];
|
||||
};
|
||||
|
||||
/* RX Queue Descriptor */
|
||||
struct be_eth_rx_d {
|
||||
u32 fragpa_hi;
|
||||
u32 fragpa_lo;
|
||||
};
|
||||
|
||||
/* RX Compl Queue Descriptor */
|
||||
|
||||
/* Pseudo amap definition for eth_rx_compl in which each bit of the
|
||||
* actual structure is defined as a byte: used to calculate
|
||||
* offset/shift/mask of each field */
|
||||
struct amap_eth_rx_compl {
|
||||
u8 vlan_tag[16]; /* dword 0 */
|
||||
u8 pktsize[14]; /* dword 0 */
|
||||
u8 port; /* dword 0 */
|
||||
u8 ip_opt; /* dword 0 */
|
||||
u8 err; /* dword 1 */
|
||||
u8 rsshp; /* dword 1 */
|
||||
u8 ipf; /* dword 1 */
|
||||
u8 tcpf; /* dword 1 */
|
||||
u8 udpf; /* dword 1 */
|
||||
u8 ipcksm; /* dword 1 */
|
||||
u8 l4_cksm; /* dword 1 */
|
||||
u8 ip_version; /* dword 1 */
|
||||
u8 macdst[6]; /* dword 1 */
|
||||
u8 vtp; /* dword 1 */
|
||||
u8 rsvd0; /* dword 1 */
|
||||
u8 fragndx[10]; /* dword 1 */
|
||||
u8 ct[2]; /* dword 1 */
|
||||
u8 sw; /* dword 1 */
|
||||
u8 numfrags[3]; /* dword 1 */
|
||||
u8 rss_flush; /* dword 2 */
|
||||
u8 cast_enc[2]; /* dword 2 */
|
||||
u8 qnq; /* dword 2 */
|
||||
u8 rss_bank; /* dword 2 */
|
||||
u8 rsvd1[23]; /* dword 2 */
|
||||
u8 lro_pkt; /* dword 2 */
|
||||
u8 rsvd2[2]; /* dword 2 */
|
||||
u8 valid; /* dword 2 */
|
||||
u8 rsshash[32]; /* dword 3 */
|
||||
} __packed;
|
||||
|
||||
struct be_eth_rx_compl {
|
||||
u32 dw[4];
|
||||
};
|
||||
1903
drivers/net/benet/be_main.c
Normal file
1903
drivers/net/benet/be_main.c
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user