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clk: imx: scu: Only save DC SS clock using non-cached clock rate

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Display sub-system has special clock settings in SCFW, the
bypassed clock is used instead of PLL in Linux kernel clock
tree, so when saving clock rate, need to save non-cached clock
rate for Display sub-system's bypass clocks, and other clocks
still use the cached clock rate which is with runtime PM ON.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
This commit is contained in:
Anson Huang 2021-06-04 17:09:41 +08:00 committed by Abel Vesa
parent a43f6e8ae4
commit 7487986c9a
1 changed files with 8 additions and 1 deletions
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9
drivers/clk/imx/clk-scu.c
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@ -547,7 +547,14 @@ static int __maybe_unused imx_clk_scu_suspend(struct device *dev)
(rsrc_id == IMX_SC_R_A72))
return 0;
clk->rate = clk_hw_get_rate(&clk->hw);
/* DC SS needs to handle bypass clock using non-cached clock rate */
if (clk->rsrc_id == IMX_SC_R_DC_0_VIDEO0 ||
clk->rsrc_id == IMX_SC_R_DC_0_VIDEO1 ||
clk->rsrc_id == IMX_SC_R_DC_1_VIDEO0 ||
clk->rsrc_id == IMX_SC_R_DC_1_VIDEO1)
clk->rate = clk_scu_recalc_rate(&clk->hw, 0);
else
clk->rate = clk_hw_get_rate(&clk->hw);
clk->is_enabled = clk_hw_is_enabled(&clk->hw);
if (clk->rate)