mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
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drm/radeon/kms: change evergreen_default_state table from global to static
evergreen_default_state and evergreen_default_size are only
used in evergreen.c. Single file symbols should be static.
So move their definitions to evergreen_blit_shaders.h
and change their storage-class-specifier to static.
Remove unneeded evergreen_blit_shader.c
evergreen_ps/vs definitions were removed with
commit 4f8629675800 ("drm/radeon/kms: remove r6xx+ blit copy routines")
So their declarations in evergreen_blit_shader.h
are not needed, so remove them.
Signed-off-by: Tom Rix <trix@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Tom Rix
Alex Deucher
parent
3eccf76c2d
commit
79847f13a0
@ -41,7 +41,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
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rs400.o rs600.o rs690.o rv515.o r520.o r600.o rv770.o radeon_test.o \
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r200.o radeon_legacy_tv.o r600_cs.o \
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radeon_pm.o atombios_dp.o r600_hdmi.o dce3_1_afmt.o \
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evergreen.o evergreen_cs.o evergreen_blit_shaders.o \
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evergreen.o evergreen_cs.o \
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evergreen_hdmi.o radeon_trace_points.o ni.o \
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atombios_encoders.o radeon_semaphore.o radeon_sa.o atombios_i2c.o si.o \
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radeon_prime.o cik.o cik_blit_shaders.o \
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@ -1,303 +0,0 @@
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/*
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* Copyright 2010 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Alex Deucher <alexander.deucher@amd.com>
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*/
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#include <linux/bug.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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/*
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* evergreen cards need to use the 3D engine to blit data which requires
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* quite a bit of hw state setup. Rather than pull the whole 3D driver
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* (which normally generates the 3D state) into the DRM, we opt to use
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* statically generated state tables. The register state and shaders
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* were hand generated to support blitting functionality. See the 3D
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* driver or documentation for descriptions of the registers and
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* shader instructions.
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*/
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const u32 evergreen_default_state[] =
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{
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0xc0016900,
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0x0000023b,
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0x00000000, /* SQ_LDS_ALLOC_PS */
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0xc0066900,
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0x00000240,
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0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0xc0046900,
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0x00000247,
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0x00000000, /* SQ_GS_VERT_ITEMSIZE */
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0x00000000,
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0x00000000,
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0x00000000,
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0xc0026900,
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0x00000010,
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0x00000000, /* DB_Z_INFO */
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0x00000000, /* DB_STENCIL_INFO */
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0xc0016900,
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0x00000200,
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0x00000000, /* DB_DEPTH_CONTROL */
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0xc0066900,
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0x00000000,
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0x00000060, /* DB_RENDER_CONTROL */
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0x00000000, /* DB_COUNT_CONTROL */
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0x00000000, /* DB_DEPTH_VIEW */
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0x0000002a, /* DB_RENDER_OVERRIDE */
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0x00000000, /* DB_RENDER_OVERRIDE2 */
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0x00000000, /* DB_HTILE_DATA_BASE */
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0xc0026900,
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0x0000000a,
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0x00000000, /* DB_STENCIL_CLEAR */
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0x00000000, /* DB_DEPTH_CLEAR */
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0xc0016900,
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0x000002dc,
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0x0000aa00, /* DB_ALPHA_TO_MASK */
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0xc0016900,
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0x00000080,
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0x00000000, /* PA_SC_WINDOW_OFFSET */
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0xc00d6900,
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0x00000083,
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0x0000ffff, /* PA_SC_CLIPRECT_RULE */
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0x00000000, /* PA_SC_CLIPRECT_0_TL */
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0x20002000, /* PA_SC_CLIPRECT_0_BR */
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0x00000000,
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0x20002000,
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0x00000000,
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0x20002000,
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0x00000000,
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0x20002000,
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0xaaaaaaaa, /* PA_SC_EDGERULE */
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0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
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0x0000000f, /* CB_TARGET_MASK */
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0x0000000f, /* CB_SHADER_MASK */
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0xc0226900,
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0x00000094,
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0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
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0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x00000000, /* PA_SC_VPORT_ZMIN_0 */
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0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
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0xc0016900,
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0x000000d4,
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0x00000000, /* SX_MISC */
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0xc0026900,
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0x00000292,
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0x00000000, /* PA_SC_MODE_CNTL_0 */
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0x00000000, /* PA_SC_MODE_CNTL_1 */
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0xc0106900,
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0x00000300,
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0x00000000, /* PA_SC_LINE_CNTL */
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0x00000000, /* PA_SC_AA_CONFIG */
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0x00000005, /* PA_SU_VTX_CNTL */
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0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
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0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
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0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
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0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
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0x00000000, /* PA_SC_AA_SAMPLE_LOCS_0 */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* PA_SC_AA_SAMPLE_LOCS_7 */
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0xffffffff, /* PA_SC_AA_MASK */
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0xc00d6900,
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0x00000202,
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0x00cc0010, /* CB_COLOR_CONTROL */
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0x00000210, /* DB_SHADER_CONTROL */
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0x00010000, /* PA_CL_CLIP_CNTL */
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0x00000004, /* PA_SU_SC_MODE_CNTL */
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0x00000100, /* PA_CL_VTE_CNTL */
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0x00000000, /* PA_CL_VS_OUT_CNTL */
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0x00000000, /* PA_CL_NANINF_CNTL */
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0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
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0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
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0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* SQ_DYN_GPR_RESOURCE_LIMIT_1 */
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0xc0066900,
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0x000002de,
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0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0xc0016900,
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0x00000229,
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0x00000000, /* SQ_PGM_START_FS */
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0xc0016900,
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0x0000022a,
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0x00000000, /* SQ_PGM_RESOURCES_FS */
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0xc0096900,
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0x00000100,
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0x00ffffff, /* VGT_MAX_VTX_INDX */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* SX_ALPHA_TEST_CONTROL */
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0x00000000, /* CB_BLEND_RED */
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0x00000000, /* CB_BLEND_GREEN */
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0x00000000, /* CB_BLEND_BLUE */
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0x00000000, /* CB_BLEND_ALPHA */
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0xc0026900,
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0x000002a8,
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0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
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0x00000000, /* */
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0xc0026900,
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0x000002ad,
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0x00000000, /* VGT_REUSE_OFF */
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0x00000000, /* */
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0xc0116900,
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0x00000280,
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0x00000000, /* PA_SU_POINT_SIZE */
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0x00000000, /* PA_SU_POINT_MINMAX */
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0x00000008, /* PA_SU_LINE_CNTL */
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0x00000000, /* PA_SC_LINE_STIPPLE */
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0x00000000, /* VGT_OUTPUT_PATH_CNTL */
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0x00000000, /* VGT_HOS_CNTL */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* VGT_GS_MODE */
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0xc0016900,
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0x000002a1,
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0x00000000, /* VGT_PRIMITIVEID_EN */
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0xc0016900,
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0x000002a5,
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0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
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0xc0016900,
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0x000002d5,
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0x00000000, /* VGT_SHADER_STAGES_EN */
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0xc0026900,
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0x000002e5,
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0x00000000, /* VGT_STRMOUT_CONFIG */
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0x00000000, /* */
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0xc0016900,
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0x000001e0,
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0x00000000, /* CB_BLEND0_CONTROL */
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0xc0016900,
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0x000001b1,
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0x00000000, /* SPI_VS_OUT_CONFIG */
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0xc0016900,
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0x00000187,
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0x00000000, /* SPI_VS_OUT_ID_0 */
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0xc0016900,
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0x00000191,
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0x00000100, /* SPI_PS_INPUT_CNTL_0 */
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0xc00b6900,
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0x000001b3,
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0x20000001, /* SPI_PS_IN_CONTROL_0 */
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0x00000000, /* SPI_PS_IN_CONTROL_1 */
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0x00000000, /* SPI_INTERP_CONTROL_0 */
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0x00000000, /* SPI_INPUT_Z */
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0x00000000, /* SPI_FOG_CNTL */
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0x00100000, /* SPI_BARYC_CNTL */
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0x00000000, /* SPI_PS_IN_CONTROL_2 */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0x00000000, /* */
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0xc0026900,
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0x00000316,
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0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
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0x00000010, /* */
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};
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const u32 evergreen_default_size = ARRAY_SIZE(evergreen_default_state);
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@ -20,16 +20,284 @@
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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||||
*
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* Authors:
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* Alex Deucher <alexander.deucher@amd.com>
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*/
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#ifndef EVERGREEN_BLIT_SHADERS_H
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#define EVERGREEN_BLIT_SHADERS_H
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extern const u32 evergreen_ps[];
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extern const u32 evergreen_vs[];
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extern const u32 evergreen_default_state[];
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/*
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* evergreen cards need to use the 3D engine to blit data which requires
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* quite a bit of hw state setup. Rather than pull the whole 3D driver
|
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* (which normally generates the 3D state) into the DRM, we opt to use
|
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* statically generated state tables. The register state and shaders
|
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* were hand generated to support blitting functionality. See the 3D
|
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* driver or documentation for descriptions of the registers and
|
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* shader instructions.
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*/
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extern const u32 evergreen_ps_size, evergreen_vs_size;
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extern const u32 evergreen_default_size;
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static const u32 evergreen_default_state[] = {
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0xc0016900,
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0x0000023b,
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0x00000000, /* SQ_LDS_ALLOC_PS */
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0xc0066900,
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0x00000240,
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0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0xc0046900,
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0x00000247,
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0x00000000, /* SQ_GS_VERT_ITEMSIZE */
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0x00000000,
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0x00000000,
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0x00000000,
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0xc0026900,
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0x00000010,
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0x00000000, /* DB_Z_INFO */
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0x00000000, /* DB_STENCIL_INFO */
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0xc0016900,
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0x00000200,
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0x00000000, /* DB_DEPTH_CONTROL */
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0xc0066900,
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0x00000000,
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0x00000060, /* DB_RENDER_CONTROL */
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0x00000000, /* DB_COUNT_CONTROL */
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0x00000000, /* DB_DEPTH_VIEW */
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0x0000002a, /* DB_RENDER_OVERRIDE */
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0x00000000, /* DB_RENDER_OVERRIDE2 */
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0x00000000, /* DB_HTILE_DATA_BASE */
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0xc0026900,
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0x0000000a,
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0x00000000, /* DB_STENCIL_CLEAR */
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0x00000000, /* DB_DEPTH_CLEAR */
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0xc0016900,
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0x000002dc,
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0x0000aa00, /* DB_ALPHA_TO_MASK */
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0xc0016900,
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0x00000080,
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0x00000000, /* PA_SC_WINDOW_OFFSET */
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0xc00d6900,
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0x00000083,
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0x0000ffff, /* PA_SC_CLIPRECT_RULE */
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0x00000000, /* PA_SC_CLIPRECT_0_TL */
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0x20002000, /* PA_SC_CLIPRECT_0_BR */
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0x00000000,
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0x20002000,
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0x00000000,
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0x20002000,
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0x00000000,
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0x20002000,
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0xaaaaaaaa, /* PA_SC_EDGERULE */
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0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
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0x0000000f, /* CB_TARGET_MASK */
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0x0000000f, /* CB_SHADER_MASK */
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0xc0226900,
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0x00000094,
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0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
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0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x80000000,
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0x20002000,
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0x00000000, /* PA_SC_VPORT_ZMIN_0 */
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0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
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0xc0016900,
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0x000000d4,
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0x00000000, /* SX_MISC */
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0xc0026900,
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0x00000292,
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0x00000000, /* PA_SC_MODE_CNTL_0 */
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0x00000000, /* PA_SC_MODE_CNTL_1 */
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0xc0106900,
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0x00000300,
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0x00000000, /* PA_SC_LINE_CNTL */
|
||||
0x00000000, /* PA_SC_AA_CONFIG */
|
||||
0x00000005, /* PA_SU_VTX_CNTL */
|
||||
0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
|
||||
0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
|
||||
0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
|
||||
0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
|
||||
0x00000000, /* PA_SC_AA_SAMPLE_LOCS_0 */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* PA_SC_AA_SAMPLE_LOCS_7 */
|
||||
0xffffffff, /* PA_SC_AA_MASK */
|
||||
|
||||
0xc00d6900,
|
||||
0x00000202,
|
||||
0x00cc0010, /* CB_COLOR_CONTROL */
|
||||
0x00000210, /* DB_SHADER_CONTROL */
|
||||
0x00010000, /* PA_CL_CLIP_CNTL */
|
||||
0x00000004, /* PA_SU_SC_MODE_CNTL */
|
||||
0x00000100, /* PA_CL_VTE_CNTL */
|
||||
0x00000000, /* PA_CL_VS_OUT_CNTL */
|
||||
0x00000000, /* PA_CL_NANINF_CNTL */
|
||||
0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
|
||||
0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
|
||||
0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* SQ_DYN_GPR_RESOURCE_LIMIT_1 */
|
||||
|
||||
0xc0066900,
|
||||
0x000002de,
|
||||
0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
|
||||
0xc0016900,
|
||||
0x00000229,
|
||||
0x00000000, /* SQ_PGM_START_FS */
|
||||
|
||||
0xc0016900,
|
||||
0x0000022a,
|
||||
0x00000000, /* SQ_PGM_RESOURCES_FS */
|
||||
|
||||
0xc0096900,
|
||||
0x00000100,
|
||||
0x00ffffff, /* VGT_MAX_VTX_INDX */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* SX_ALPHA_TEST_CONTROL */
|
||||
0x00000000, /* CB_BLEND_RED */
|
||||
0x00000000, /* CB_BLEND_GREEN */
|
||||
0x00000000, /* CB_BLEND_BLUE */
|
||||
0x00000000, /* CB_BLEND_ALPHA */
|
||||
|
||||
0xc0026900,
|
||||
0x000002a8,
|
||||
0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
|
||||
0x00000000, /* */
|
||||
|
||||
0xc0026900,
|
||||
0x000002ad,
|
||||
0x00000000, /* VGT_REUSE_OFF */
|
||||
0x00000000, /* */
|
||||
|
||||
0xc0116900,
|
||||
0x00000280,
|
||||
0x00000000, /* PA_SU_POINT_SIZE */
|
||||
0x00000000, /* PA_SU_POINT_MINMAX */
|
||||
0x00000008, /* PA_SU_LINE_CNTL */
|
||||
0x00000000, /* PA_SC_LINE_STIPPLE */
|
||||
0x00000000, /* VGT_OUTPUT_PATH_CNTL */
|
||||
0x00000000, /* VGT_HOS_CNTL */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* VGT_GS_MODE */
|
||||
|
||||
0xc0016900,
|
||||
0x000002a1,
|
||||
0x00000000, /* VGT_PRIMITIVEID_EN */
|
||||
|
||||
0xc0016900,
|
||||
0x000002a5,
|
||||
0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
|
||||
|
||||
0xc0016900,
|
||||
0x000002d5,
|
||||
0x00000000, /* VGT_SHADER_STAGES_EN */
|
||||
|
||||
0xc0026900,
|
||||
0x000002e5,
|
||||
0x00000000, /* VGT_STRMOUT_CONFIG */
|
||||
0x00000000, /* */
|
||||
|
||||
0xc0016900,
|
||||
0x000001e0,
|
||||
0x00000000, /* CB_BLEND0_CONTROL */
|
||||
|
||||
0xc0016900,
|
||||
0x000001b1,
|
||||
0x00000000, /* SPI_VS_OUT_CONFIG */
|
||||
|
||||
0xc0016900,
|
||||
0x00000187,
|
||||
0x00000000, /* SPI_VS_OUT_ID_0 */
|
||||
|
||||
0xc0016900,
|
||||
0x00000191,
|
||||
0x00000100, /* SPI_PS_INPUT_CNTL_0 */
|
||||
|
||||
0xc00b6900,
|
||||
0x000001b3,
|
||||
0x20000001, /* SPI_PS_IN_CONTROL_0 */
|
||||
0x00000000, /* SPI_PS_IN_CONTROL_1 */
|
||||
0x00000000, /* SPI_INTERP_CONTROL_0 */
|
||||
0x00000000, /* SPI_INPUT_Z */
|
||||
0x00000000, /* SPI_FOG_CNTL */
|
||||
0x00100000, /* SPI_BARYC_CNTL */
|
||||
0x00000000, /* SPI_PS_IN_CONTROL_2 */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
0x00000000, /* */
|
||||
|
||||
0xc0026900,
|
||||
0x00000316,
|
||||
0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
|
||||
0x00000010, /* */
|
||||
};
|
||||
|
||||
static const u32 evergreen_default_size = ARRAY_SIZE(evergreen_default_state);
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user