mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
synced 2025-01-11 00:08:50 +00:00
GMAC: add driver for Rockchip RK3288 SoCs integrated GMAC
This driver is based on stmmac driver. changes since v2: - use tab instead of space for macros - use HIWORD_UPDATE macro for GMAC_CLK_RX_DL_CFG and GMAC_CLK_TX_DL_CFG - remove drive-strength setting in the driver and set it in the pinctrl settings - use dev_err instead of pr_err - remove clock names's macros, just use the real name of the clock - use devm_clk_get() instead of clk_get() - remove clk_set_parent(bsp_priv->clk_mac, bsp_priv->clk_mac_pll) - remove gpio setting for LDO, just use regulator API - remove phy reset using gpio in the glue layer, it has been handled in the stmmac driver - remove handling phy interrupt (mii interrupt) changes since v1: - use BIT() to set register - combine two remap_write() operations into one for the same register - use macros for register value setting - remove grf fail check in rk_gmac_setup() and save all the check in set_rgmii_speed() - remove .tx_coe=1 in rk_gmac_data Signed-off-by: Roger Chen <roger.chen@rock-chips.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Roger Chen
David S. Miller
parent
9aacfb2023
commit
7ad269ea1a
@ -6,7 +6,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
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obj-$(CONFIG_STMMAC_PLATFORM) += stmmac-platform.o
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stmmac-platform-objs:= stmmac_platform.o dwmac-meson.o dwmac-sunxi.o \
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dwmac-sti.o dwmac-socfpga.o
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dwmac-sti.o dwmac-socfpga.o dwmac-rk.o
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obj-$(CONFIG_STMMAC_PCI) += stmmac-pci.o
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stmmac-pci-objs:= stmmac_pci.o
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459
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
Normal file
459
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
Normal file
@ -0,0 +1,459 @@
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/**
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* dwmac-rk.c - Rockchip RK3288 DWMAC specific glue layer
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*
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* Copyright (C) 2014 Chen-Zhi (Roger Chen)
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*
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* Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/stmmac.h>
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/phy.h>
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#include <linux/of_net.h>
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#include <linux/gpio.h>
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#include <linux/of_gpio.h>
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#include <linux/of_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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struct rk_priv_data {
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struct platform_device *pdev;
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int phy_iface;
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char regulator[32];
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bool clk_enabled;
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bool clock_input;
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struct clk *clk_mac;
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struct clk *clk_mac_pll;
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struct clk *gmac_clkin;
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struct clk *mac_clk_rx;
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struct clk *mac_clk_tx;
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struct clk *clk_mac_ref;
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struct clk *clk_mac_refout;
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struct clk *aclk_mac;
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struct clk *pclk_mac;
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int tx_delay;
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int rx_delay;
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struct regmap *grf;
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};
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#define HIWORD_UPDATE(val, mask, shift) \
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((val) << (shift) | (mask) << ((shift) + 16))
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#define GRF_BIT(nr) (BIT(nr) | BIT(nr+16))
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#define GRF_CLR_BIT(nr) (BIT(nr+16))
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#define RK3288_GRF_SOC_CON1 0x0248
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#define RK3288_GRF_SOC_CON3 0x0250
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#define RK3288_GRF_GPIO3D_E 0x01ec
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#define RK3288_GRF_GPIO4A_E 0x01f0
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#define RK3288_GRF_GPIO4B_E 0x01f4
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/*RK3288_GRF_SOC_CON1*/
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#define GMAC_PHY_INTF_SEL_RGMII (GRF_BIT(6) | GRF_CLR_BIT(7) | GRF_CLR_BIT(8))
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#define GMAC_PHY_INTF_SEL_RMII (GRF_CLR_BIT(6) | GRF_CLR_BIT(7) | GRF_BIT(8))
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#define GMAC_FLOW_CTRL GRF_BIT(9)
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#define GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(9)
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#define GMAC_SPEED_10M GRF_CLR_BIT(10)
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#define GMAC_SPEED_100M GRF_BIT(10)
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#define GMAC_RMII_CLK_25M GRF_BIT(11)
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#define GMAC_RMII_CLK_2_5M GRF_CLR_BIT(11)
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#define GMAC_CLK_125M (GRF_CLR_BIT(12) | GRF_CLR_BIT(13))
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#define GMAC_CLK_25M (GRF_BIT(12) | GRF_BIT(13))
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#define GMAC_CLK_2_5M (GRF_CLR_BIT(12) | GRF_BIT(13))
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#define GMAC_RMII_MODE GRF_BIT(14)
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#define GMAC_RMII_MODE_CLR GRF_CLR_BIT(14)
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/*RK3288_GRF_SOC_CON3*/
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#define GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
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#define GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
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#define GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
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#define GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
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#define GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 7)
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#define GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
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static void set_to_rgmii(struct rk_priv_data *bsp_priv,
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int tx_delay, int rx_delay)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
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return;
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}
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regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
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GMAC_PHY_INTF_SEL_RGMII | GMAC_RMII_MODE_CLR);
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regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
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GMAC_RXCLK_DLY_ENABLE | GMAC_TXCLK_DLY_ENABLE |
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GMAC_CLK_RX_DL_CFG(rx_delay) |
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GMAC_CLK_TX_DL_CFG(tx_delay));
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}
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static void set_to_rmii(struct rk_priv_data *bsp_priv)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
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return;
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}
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regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
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GMAC_PHY_INTF_SEL_RMII | GMAC_RMII_MODE);
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}
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static void set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
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return;
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}
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if (speed == 10)
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regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, GMAC_CLK_2_5M);
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else if (speed == 100)
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regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, GMAC_CLK_25M);
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else if (speed == 1000)
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regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1, GMAC_CLK_125M);
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else
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dev_err(dev, "unknown speed value for RGMII! speed=%d", speed);
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}
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static void set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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if (IS_ERR(bsp_priv->grf)) {
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dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
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return;
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}
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if (speed == 10) {
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regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
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GMAC_RMII_CLK_2_5M | GMAC_SPEED_10M);
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} else if (speed == 100) {
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regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON1,
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GMAC_RMII_CLK_25M | GMAC_SPEED_100M);
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} else {
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dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
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}
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}
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static int gmac_clk_init(struct rk_priv_data *bsp_priv)
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{
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struct device *dev = &bsp_priv->pdev->dev;
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bsp_priv->clk_enabled = false;
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bsp_priv->mac_clk_rx = devm_clk_get(dev, "mac_clk_rx");
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if (IS_ERR(bsp_priv->mac_clk_rx))
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dev_err(dev, "%s: cannot get clock %s\n",
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__func__, "mac_clk_rx");
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bsp_priv->mac_clk_tx = devm_clk_get(dev, "mac_clk_tx");
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if (IS_ERR(bsp_priv->mac_clk_tx))
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dev_err(dev, "%s: cannot get clock %s\n",
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__func__, "mac_clk_tx");
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bsp_priv->aclk_mac = devm_clk_get(dev, "aclk_mac");
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if (IS_ERR(bsp_priv->aclk_mac))
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dev_err(dev, "%s: cannot get clock %s\n",
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__func__, "aclk_mac");
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bsp_priv->pclk_mac = devm_clk_get(dev, "pclk_mac");
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if (IS_ERR(bsp_priv->pclk_mac))
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dev_err(dev, "%s: cannot get clock %s\n",
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__func__, "pclk_mac");
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bsp_priv->clk_mac = devm_clk_get(dev, "stmmaceth");
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if (IS_ERR(bsp_priv->clk_mac))
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dev_err(dev, "%s: cannot get clock %s\n",
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__func__, "stmmaceth");
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if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
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bsp_priv->clk_mac_ref = devm_clk_get(dev, "clk_mac_ref");
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if (IS_ERR(bsp_priv->clk_mac_ref))
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dev_err(dev, "%s: cannot get clock %s\n",
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__func__, "clk_mac_ref");
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if (!bsp_priv->clock_input) {
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bsp_priv->clk_mac_refout =
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devm_clk_get(dev, "clk_mac_refout");
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if (IS_ERR(bsp_priv->clk_mac_refout))
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dev_err(dev, "%s: cannot get clock %s\n",
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__func__, "clk_mac_refout");
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}
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}
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if (bsp_priv->clock_input) {
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dev_info(dev, "%s: clock input from PHY\n", __func__);
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} else {
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if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
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clk_set_rate(bsp_priv->clk_mac_pll, 50000000);
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}
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return 0;
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}
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static int gmac_clk_enable(struct rk_priv_data *bsp_priv, bool enable)
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{
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int phy_iface = phy_iface = bsp_priv->phy_iface;
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if (enable) {
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if (!bsp_priv->clk_enabled) {
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if (phy_iface == PHY_INTERFACE_MODE_RMII) {
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if (!IS_ERR(bsp_priv->mac_clk_rx))
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clk_prepare_enable(
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bsp_priv->mac_clk_rx);
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if (!IS_ERR(bsp_priv->clk_mac_ref))
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clk_prepare_enable(
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bsp_priv->clk_mac_ref);
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if (!IS_ERR(bsp_priv->clk_mac_refout))
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clk_prepare_enable(
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bsp_priv->clk_mac_refout);
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}
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if (!IS_ERR(bsp_priv->aclk_mac))
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clk_prepare_enable(bsp_priv->aclk_mac);
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if (!IS_ERR(bsp_priv->pclk_mac))
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clk_prepare_enable(bsp_priv->pclk_mac);
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if (!IS_ERR(bsp_priv->mac_clk_tx))
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clk_prepare_enable(bsp_priv->mac_clk_tx);
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/**
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* if (!IS_ERR(bsp_priv->clk_mac))
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* clk_prepare_enable(bsp_priv->clk_mac);
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*/
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mdelay(5);
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bsp_priv->clk_enabled = true;
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}
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} else {
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if (bsp_priv->clk_enabled) {
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if (phy_iface == PHY_INTERFACE_MODE_RMII) {
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if (!IS_ERR(bsp_priv->mac_clk_rx))
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clk_disable_unprepare(
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bsp_priv->mac_clk_rx);
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if (!IS_ERR(bsp_priv->clk_mac_ref))
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clk_disable_unprepare(
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bsp_priv->clk_mac_ref);
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if (!IS_ERR(bsp_priv->clk_mac_refout))
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clk_disable_unprepare(
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bsp_priv->clk_mac_refout);
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}
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if (!IS_ERR(bsp_priv->aclk_mac))
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clk_disable_unprepare(bsp_priv->aclk_mac);
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if (!IS_ERR(bsp_priv->pclk_mac))
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clk_disable_unprepare(bsp_priv->pclk_mac);
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if (!IS_ERR(bsp_priv->mac_clk_tx))
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clk_disable_unprepare(bsp_priv->mac_clk_tx);
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/**
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* if (!IS_ERR(bsp_priv->clk_mac))
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* clk_disable_unprepare(bsp_priv->clk_mac);
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*/
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bsp_priv->clk_enabled = false;
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}
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}
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return 0;
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}
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static int phy_power_on(struct rk_priv_data *bsp_priv, bool enable)
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{
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struct regulator *ldo;
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char *ldostr = bsp_priv->regulator;
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int ret;
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struct device *dev = &bsp_priv->pdev->dev;
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if (!ldostr) {
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dev_err(dev, "%s: no ldo found\n", __func__);
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return -1;
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}
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ldo = regulator_get(NULL, ldostr);
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if (!ldo) {
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dev_err(dev, "\n%s get ldo %s failed\n", __func__, ldostr);
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} else {
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if (enable) {
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if (!regulator_is_enabled(ldo)) {
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regulator_set_voltage(ldo, 3300000, 3300000);
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ret = regulator_enable(ldo);
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if (ret != 0)
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dev_err(dev, "%s: fail to enable %s\n",
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__func__, ldostr);
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else
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dev_info(dev, "turn on ldo done.\n");
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} else {
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dev_warn(dev, "%s is enabled before enable",
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ldostr);
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}
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} else {
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if (regulator_is_enabled(ldo)) {
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ret = regulator_disable(ldo);
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if (ret != 0)
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dev_err(dev, "%s: fail to disable %s\n",
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__func__, ldostr);
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else
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dev_info(dev, "turn off ldo done.\n");
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} else {
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dev_warn(dev, "%s is disabled before disable",
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ldostr);
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}
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}
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regulator_put(ldo);
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}
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return 0;
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}
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static void *rk_gmac_setup(struct platform_device *pdev)
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{
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struct rk_priv_data *bsp_priv;
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struct device *dev = &pdev->dev;
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int ret;
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const char *strings = NULL;
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int value;
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bsp_priv = devm_kzalloc(dev, sizeof(*bsp_priv), GFP_KERNEL);
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if (!bsp_priv)
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return ERR_PTR(-ENOMEM);
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bsp_priv->phy_iface = of_get_phy_mode(dev->of_node);
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ret = of_property_read_string(dev->of_node, "phy_regulator", &strings);
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if (ret) {
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dev_warn(dev, "%s: Can not read property: phy_regulator.\n",
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__func__);
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} else {
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dev_info(dev, "%s: PHY power controlled by regulator(%s).\n",
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__func__, strings);
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strcpy(bsp_priv->regulator, strings);
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}
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ret = of_property_read_string(dev->of_node, "clock_in_out", &strings);
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if (ret) {
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dev_err(dev, "%s: Can not read property: clock_in_out.\n",
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__func__);
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bsp_priv->clock_input = true;
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} else {
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dev_info(dev, "%s: clock input or output? (%s).\n",
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__func__, strings);
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if (!strcmp(strings, "input"))
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bsp_priv->clock_input = true;
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else
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bsp_priv->clock_input = false;
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}
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ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
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if (ret) {
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bsp_priv->tx_delay = 0x30;
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dev_err(dev, "%s: Can not read property: tx_delay.", __func__);
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dev_err(dev, "%s: set tx_delay to 0x%x\n",
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__func__, bsp_priv->tx_delay);
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} else {
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dev_info(dev, "%s: TX delay(0x%x).\n", __func__, value);
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bsp_priv->tx_delay = value;
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}
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ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
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if (ret) {
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bsp_priv->rx_delay = 0x10;
|
||||
dev_err(dev, "%s: Can not read property: rx_delay.", __func__);
|
||||
dev_err(dev, "%s: set rx_delay to 0x%x\n",
|
||||
__func__, bsp_priv->rx_delay);
|
||||
} else {
|
||||
dev_info(dev, "%s: RX delay(0x%x).\n", __func__, value);
|
||||
bsp_priv->rx_delay = value;
|
||||
}
|
||||
|
||||
bsp_priv->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
|
||||
"rockchip,grf");
|
||||
bsp_priv->pdev = pdev;
|
||||
|
||||
/*rmii or rgmii*/
|
||||
if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII) {
|
||||
dev_info(dev, "%s: init for RGMII\n", __func__);
|
||||
set_to_rgmii(bsp_priv, bsp_priv->tx_delay, bsp_priv->rx_delay);
|
||||
} else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII) {
|
||||
dev_info(dev, "%s: init for RMII\n", __func__);
|
||||
set_to_rmii(bsp_priv);
|
||||
} else {
|
||||
dev_err(dev, "%s: NO interface defined!\n", __func__);
|
||||
}
|
||||
|
||||
gmac_clk_init(bsp_priv);
|
||||
|
||||
return bsp_priv;
|
||||
}
|
||||
|
||||
static int rk_gmac_init(struct platform_device *pdev, void *priv)
|
||||
{
|
||||
struct rk_priv_data *bsp_priv = priv;
|
||||
int ret;
|
||||
|
||||
ret = phy_power_on(bsp_priv, true);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = gmac_clk_enable(bsp_priv, true);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void rk_gmac_exit(struct platform_device *pdev, void *priv)
|
||||
{
|
||||
struct rk_priv_data *gmac = priv;
|
||||
|
||||
phy_power_on(gmac, false);
|
||||
gmac_clk_enable(gmac, false);
|
||||
}
|
||||
|
||||
static void rk_fix_speed(void *priv, unsigned int speed)
|
||||
{
|
||||
struct rk_priv_data *bsp_priv = priv;
|
||||
struct device *dev = &bsp_priv->pdev->dev;
|
||||
|
||||
if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RGMII)
|
||||
set_rgmii_speed(bsp_priv, speed);
|
||||
else if (bsp_priv->phy_iface == PHY_INTERFACE_MODE_RMII)
|
||||
set_rmii_speed(bsp_priv, speed);
|
||||
else
|
||||
dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
|
||||
}
|
||||
|
||||
const struct stmmac_of_data rk3288_gmac_data = {
|
||||
.has_gmac = 1,
|
||||
.fix_mac_speed = rk_fix_speed,
|
||||
.setup = rk_gmac_setup,
|
||||
.init = rk_gmac_init,
|
||||
.exit = rk_gmac_exit,
|
||||
};
|
||||
@ -33,6 +33,7 @@
|
||||
|
||||
static const struct of_device_id stmmac_dt_ids[] = {
|
||||
/* SoC specific glue layers should come before generic bindings */
|
||||
{ .compatible = "rockchip,rk3288-gmac", .data = &rk3288_gmac_data},
|
||||
{ .compatible = "amlogic,meson6-dwmac", .data = &meson6_dwmac_data},
|
||||
{ .compatible = "allwinner,sun7i-a20-gmac", .data = &sun7i_gmac_data},
|
||||
{ .compatible = "st,stih415-dwmac", .data = &stih4xx_dwmac_data},
|
||||
|
||||
@ -24,5 +24,6 @@ extern const struct stmmac_of_data sun7i_gmac_data;
|
||||
extern const struct stmmac_of_data stih4xx_dwmac_data;
|
||||
extern const struct stmmac_of_data stid127_dwmac_data;
|
||||
extern const struct stmmac_of_data socfpga_gmac_data;
|
||||
extern const struct stmmac_of_data rk3288_gmac_data;
|
||||
|
||||
#endif /* __STMMAC_PLATFORM_H__ */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user