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bnx2x: Fan failure mechanism on additional design
The A1021G board is also using the fan failure mechanism in the same way the A1022G board does Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2550,6 +2550,7 @@ static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
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BNX2X_ERR("SPIO5 hw attention\n");
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switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
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case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
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case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
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/* Fan failure attention */
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@ -5337,6 +5338,7 @@ static int bnx2x_init_common(struct bnx2x *bp)
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}
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switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
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case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
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case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
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/* Fan failure is indicated by SPIO 5 */
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bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
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@ -5531,6 +5533,7 @@ static int bnx2x_init_port(struct bnx2x *bp)
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/* Port DMAE comes here */
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switch (bp->common.board & SHARED_HW_CFG_BOARD_TYPE_MASK) {
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case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1021G:
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case SHARED_HW_CFG_BOARD_TYPE_BCM957710A1022G:
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/* add SPIO 5 to group 0 */
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val = REG_RD(bp, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
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