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Merge branch 'next' of git://linuxtv.org/media-ci/media-pending.git

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This commit is contained in:
Stephen Rothwell 2024-12-20 11:07:40 +11:00
commit 7bb5219654
116 changed files with 4392 additions and 6141 deletions
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6
Documentation/admin-guide/media/ipu3.rst
View File

@ -98,7 +98,7 @@ frames in packed raw Bayer format to IPU3 CSI2 receiver.
# and that ov5670 sensor is connected to i2c bus 10 with address 0x36
export SDEV=$(media-ctl -d $MDEV -e "ov5670 10-0036")
# Establish the link for the media devices using media-ctl [#f3]_
# Establish the link for the media devices using media-ctl
media-ctl -d $MDEV -l "ov5670:0 -> ipu3-csi2 0:0[1]"
# Set the format for the media devices
@ -589,12 +589,8 @@ preserved.
References
==========
.. [#f5] drivers/staging/media/ipu3/include/uapi/intel-ipu3.h
.. [#f1] https://github.com/intel/nvt
.. [#f2] http://git.ideasonboard.org/yavta.git
.. [#f3] http://git.ideasonboard.org/?p=media-ctl.git;a=summary
.. [#f4] ImgU limitation requires an additional 16x16 for all input resolutions

2
Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml
View File

@ -33,6 +33,8 @@ properties:
- sony,imx290lqr # Colour
- sony,imx290llr # Monochrome
- sony,imx327lqr # Colour
- sony,imx462lqr # Colour
- sony,imx462llr # Monochrome
- const: sony,imx290
deprecated: true

425
Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml Normal file
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@ -0,0 +1,425 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/qcom,sc7280-camss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SC7280 CAMSS ISP
maintainers:
- Azam Sadiq Pasha Kapatrala Syed <akapatra@quicinc.com>
- Hariram Purushothaman <hariramp@quicinc.com>
description:
The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
properties:
compatible:
const: qcom,sc7280-camss
reg:
maxItems: 15
reg-names:
items:
- const: csid0
- const: csid1
- const: csid2
- const: csid_lite0
- const: csid_lite1
- const: csiphy0
- const: csiphy1
- const: csiphy2
- const: csiphy3
- const: csiphy4
- const: vfe0
- const: vfe1
- const: vfe2
- const: vfe_lite0
- const: vfe_lite1
clocks:
maxItems: 33
clock-names:
items:
- const: camnoc_axi
- const: cpas_ahb
- const: csiphy0
- const: csiphy0_timer
- const: csiphy1
- const: csiphy1_timer
- const: csiphy2
- const: csiphy2_timer
- const: csiphy3
- const: csiphy3_timer
- const: csiphy4
- const: csiphy4_timer
- const: gcc_camera_ahb
- const: gcc_cam_hf_axi
- const: icp_ahb
- const: vfe0
- const: vfe0_axi
- const: vfe0_cphy_rx
- const: vfe0_csid
- const: vfe1
- const: vfe1_axi
- const: vfe1_cphy_rx
- const: vfe1_csid
- const: vfe2
- const: vfe2_axi
- const: vfe2_cphy_rx
- const: vfe2_csid
- const: vfe_lite0
- const: vfe_lite0_cphy_rx
- const: vfe_lite0_csid
- const: vfe_lite1
- const: vfe_lite1_cphy_rx
- const: vfe_lite1_csid
interrupts:
maxItems: 15
interrupt-names:
items:
- const: csid0
- const: csid1
- const: csid2
- const: csid_lite0
- const: csid_lite1
- const: csiphy0
- const: csiphy1
- const: csiphy2
- const: csiphy3
- const: csiphy4
- const: vfe0
- const: vfe1
- const: vfe2
- const: vfe_lite0
- const: vfe_lite1
interconnects:
maxItems: 2
interconnect-names:
items:
- const: ahb
- const: hf_0
iommus:
maxItems: 1
power-domains:
items:
- description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
- description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
- description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
- description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
power-domain-names:
items:
- const: ife0
- const: ife1
- const: ife2
- const: top
vdda-phy-supply:
description:
Phandle to a regulator supply to PHY core block.
vdda-pll-supply:
description:
Phandle to 1.8V regulator supply to PHY refclk pll block.
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
CSI input ports.
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Input port for receiving CSI data on CSIPHY 0.
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
required:
- data-lanes
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Input port for receiving CSI data on CSIPHY 1.
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
required:
- data-lanes
port@2:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Input port for receiving CSI data on CSIPHY 2.
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
required:
- data-lanes
port@3:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Input port for receiving CSI data on CSIPHY 3.
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
required:
- data-lanes
port@4:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Input port for receiving CSI data on CSIPHY 4.
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
required:
- data-lanes
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- interrupts
- interrupt-names
- interconnects
- interconnect-names
- iommus
- power-domains
- power-domain-names
- vdda-phy-supply
- vdda-pll-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,camcc-sc7280.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
isp@acb3000 {
compatible = "qcom,sc7280-camss";
reg = <0x0 0x0acb3000 0x0 0x1000>,
<0x0 0x0acba000 0x0 0x1000>,
<0x0 0x0acc1000 0x0 0x1000>,
<0x0 0x0acc8000 0x0 0x1000>,
<0x0 0x0accf000 0x0 0x1000>,
<0x0 0x0ace0000 0x0 0x2000>,
<0x0 0x0ace2000 0x0 0x2000>,
<0x0 0x0ace4000 0x0 0x2000>,
<0x0 0x0ace6000 0x0 0x2000>,
<0x0 0x0ace8000 0x0 0x2000>,
<0x0 0x0acaf000 0x0 0x4000>,
<0x0 0x0acb6000 0x0 0x4000>,
<0x0 0x0acbd000 0x0 0x4000>,
<0x0 0x0acc4000 0x0 0x4000>,
<0x0 0x0accb000 0x0 0x4000>;
reg-names = "csid0",
"csid1",
"csid2",
"csid_lite0",
"csid_lite1",
"csiphy0",
"csiphy1",
"csiphy2",
"csiphy3",
"csiphy4",
"vfe0",
"vfe1",
"vfe2",
"vfe_lite0",
"vfe_lite1";
clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
<&camcc CAM_CC_CPAS_AHB_CLK>,
<&camcc CAM_CC_CSIPHY0_CLK>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY1_CLK>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY2_CLK>,
<&camcc CAM_CC_CSI2PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY3_CLK>,
<&camcc CAM_CC_CSI3PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY4_CLK>,
<&camcc CAM_CC_CSI4PHYTIMER_CLK>,
<&gcc GCC_CAMERA_AHB_CLK>,
<&gcc GCC_CAMERA_HF_AXI_CLK>,
<&camcc CAM_CC_ICP_AHB_CLK>,
<&camcc CAM_CC_IFE_0_CLK>,
<&camcc CAM_CC_IFE_0_AXI_CLK>,
<&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_0_CSID_CLK>,
<&camcc CAM_CC_IFE_1_CLK>,
<&camcc CAM_CC_IFE_1_AXI_CLK>,
<&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_1_CSID_CLK>,
<&camcc CAM_CC_IFE_2_CLK>,
<&camcc CAM_CC_IFE_2_AXI_CLK>,
<&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_2_CSID_CLK>,
<&camcc CAM_CC_IFE_LITE_0_CLK>,
<&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_LITE_0_CSID_CLK>,
<&camcc CAM_CC_IFE_LITE_1_CLK>,
<&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_LITE_1_CSID_CLK>;
clock-names = "camnoc_axi",
"cpas_ahb",
"csiphy0",
"csiphy0_timer",
"csiphy1",
"csiphy1_timer",
"csiphy2",
"csiphy2_timer",
"csiphy3",
"csiphy3_timer",
"csiphy4",
"csiphy4_timer",
"gcc_camera_ahb",
"gcc_cam_hf_axi",
"icp_ahb",
"vfe0",
"vfe0_axi",
"vfe0_cphy_rx",
"vfe0_csid",
"vfe1",
"vfe1_axi",
"vfe1_cphy_rx",
"vfe1_csid",
"vfe2",
"vfe2_axi",
"vfe2_cphy_rx",
"vfe2_csid",
"vfe_lite0",
"vfe_lite0_cphy_rx",
"vfe_lite0_csid",
"vfe_lite1",
"vfe_lite1_cphy_rx",
"vfe_lite1_csid";
interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csid0",
"csid1",
"csid2",
"csid_lite0",
"csid_lite1",
"csiphy0",
"csiphy1",
"csiphy2",
"csiphy3",
"csiphy4",
"vfe0",
"vfe1",
"vfe2",
"vfe_lite0",
"vfe_lite1";
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&cnoc2 SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "ahb",
"hf_0";
iommus = <&apps_smmu 0x800 0x4e0>;
power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
<&camcc CAM_CC_IFE_1_GDSC>,
<&camcc CAM_CC_IFE_2_GDSC>,
<&camcc CAM_CC_TITAN_TOP_GDSC>;
power-domain-names = "ife0",
"ife1",
"ife2",
"top";
vdda-phy-supply = <&vreg_l10c_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
};
};
};

40
Documentation/devicetree/bindings/media/qcom,sc8280xp-camss.yaml
View File

@ -328,26 +328,26 @@ examples:
vdda-phy-supply = <&vreg_l6d>;
vdda-pll-supply = <&vreg_l4d>;
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 640 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 641 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 758 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 759 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 760 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 761 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 762 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 764 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csid1_lite",
"vfe_lite1",

20
Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml
View File

@ -296,16 +296,16 @@ examples:
"vfe_lite_cphy_rx",
"vfe_lite_src";
interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csid0",
"csid1",

28
Documentation/devicetree/bindings/media/qcom,sm8250-camss.yaml
View File

@ -329,20 +329,20 @@ examples:
vdda-phy-supply = <&vreg_l5a_0p88>;
vdda-pll-supply = <&vreg_l9a_1p2>;
interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 86 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy0",
"csiphy1",
"csiphy2",

53
Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml
View File

@ -12,7 +12,9 @@ maintainers:
properties:
compatible:
const: st,stm32mp13-dcmipp
enum:
- st,stm32mp13-dcmipp
- st,stm32mp25-dcmipp
reg:
maxItems: 1
@ -21,11 +23,24 @@ properties:
maxItems: 1
clocks:
maxItems: 1
items:
- description: bus clock
- description: csi clock
minItems: 1
clock-names:
items:
- const: kclk
- const: mclk
minItems: 1
resets:
maxItems: 1
access-controllers:
minItems: 1
maxItems: 2
port:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
@ -39,7 +54,7 @@ properties:
properties:
bus-type:
enum: [5, 6]
enum: [4, 5, 6]
default: 5
bus-width:
@ -50,9 +65,6 @@ properties:
hsync-active: true
vsync-active: true
required:
- pclk-sample
required:
- compatible
- reg
@ -61,6 +73,35 @@ required:
- resets
- port
allOf:
- if:
properties:
compatible:
contains:
enum:
- st,stm32mp13-dcmipp
then:
properties:
clocks:
maxItems: 1
clock-names:
maxItems: 1
port:
properties:
endpoint:
properties:
bus-type:
enum: [5, 6]
else:
properties:
clocks:
minItems: 2
clock-names:
minItems: 2
additionalProperties: false
examples:

125
Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml Normal file
View File

@ -0,0 +1,125 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/st,stm32mp25-csi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32 CSI controller
description:
The STM32 CSI controller allows connecting a CSI based
camera to the DCMIPP camera pipeline.
maintainers:
- Alain Volmat <alain.volmat@foss.st.com>
properties:
compatible:
enum:
- st,stm32mp25-csi
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 3
clock-names:
items:
- const: pclk
- const: txesc
- const: csi2phy
resets:
maxItems: 1
vdd-supply:
description: Digital core power supply (0.91V)
vdda18-supply:
description: System analog power supply (1.8V)
access-controllers:
minItems: 1
maxItems: 2
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Input port node
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
items:
- const: 1
- const: 2
required:
- data-lanes
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
Output port node
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/media/video-interfaces.h>
#include <dt-bindings/reset/st,stm32mp25-rcc.h>
csi@48020000 {
compatible = "st,stm32mp25-csi";
reg = <0x48020000 0x2000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rcc CSI_R>;
clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, <&rcc CK_KER_CSIPHY>;
clock-names = "pclk", "txesc", "csi2phy";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&imx335_ep>;
data-lanes = <1 2>;
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
};
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&dcmipp_0>;
};
};
};
};
...

21
Documentation/devicetree/bindings/media/video-interfaces.yaml
View File

@ -210,6 +210,27 @@ properties:
lane-polarities property is omitted, the value must be interpreted as 0
(normal). This property is valid for serial busses only.
line-orders:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 1
maxItems: 8
items:
enum:
- 0 # ABC
- 1 # ACB
- 2 # BAC
- 3 # BCA
- 4 # CAB
- 5 # CBA
description:
An array of line orders of the CSI-2 C-PHY data lanes. The order of the
lanes are the same as in data-lanes property. Valid values are 0-5 as
defined in the MIPI Discovery and Configuration (DisCo) Specification for
Imaging. The length of the array must be the same length as the
data-lanes property. If the line-orders property is omitted, the value
shall be interpreted as 0 (ABC). This property is valid for CSI-2 C-PHY
busses only.
strobe:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 0, 1 ]

9
Documentation/driver-api/media/tx-rx.rst
View File

@ -50,7 +50,7 @@ The :ref:`V4L2_CID_LINK_FREQ <v4l2-cid-link-freq>` control is used to tell the
receiver the frequency of the bus (i.e. it is not the same as the symbol rate).
``.enable_streams()`` and ``.disable_streams()`` callbacks
^^^^^^^^^^^^^^^^^^^^^^^^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The struct v4l2_subdev_pad_ops->enable_streams() and struct
v4l2_subdev_pad_ops->disable_streams() callbacks are used by the receiver driver
@ -79,14 +79,15 @@ where
* - link_freq
- The value of the ``V4L2_CID_LINK_FREQ`` integer64 menu item.
* - nr_of_lanes
- Number of data lanes used on the CSI-2 link. This can
be obtained from the OF endpoint configuration.
- Number of data lanes used on the CSI-2 link.
* - 2
- Data is transferred on both rising and falling edge of the signal.
* - bits_per_sample
- Number of bits per sample.
* - k
- 16 for D-PHY and 7 for C-PHY
- 16 for D-PHY and 7 for C-PHY.
Information on whether D-PHY or C-PHY is used, and the value of ``nr_of_lanes``, can be obtained from the OF endpoint configuration.
.. note::

25
MAINTAINERS
View File

@ -816,7 +816,7 @@ F: drivers/media/platform/sunxi/sun4i-csi/
ALLWINNER A31 CSI DRIVER
M: Yong Deng <yong.deng@magewell.com>
M: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
M: Paul Kocialkowski <paulk@sys-base.io>
L: linux-media@vger.kernel.org
S: Maintained
T: git git://linuxtv.org/media.git
@ -824,7 +824,7 @@ F: Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml
F: drivers/media/platform/sunxi/sun6i-csi/
ALLWINNER A31 ISP DRIVER
M: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
M: Paul Kocialkowski <paulk@sys-base.io>
L: linux-media@vger.kernel.org
S: Maintained
T: git git://linuxtv.org/media.git
@ -833,7 +833,7 @@ F: drivers/staging/media/sunxi/sun6i-isp/
F: drivers/staging/media/sunxi/sun6i-isp/uapi/sun6i-isp-config.h
ALLWINNER A31 MIPI CSI-2 BRIDGE DRIVER
M: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
M: Paul Kocialkowski <paulk@sys-base.io>
L: linux-media@vger.kernel.org
S: Maintained
T: git git://linuxtv.org/media.git
@ -876,7 +876,7 @@ F: drivers/thermal/sun8i_thermal.c
ALLWINNER VPU DRIVER
M: Maxime Ripard <mripard@kernel.org>
M: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
M: Paul Kocialkowski <paulk@sys-base.io>
L: linux-media@vger.kernel.org
S: Maintained
F: drivers/staging/media/sunxi/cedrus/
@ -7249,7 +7249,7 @@ F: Documentation/devicetree/bindings/display/panel/lg,sw43408.yaml
F: drivers/gpu/drm/panel/panel-lg-sw43408.c
DRM DRIVER FOR LOGICVC DISPLAY CONTROLLER
M: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
M: Paul Kocialkowski <paulk@sys-base.io>
S: Supported
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
F: drivers/gpu/drm/logicvc/
@ -10048,7 +10048,8 @@ F: include/trace/events/handshake.h
F: net/handshake/
HANTRO VPU CODEC DRIVER
M: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
M: Nicolas Dufresne <nicolas.dufresne@collabora.com>
M: Benjamin Gaignard <benjamin.gaignard@collabora.com>
M: Philipp Zabel <p.zabel@pengutronix.de>
L: linux-media@vger.kernel.org
L: linux-rockchip@lists.infradead.org
@ -14520,6 +14521,14 @@ W: https://linuxtv.org
T: git git://linuxtv.org/media.git
F: drivers/media/dvb-frontends/stv6111*
MEDIA DRIVERS FOR STM32 - CSI
M: Alain Volmat <alain.volmat@foss.st.com>
L: linux-media@vger.kernel.org
S: Supported
T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/st,stm32mp25-csi.yaml
F: drivers/media/platform/stm32/stm32-csi.c
MEDIA DRIVERS FOR STM32 - DCMI / DCMIPP
M: Hugues Fruchet <hugues.fruchet@foss.st.com>
M: Alain Volmat <alain.volmat@foss.st.com>
@ -24480,7 +24489,11 @@ L: linux-media@vger.kernel.org
S: Maintained
W: http://www.ideasonboard.org/uvc/
T: git git://linuxtv.org/media.git
F: Documentation/userspace-api/media/drivers/uvcvideo.rst
F: Documentation/userspace-api/media/v4l/metafmt-uvc.rst
F: drivers/media/common/uvc.c
F: drivers/media/usb/uvc/
F: include/linux/usb/uvc.h
F: include/uapi/linux/uvcvideo.h
USB WEBCAM GADGET

4
drivers/media/common/b2c2/flexcop-common.h
View File

@ -125,8 +125,6 @@ void flexcop_dma_free(struct flexcop_dma *dma);
int flexcop_dma_control_timer_irq(struct flexcop_device *fc,
flexcop_dma_index_t no, int onoff);
int flexcop_dma_control_size_irq(struct flexcop_device *fc,
flexcop_dma_index_t no, int onoff);
int flexcop_dma_config(struct flexcop_device *fc, struct flexcop_dma *dma,
flexcop_dma_index_t dma_idx);
int flexcop_dma_xfer_control(struct flexcop_device *fc,
@ -170,8 +168,6 @@ int flexcop_sram_init(struct flexcop_device *fc);
void flexcop_determine_revision(struct flexcop_device *fc);
void flexcop_device_name(struct flexcop_device *fc,
const char *prefix, const char *suffix);
void flexcop_dump_reg(struct flexcop_device *fc,
flexcop_ibi_register reg, int num);
/* from flexcop-hw-filter.c */
int flexcop_pid_feed_control(struct flexcop_device *fc,

13
drivers/media/common/b2c2/flexcop-misc.c
View File

@ -70,16 +70,3 @@ void flexcop_device_name(struct flexcop_device *fc,
flexcop_bus_names[fc->bus_type],
flexcop_revision_names[fc->rev], suffix);
}
void flexcop_dump_reg(struct flexcop_device *fc,
flexcop_ibi_register reg, int num)
{
flexcop_ibi_value v;
int i;
for (i = 0; i < num; i++) {
v = fc->read_ibi_reg(fc, reg+4*i);
deb_rdump("0x%03x: %08x, ", reg+4*i, v.raw);
}
deb_rdump("\n");
}
EXPORT_SYMBOL(flexcop_dump_reg);

8
drivers/media/dvb-frontends/cxd2841er.c
View File

@ -311,12 +311,8 @@ static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
static u32 cxd2841er_calc_iffreq_xtal(enum cxd2841er_xtal xtal, u32 ifhz)
{
u64 tmp;
tmp = (u64) ifhz * 16777216;
do_div(tmp, ((xtal == SONY_XTAL_24000) ? 48000000 : 41000000));
return (u32) tmp;
return div_u64(ifhz * 16777216ull,
(xtal == SONY_XTAL_24000) ? 48000000 : 41000000);
}
static u32 cxd2841er_calc_iffreq(u32 ifhz)

18
drivers/media/i2c/ccs/ccs-core.c
View File

@ -3335,9 +3335,11 @@ static int ccs_probe(struct i2c_client *client)
rval = request_firmware(&fw, filename, &client->dev);
if (!rval) {
ccs_data_parse(&sensor->sdata, fw->data, fw->size, &client->dev,
true);
rval = ccs_data_parse(&sensor->sdata, fw->data, fw->size,
&client->dev, true);
release_firmware(fw);
if (rval)
goto out_power_off;
}
if (!(ccsdev->flags & CCS_DEVICE_FLAG_IS_SMIA) ||
@ -3351,9 +3353,11 @@ static int ccs_probe(struct i2c_client *client)
rval = request_firmware(&fw, filename, &client->dev);
if (!rval) {
ccs_data_parse(&sensor->mdata, fw->data, fw->size,
&client->dev, true);
rval = ccs_data_parse(&sensor->mdata, fw->data,
fw->size, &client->dev, true);
release_firmware(fw);
if (rval)
goto out_release_sdata;
}
}
@ -3566,15 +3570,15 @@ static int ccs_probe(struct i2c_client *client)
out_cleanup:
ccs_cleanup(sensor);
out_free_ccs_limits:
kfree(sensor->ccs_limits);
out_release_mdata:
kvfree(sensor->mdata.backing);
out_release_sdata:
kvfree(sensor->sdata.backing);
out_free_ccs_limits:
kfree(sensor->ccs_limits);
out_power_off:
ccs_power_off(&client->dev);
mutex_destroy(&sensor->mutex);

15
drivers/media/i2c/ccs/ccs-data.c
View File

@ -10,6 +10,7 @@
#include <linux/limits.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/string.h>
#include "ccs-data-defs.h"
@ -97,7 +98,7 @@ ccs_data_parse_length_specifier(const struct __ccs_data_length_specifier *__len,
plen = ((size_t)
(__len3->length[0] &
((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1))
<< 16) + (__len3->length[0] << 8) + __len3->length[1];
<< 16) + (__len3->length[1] << 8) + __len3->length[2];
break;
}
default:
@ -948,15 +949,15 @@ int ccs_data_parse(struct ccs_data_container *ccsdata, const void *data,
rval = __ccs_data_parse(&bin, ccsdata, data, len, dev, verbose);
if (rval)
return rval;
goto out_cleanup;
rval = bin_backing_alloc(&bin);
if (rval)
return rval;
goto out_cleanup;
rval = __ccs_data_parse(&bin, ccsdata, data, len, dev, false);
if (rval)
goto out_free;
goto out_cleanup;
if (verbose && ccsdata->version)
print_ccs_data_version(dev, ccsdata->version);
@ -965,15 +966,17 @@ int ccs_data_parse(struct ccs_data_container *ccsdata, const void *data,
rval = -EPROTO;
dev_dbg(dev, "parsing mismatch; base %p; now %p; end %p\n",
bin.base, bin.now, bin.end);
goto out_free;
goto out_cleanup;
}
ccsdata->backing = bin.base;
return 0;
out_free:
out_cleanup:
kvfree(bin.base);
memset(ccsdata, 0, sizeof(*ccsdata));
dev_warn(dev, "failed to parse CCS static data: %d\n", rval);
return rval;
}

26
drivers/media/i2c/ds90ub913.c
View File

@ -8,6 +8,7 @@
* Copyright (c) 2023 Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
*/
#include <linux/bitfield.h>
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/delay.h>
@ -146,6 +147,19 @@ static int ub913_write(const struct ub913_data *priv, u8 reg, u8 val)
return ret;
}
static int ub913_update_bits(const struct ub913_data *priv, u8 reg, u8 mask,
u8 val)
{
int ret;
ret = regmap_update_bits(priv->regmap, reg, mask, val);
if (ret < 0)
dev_err(&priv->client->dev,
"Cannot update register 0x%02x %d!\n", reg, ret);
return ret;
}
/*
* GPIO chip
*/
@ -733,10 +747,13 @@ static int ub913_hw_init(struct ub913_data *priv)
if (ret)
return dev_err_probe(dev, ret, "i2c master init failed\n");
ub913_read(priv, UB913_REG_GENERAL_CFG, &v);
v &= ~UB913_REG_GENERAL_CFG_PCLK_RISING;
v |= priv->pclk_polarity_rising ? UB913_REG_GENERAL_CFG_PCLK_RISING : 0;
ub913_write(priv, UB913_REG_GENERAL_CFG, v);
ret = ub913_update_bits(priv, UB913_REG_GENERAL_CFG,
UB913_REG_GENERAL_CFG_PCLK_RISING,
FIELD_PREP(UB913_REG_GENERAL_CFG_PCLK_RISING,
priv->pclk_polarity_rising));
if (ret)
return ret;
return 0;
}
@ -793,7 +810,6 @@ static void ub913_subdev_uninit(struct ub913_data *priv)
v4l2_async_unregister_subdev(&priv->sd);
ub913_v4l2_nf_unregister(priv);
v4l2_subdev_cleanup(&priv->sd);
fwnode_handle_put(priv->sd.fwnode);
media_entity_cleanup(&priv->sd.entity);
}

56
drivers/media/i2c/ds90ub953.c
View File

@ -65,6 +65,9 @@
#define UB953_REG_GPIO_INPUT_CTRL_OUT_EN(n) BIT(4 + (n))
#define UB953_REG_GPIO_INPUT_CTRL_INPUT_EN(n) BIT(0 + (n))
#define UB953_REG_BC_CTRL 0x49
#define UB953_REG_BC_CTRL_CRC_ERR_CLR BIT(3)
#define UB953_REG_REV_MASK_ID 0x50
#define UB953_REG_GENERAL_STATUS 0x52
@ -397,8 +400,13 @@ static int ub953_gpiochip_probe(struct ub953_data *priv)
int ret;
/* Set all GPIOs to local input mode */
ub953_write(priv, UB953_REG_LOCAL_GPIO_DATA, 0);
ub953_write(priv, UB953_REG_GPIO_INPUT_CTRL, 0xf);
ret = ub953_write(priv, UB953_REG_LOCAL_GPIO_DATA, 0);
if (ret)
return ret;
ret = ub953_write(priv, UB953_REG_GPIO_INPUT_CTRL, 0xf);
if (ret)
return ret;
gc->label = dev_name(dev);
gc->parent = dev;
@ -618,6 +626,12 @@ static int ub953_log_status(struct v4l2_subdev *sd)
ub953_read(priv, UB953_REG_CRC_ERR_CNT2, &v2);
dev_info(dev, "CRC error count %u\n", v1 | (v2 << 8));
/* Clear CRC error counter */
if (v1 || v2)
regmap_update_bits(priv->regmap, UB953_REG_BC_CTRL,
UB953_REG_BC_CTRL_CRC_ERR_CLR,
UB953_REG_BC_CTRL_CRC_ERR_CLR);
ub953_read(priv, UB953_REG_CSI_ERR_CNT, &v);
dev_info(dev, "CSI error count %u\n", v);
@ -958,10 +972,11 @@ static void ub953_calc_clkout_params(struct ub953_data *priv,
clkout_data->rate = clkout_rate;
}
static void ub953_write_clkout_regs(struct ub953_data *priv,
const struct ub953_clkout_data *clkout_data)
static int ub953_write_clkout_regs(struct ub953_data *priv,
const struct ub953_clkout_data *clkout_data)
{
u8 clkout_ctrl0, clkout_ctrl1;
int ret;
if (priv->hw_data->is_ub971)
clkout_ctrl0 = clkout_data->m;
@ -971,8 +986,15 @@ static void ub953_write_clkout_regs(struct ub953_data *priv,
clkout_ctrl1 = clkout_data->n;
ub953_write(priv, UB953_REG_CLKOUT_CTRL0, clkout_ctrl0);
ub953_write(priv, UB953_REG_CLKOUT_CTRL1, clkout_ctrl1);
ret = ub953_write(priv, UB953_REG_CLKOUT_CTRL0, clkout_ctrl0);
if (ret)
return ret;
ret = ub953_write(priv, UB953_REG_CLKOUT_CTRL1, clkout_ctrl1);
if (ret)
return ret;
return 0;
}
static unsigned long ub953_clkout_recalc_rate(struct clk_hw *hw,
@ -1052,9 +1074,7 @@ static int ub953_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
dev_dbg(&priv->client->dev, "%s %lu (requested %lu)\n", __func__,
clkout_data.rate, rate);
ub953_write_clkout_regs(priv, &clkout_data);
return 0;
return ub953_write_clkout_regs(priv, &clkout_data);
}
static const struct clk_ops ub953_clkout_ops = {
@ -1079,7 +1099,9 @@ static int ub953_register_clkout(struct ub953_data *priv)
/* Initialize clkout to 25MHz by default */
ub953_calc_clkout_params(priv, UB953_DEFAULT_CLKOUT_RATE, &clkout_data);
ub953_write_clkout_regs(priv, &clkout_data);
ret = ub953_write_clkout_regs(priv, &clkout_data);
if (ret)
return ret;
priv->clkout_clk_hw.init = &init;
@ -1226,10 +1248,15 @@ static int ub953_hw_init(struct ub953_data *priv)
if (ret)
return dev_err_probe(dev, ret, "i2c init failed\n");
ub953_write(priv, UB953_REG_GENERAL_CFG,
(priv->non_continous_clk ? 0 : UB953_REG_GENERAL_CFG_CONT_CLK) |
((priv->num_data_lanes - 1) << UB953_REG_GENERAL_CFG_CSI_LANE_SEL_SHIFT) |
UB953_REG_GENERAL_CFG_CRC_TX_GEN_ENABLE);
v = 0;
v |= priv->non_continous_clk ? 0 : UB953_REG_GENERAL_CFG_CONT_CLK;
v |= (priv->num_data_lanes - 1) <<
UB953_REG_GENERAL_CFG_CSI_LANE_SEL_SHIFT;
v |= UB953_REG_GENERAL_CFG_CRC_TX_GEN_ENABLE;
ret = ub953_write(priv, UB953_REG_GENERAL_CFG, v);
if (ret)
return ret;
return 0;
}
@ -1288,7 +1315,6 @@ static void ub953_subdev_uninit(struct ub953_data *priv)
v4l2_async_unregister_subdev(&priv->sd);
ub953_v4l2_notifier_unregister(priv);
v4l2_subdev_cleanup(&priv->sd);
fwnode_handle_put(priv->sd.fwnode);
media_entity_cleanup(&priv->sd.entity);
}

188
drivers/media/i2c/ds90ub960.c
View File

@ -43,6 +43,7 @@
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
#include <linux/units.h>
#include <linux/workqueue.h>
#include <media/i2c/ds90ub9xx.h>
@ -51,7 +52,16 @@
#include <media/v4l2-fwnode.h>
#include <media/v4l2-subdev.h>
#define MHZ(v) ((u32)((v) * 1000000U))
#define MHZ(v) ((u32)((v) * HZ_PER_MHZ))
/*
* If this is defined, the i2c addresses from UB960_DEBUG_I2C_RX_ID to
* UB960_DEBUG_I2C_RX_ID + 3 can be used to access the paged RX port registers
* directly.
*
* Only for debug purposes.
*/
/* #define UB960_DEBUG_I2C_RX_ID 0x40 */
#define UB960_POLL_TIME_MS 500
@ -349,12 +359,13 @@
#define UB960_SR_FPD3_RX_ID(n) (0xf0 + (n))
#define UB960_SR_FPD3_RX_ID_LEN 6
#define UB960_SR_I2C_RX_ID(n) (0xf8 + (n)) /* < UB960_FPD_RX_NPORTS */
#define UB960_SR_I2C_RX_ID(n) (0xf8 + (n))
#define UB9702_SR_REFCLK_FREQ 0x3d
/* Indirect register blocks */
#define UB960_IND_TARGET_PAT_GEN 0x00
#define UB960_IND_TARGET_RX_ANA(n) (0x01 + (n))
#define UB960_IND_TARGET_CSI_CSIPLL_REG_1 0x92 /* UB9702 */
#define UB960_IND_TARGET_CSI_ANA 0x07
/* UB960_IR_PGEN_*: Indirect Registers for Test Pattern Generator */
@ -568,11 +579,23 @@ struct ub960_format_info {
};
static const struct ub960_format_info ub960_formats[] = {
{ .code = MEDIA_BUS_FMT_RGB888_1X24, .bpp = 24, .datatype = MIPI_CSI2_DT_RGB888, },
{ .code = MEDIA_BUS_FMT_YUYV8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, },
{ .code = MEDIA_BUS_FMT_UYVY8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, },
{ .code = MEDIA_BUS_FMT_VYUY8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, },
{ .code = MEDIA_BUS_FMT_YVYU8_1X16, .bpp = 16, .datatype = MIPI_CSI2_DT_YUV422_8B, },
{ .code = MEDIA_BUS_FMT_SBGGR8_1X8, .bpp = 8, .datatype = MIPI_CSI2_DT_RAW8, },
{ .code = MEDIA_BUS_FMT_SGBRG8_1X8, .bpp = 8, .datatype = MIPI_CSI2_DT_RAW8, },
{ .code = MEDIA_BUS_FMT_SGRBG8_1X8, .bpp = 8, .datatype = MIPI_CSI2_DT_RAW8, },
{ .code = MEDIA_BUS_FMT_SRGGB8_1X8, .bpp = 8, .datatype = MIPI_CSI2_DT_RAW8, },
{ .code = MEDIA_BUS_FMT_SBGGR10_1X10, .bpp = 10, .datatype = MIPI_CSI2_DT_RAW10, },
{ .code = MEDIA_BUS_FMT_SGBRG10_1X10, .bpp = 10, .datatype = MIPI_CSI2_DT_RAW10, },
{ .code = MEDIA_BUS_FMT_SGRBG10_1X10, .bpp = 10, .datatype = MIPI_CSI2_DT_RAW10, },
{ .code = MEDIA_BUS_FMT_SRGGB10_1X10, .bpp = 10, .datatype = MIPI_CSI2_DT_RAW10, },
{ .code = MEDIA_BUS_FMT_SBGGR12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, },
{ .code = MEDIA_BUS_FMT_SGBRG12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, },
{ .code = MEDIA_BUS_FMT_SGRBG12_1X12, .bpp = 12, .datatype = MIPI_CSI2_DT_RAW12, },
@ -1552,7 +1575,12 @@ static int ub960_rxport_wait_locks(struct ub960_data *priv,
if (missing == 0)
break;
msleep(50);
/*
* The sleep time of 10 ms was found by testing to give a lock
* with a few iterations. It can be decreased if on some setups
* the lock can be achieved much faster.
*/
fsleep(10 * USEC_PER_MSEC);
}
if (lock_mask)
@ -1574,16 +1602,24 @@ static int ub960_rxport_wait_locks(struct ub960_data *priv,
ub960_rxport_read16(priv, nport, UB960_RR_RX_FREQ_HIGH, &v);
ret = ub960_rxport_get_strobe_pos(priv, nport, &strobe_pos);
if (ret)
return ret;
if (priv->hw_data->is_ub9702) {
dev_dbg(dev, "\trx%u: locked, freq %llu Hz\n",
nport, ((u64)v * HZ_PER_MHZ) >> 8);
} else {
ret = ub960_rxport_get_strobe_pos(priv, nport,
&strobe_pos);
if (ret)
return ret;
ret = ub960_rxport_get_eq_level(priv, nport, &eq_level);
if (ret)
return ret;
ret = ub960_rxport_get_eq_level(priv, nport, &eq_level);
if (ret)
return ret;
dev_dbg(dev, "\trx%u: locked, SP: %d, EQ: %u, freq %llu Hz\n",
nport, strobe_pos, eq_level, (v * 1000000ULL) >> 8);
dev_dbg(dev,
"\trx%u: locked, SP: %d, EQ: %u, freq %llu Hz\n",
nport, strobe_pos, eq_level,
((u64)v * HZ_PER_MHZ) >> 8);
}
}
return 0;
@ -2412,7 +2448,6 @@ static int ub960_configure_ports_for_streaming(struct ub960_data *priv,
} rx_data[UB960_MAX_RX_NPORTS] = {};
u8 vc_map[UB960_MAX_RX_NPORTS] = {};
struct v4l2_subdev_route *route;
unsigned int nport;
int ret;
ret = ub960_validate_stream_vcs(priv);
@ -2482,7 +2517,8 @@ static int ub960_configure_ports_for_streaming(struct ub960_data *priv,
*/
fwd_ctl = GENMASK(7, 4);
for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
for (unsigned int nport = 0; nport < priv->hw_data->num_rxports;
nport++) {
struct ub960_rxport *rxport = priv->rxports[nport];
u8 vc = vc_map[nport];
@ -2522,7 +2558,7 @@ static int ub960_configure_ports_for_streaming(struct ub960_data *priv,
for (i = 0; i < 8; i++)
ub960_rxport_write(priv, nport,
UB960_RR_VC_ID_MAP(i),
nport);
(nport << 4) | nport);
}
break;
@ -2939,20 +2975,78 @@ static const struct v4l2_subdev_pad_ops ub960_pad_ops = {
.set_fmt = ub960_set_fmt,
};
static void ub960_log_status_ub960_sp_eq(struct ub960_data *priv,
unsigned int nport)
{
struct device *dev = &priv->client->dev;
u8 eq_level;
s8 strobe_pos;
int ret;
u8 v;
/* Strobe */
ret = ub960_read(priv, UB960_XR_AEQ_CTL1, &v);
if (ret)
return;
dev_info(dev, "\t%s strobe\n",
(v & UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN) ? "Adaptive" :
"Manual");
if (v & UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN) {
ret = ub960_read(priv, UB960_XR_SFILTER_CFG, &v);
if (ret)
return;
dev_info(dev, "\tStrobe range [%d, %d]\n",
((v >> UB960_XR_SFILTER_CFG_SFILTER_MIN_SHIFT) & 0xf) - 7,
((v >> UB960_XR_SFILTER_CFG_SFILTER_MAX_SHIFT) & 0xf) - 7);
}
ret = ub960_rxport_get_strobe_pos(priv, nport, &strobe_pos);
if (ret)
return;
dev_info(dev, "\tStrobe pos %d\n", strobe_pos);
/* EQ */
ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_BYPASS, &v);
if (ret)
return;
dev_info(dev, "\t%s EQ\n",
(v & UB960_RR_AEQ_BYPASS_ENABLE) ? "Manual" :
"Adaptive");
if (!(v & UB960_RR_AEQ_BYPASS_ENABLE)) {
ret = ub960_rxport_read(priv, nport, UB960_RR_AEQ_MIN_MAX, &v);
if (ret)
return;
dev_info(dev, "\tEQ range [%u, %u]\n",
(v >> UB960_RR_AEQ_MIN_MAX_AEQ_FLOOR_SHIFT) & 0xf,
(v >> UB960_RR_AEQ_MIN_MAX_AEQ_MAX_SHIFT) & 0xf);
}
if (ub960_rxport_get_eq_level(priv, nport, &eq_level) == 0)
dev_info(dev, "\tEQ level %u\n", eq_level);
}
static int ub960_log_status(struct v4l2_subdev *sd)
{
struct ub960_data *priv = sd_to_ub960(sd);
struct device *dev = &priv->client->dev;
struct v4l2_subdev_state *state;
unsigned int nport;
unsigned int i;
u16 v16 = 0;
u8 v = 0;
u8 id[UB960_SR_FPD3_RX_ID_LEN];
state = v4l2_subdev_lock_and_get_active_state(sd);
for (i = 0; i < sizeof(id); i++)
for (unsigned int i = 0; i < sizeof(id); i++)
ub960_read(priv, UB960_SR_FPD3_RX_ID(i), &id[i]);
dev_info(dev, "ID '%.*s'\n", (int)sizeof(id), id);
@ -2986,9 +3080,6 @@ static int ub960_log_status(struct v4l2_subdev *sd)
for (nport = 0; nport < priv->hw_data->num_rxports; nport++) {
struct ub960_rxport *rxport = priv->rxports[nport];
u8 eq_level;
s8 strobe_pos;
unsigned int i;
dev_info(dev, "RX %u\n", nport);
@ -3009,7 +3100,7 @@ static int ub960_log_status(struct v4l2_subdev *sd)
dev_info(dev, "\trx_port_sts2 %#02x\n", v);
ub960_rxport_read16(priv, nport, UB960_RR_RX_FREQ_HIGH, &v16);
dev_info(dev, "\tlink freq %llu Hz\n", (v16 * 1000000ULL) >> 8);
dev_info(dev, "\tlink freq %llu Hz\n", ((u64)v16 * HZ_PER_MHZ) >> 8);
ub960_rxport_read16(priv, nport, UB960_RR_RX_PAR_ERR_HI, &v16);
dev_info(dev, "\tparity errors %u\n", v16);
@ -3023,47 +3114,11 @@ static int ub960_log_status(struct v4l2_subdev *sd)
ub960_rxport_read(priv, nport, UB960_RR_CSI_ERR_COUNTER, &v);
dev_info(dev, "\tcsi_err_counter %u\n", v);
/* Strobe */
ub960_read(priv, UB960_XR_AEQ_CTL1, &v);
dev_info(dev, "\t%s strobe\n",
(v & UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN) ? "Adaptive" :
"Manual");
if (v & UB960_XR_AEQ_CTL1_AEQ_SFILTER_EN) {
ub960_read(priv, UB960_XR_SFILTER_CFG, &v);
dev_info(dev, "\tStrobe range [%d, %d]\n",
((v >> UB960_XR_SFILTER_CFG_SFILTER_MIN_SHIFT) & 0xf) - 7,
((v >> UB960_XR_SFILTER_CFG_SFILTER_MAX_SHIFT) & 0xf) - 7);
}
ub960_rxport_get_strobe_pos(priv, nport, &strobe_pos);
dev_info(dev, "\tStrobe pos %d\n", strobe_pos);
/* EQ */
ub960_rxport_read(priv, nport, UB960_RR_AEQ_BYPASS, &v);
dev_info(dev, "\t%s EQ\n",
(v & UB960_RR_AEQ_BYPASS_ENABLE) ? "Manual" :
"Adaptive");
if (!(v & UB960_RR_AEQ_BYPASS_ENABLE)) {
ub960_rxport_read(priv, nport, UB960_RR_AEQ_MIN_MAX, &v);
dev_info(dev, "\tEQ range [%u, %u]\n",
(v >> UB960_RR_AEQ_MIN_MAX_AEQ_FLOOR_SHIFT) & 0xf,
(v >> UB960_RR_AEQ_MIN_MAX_AEQ_MAX_SHIFT) & 0xf);
}
if (ub960_rxport_get_eq_level(priv, nport, &eq_level) == 0)
dev_info(dev, "\tEQ level %u\n", eq_level);
if (!priv->hw_data->is_ub9702)
ub960_log_status_ub960_sp_eq(priv, nport);
/* GPIOs */
for (i = 0; i < UB960_NUM_BC_GPIOS; i++) {
for (unsigned int i = 0; i < UB960_NUM_BC_GPIOS; i++) {
u8 ctl_reg;
u8 ctl_shift;
@ -3834,13 +3889,16 @@ static int ub960_enable_core_hw(struct ub960_data *priv)
if (ret)
goto err_pd_gpio;
ret = ub960_read(priv, UB960_XR_REFCLK_FREQ, &refclk_freq);
if (priv->hw_data->is_ub9702)
ret = ub960_read(priv, UB9702_SR_REFCLK_FREQ, &refclk_freq);
else
ret = ub960_read(priv, UB960_XR_REFCLK_FREQ, &refclk_freq);
if (ret)
goto err_pd_gpio;
dev_dbg(dev, "refclk valid %u freq %u MHz (clk fw freq %lu MHz)\n",
!!(dev_sts & BIT(4)), refclk_freq,
clk_get_rate(priv->refclk) / 1000000);
clk_get_rate(priv->refclk) / HZ_PER_MHZ);
/* Disable all RX ports by default */
ret = ub960_write(priv, UB960_SR_RX_PORT_CTL, 0);
@ -3974,6 +4032,12 @@ static int ub960_probe(struct i2c_client *client)
schedule_delayed_work(&priv->poll_work,
msecs_to_jiffies(UB960_POLL_TIME_MS));
#ifdef UB960_DEBUG_I2C_RX_ID
for (unsigned int i = 0; i < priv->hw_data->num_rxports; i++)
ub960_write(priv, UB960_SR_I2C_RX_ID(i),
(UB960_DEBUG_I2C_RX_ID + i) << 1);
#endif
return 0;
err_free_sers:

2
drivers/media/i2c/imx208.c
View File

@ -814,7 +814,7 @@ static int imx208_read_otp(struct imx208 *imx208)
}
static ssize_t otp_read(struct file *filp, struct kobject *kobj,
struct bin_attribute *bin_attr,
const struct bin_attribute *bin_attr,
char *buf, loff_t off, size_t count)
{
struct i2c_client *client = to_i2c_client(kobj_to_dev(kobj));

81
drivers/media/i2c/imx290.c
View File

@ -170,12 +170,15 @@ enum imx290_model {
IMX290_MODEL_IMX290LQR,
IMX290_MODEL_IMX290LLR,
IMX290_MODEL_IMX327LQR,
IMX290_MODEL_IMX462LQR,
IMX290_MODEL_IMX462LLR,
};
struct imx290_model_info {
enum imx290_colour_variant colour_variant;
const struct cci_reg_sequence *init_regs;
size_t init_regs_num;
unsigned int max_analog_gain;
const char *name;
};
@ -267,7 +270,6 @@ static const struct cci_reg_sequence imx290_global_init_settings[] = {
{ IMX290_WINWV, 1097 },
{ IMX290_XSOUTSEL, IMX290_XSOUTSEL_XVSOUTSEL_VSYNC |
IMX290_XSOUTSEL_XHSOUTSEL_HSYNC },
{ CCI_REG8(0x3011), 0x02 },
{ CCI_REG8(0x3012), 0x64 },
{ CCI_REG8(0x3013), 0x00 },
};
@ -275,6 +277,51 @@ static const struct cci_reg_sequence imx290_global_init_settings[] = {
static const struct cci_reg_sequence imx290_global_init_settings_290[] = {
{ CCI_REG8(0x300f), 0x00 },
{ CCI_REG8(0x3010), 0x21 },
{ CCI_REG8(0x3011), 0x00 },
{ CCI_REG8(0x3016), 0x09 },
{ CCI_REG8(0x3070), 0x02 },
{ CCI_REG8(0x3071), 0x11 },
{ CCI_REG8(0x309b), 0x10 },
{ CCI_REG8(0x309c), 0x22 },
{ CCI_REG8(0x30a2), 0x02 },
{ CCI_REG8(0x30a6), 0x20 },
{ CCI_REG8(0x30a8), 0x20 },
{ CCI_REG8(0x30aa), 0x20 },
{ CCI_REG8(0x30ac), 0x20 },
{ CCI_REG8(0x30b0), 0x43 },
{ CCI_REG8(0x3119), 0x9e },
{ CCI_REG8(0x311c), 0x1e },
{ CCI_REG8(0x311e), 0x08 },
{ CCI_REG8(0x3128), 0x05 },
{ CCI_REG8(0x313d), 0x83 },
{ CCI_REG8(0x3150), 0x03 },
{ CCI_REG8(0x317e), 0x00 },
{ CCI_REG8(0x32b8), 0x50 },
{ CCI_REG8(0x32b9), 0x10 },
{ CCI_REG8(0x32ba), 0x00 },
{ CCI_REG8(0x32bb), 0x04 },
{ CCI_REG8(0x32c8), 0x50 },
{ CCI_REG8(0x32c9), 0x10 },
{ CCI_REG8(0x32ca), 0x00 },
{ CCI_REG8(0x32cb), 0x04 },
{ CCI_REG8(0x332c), 0xd3 },
{ CCI_REG8(0x332d), 0x10 },
{ CCI_REG8(0x332e), 0x0d },
{ CCI_REG8(0x3358), 0x06 },
{ CCI_REG8(0x3359), 0xe1 },
{ CCI_REG8(0x335a), 0x11 },
{ CCI_REG8(0x3360), 0x1e },
{ CCI_REG8(0x3361), 0x61 },
{ CCI_REG8(0x3362), 0x10 },
{ CCI_REG8(0x33b0), 0x50 },
{ CCI_REG8(0x33b2), 0x1a },
{ CCI_REG8(0x33b3), 0x04 },
};
static const struct cci_reg_sequence imx290_global_init_settings_462[] = {
{ CCI_REG8(0x300f), 0x00 },
{ CCI_REG8(0x3010), 0x21 },
{ CCI_REG8(0x3011), 0x02 },
{ CCI_REG8(0x3016), 0x09 },
{ CCI_REG8(0x3070), 0x02 },
{ CCI_REG8(0x3071), 0x11 },
@ -328,6 +375,7 @@ static const struct cci_reg_sequence xclk_regs[][IMX290_NUM_CLK_REGS] = {
};
static const struct cci_reg_sequence imx290_global_init_settings_327[] = {
{ CCI_REG8(0x3011), 0x02 },
{ CCI_REG8(0x309e), 0x4A },
{ CCI_REG8(0x309f), 0x4A },
{ CCI_REG8(0x313b), 0x61 },
@ -876,14 +924,10 @@ static int imx290_ctrl_init(struct imx290 *imx290)
* up to 72.0dB (240) add further digital gain. Limit the range to
* analog gain only, support for digital gain can be added separately
* if needed.
*
* The IMX327 and IMX462 are largely compatible with the IMX290, but
* have an analog gain range of 0.0dB to 29.4dB and 42dB of digital
* gain. When support for those sensors gets added to the driver, the
* gain control should be adjusted accordingly.
*/
v4l2_ctrl_new_std(&imx290->ctrls, &imx290_ctrl_ops,
V4L2_CID_ANALOGUE_GAIN, 0, 100, 1, 0);
V4L2_CID_ANALOGUE_GAIN, 0,
imx290->model->max_analog_gain, 1, 0);
/*
* Correct range will be determined through imx290_ctrl_update setting
@ -1441,20 +1485,37 @@ static const struct imx290_model_info imx290_models[] = {
.colour_variant = IMX290_VARIANT_COLOUR,
.init_regs = imx290_global_init_settings_290,
.init_regs_num = ARRAY_SIZE(imx290_global_init_settings_290),
.max_analog_gain = 100,
.name = "imx290",
},
[IMX290_MODEL_IMX290LLR] = {
.colour_variant = IMX290_VARIANT_MONO,
.init_regs = imx290_global_init_settings_290,
.init_regs_num = ARRAY_SIZE(imx290_global_init_settings_290),
.max_analog_gain = 100,
.name = "imx290",
},
[IMX290_MODEL_IMX327LQR] = {
.colour_variant = IMX290_VARIANT_COLOUR,
.init_regs = imx290_global_init_settings_327,
.init_regs_num = ARRAY_SIZE(imx290_global_init_settings_327),
.max_analog_gain = 98,
.name = "imx327",
},
[IMX290_MODEL_IMX462LQR] = {
.colour_variant = IMX290_VARIANT_COLOUR,
.init_regs = imx290_global_init_settings_462,
.init_regs_num = ARRAY_SIZE(imx290_global_init_settings_462),
.max_analog_gain = 98,
.name = "imx462",
},
[IMX290_MODEL_IMX462LLR] = {
.colour_variant = IMX290_VARIANT_MONO,
.init_regs = imx290_global_init_settings_462,
.init_regs_num = ARRAY_SIZE(imx290_global_init_settings_462),
.max_analog_gain = 98,
.name = "imx462",
},
};
static int imx290_parse_dt(struct imx290 *imx290)
@ -1653,6 +1714,12 @@ static const struct of_device_id imx290_of_match[] = {
}, {
.compatible = "sony,imx327lqr",
.data = &imx290_models[IMX290_MODEL_IMX327LQR],
}, {
.compatible = "sony,imx462lqr",
.data = &imx290_models[IMX290_MODEL_IMX462LQR],
}, {
.compatible = "sony,imx462llr",
.data = &imx290_models[IMX290_MODEL_IMX462LLR],
},
{ /* sentinel */ },
};

2
drivers/media/i2c/imx296.c
View File

@ -954,6 +954,8 @@ static int imx296_identify_model(struct imx296 *sensor)
return ret;
}
usleep_range(2000, 5000);
ret = imx296_read(sensor, IMX296_SENSOR_INFO);
if (ret < 0) {
dev_err(sensor->dev, "failed to read sensor information (%d)\n",

42
drivers/media/i2c/imx412.c
View File

@ -547,7 +547,7 @@ static int imx412_update_exp_gain(struct imx412 *imx412, u32 exposure, u32 gain)
lpfr = imx412->vblank + imx412->cur_mode->height;
dev_dbg(imx412->dev, "Set exp %u, analog gain %u, lpfr %u",
dev_dbg(imx412->dev, "Set exp %u, analog gain %u, lpfr %u\n",
exposure, gain, lpfr);
ret = imx412_write_reg(imx412, IMX412_REG_HOLD, 1, 1);
@ -594,7 +594,7 @@ static int imx412_set_ctrl(struct v4l2_ctrl *ctrl)
case V4L2_CID_VBLANK:
imx412->vblank = imx412->vblank_ctrl->val;
dev_dbg(imx412->dev, "Received vblank %u, new lpfr %u",
dev_dbg(imx412->dev, "Received vblank %u, new lpfr %u\n",
imx412->vblank,
imx412->vblank + imx412->cur_mode->height);
@ -613,7 +613,7 @@ static int imx412_set_ctrl(struct v4l2_ctrl *ctrl)
exposure = ctrl->val;
analog_gain = imx412->again_ctrl->val;
dev_dbg(imx412->dev, "Received exp %u, analog gain %u",
dev_dbg(imx412->dev, "Received exp %u, analog gain %u\n",
exposure, analog_gain);
ret = imx412_update_exp_gain(imx412, exposure, analog_gain);
@ -622,7 +622,7 @@ static int imx412_set_ctrl(struct v4l2_ctrl *ctrl)
break;
default:
dev_err(imx412->dev, "Invalid control %d", ctrl->id);
dev_err(imx412->dev, "Invalid control %d\n", ctrl->id);
ret = -EINVAL;
}
@ -803,14 +803,14 @@ static int imx412_start_streaming(struct imx412 *imx412)
ret = imx412_write_regs(imx412, reg_list->regs,
reg_list->num_of_regs);
if (ret) {
dev_err(imx412->dev, "fail to write initial registers");
dev_err(imx412->dev, "fail to write initial registers\n");
return ret;
}
/* Setup handler will write actual exposure and gain */
ret = __v4l2_ctrl_handler_setup(imx412->sd.ctrl_handler);
if (ret) {
dev_err(imx412->dev, "fail to setup handler");
dev_err(imx412->dev, "fail to setup handler\n");
return ret;
}
@ -821,7 +821,7 @@ static int imx412_start_streaming(struct imx412 *imx412)
ret = imx412_write_reg(imx412, IMX412_REG_MODE_SELECT,
1, IMX412_MODE_STREAMING);
if (ret) {
dev_err(imx412->dev, "fail to start streaming");
dev_err(imx412->dev, "fail to start streaming\n");
return ret;
}
@ -895,7 +895,7 @@ static int imx412_detect(struct imx412 *imx412)
return ret;
if (val != IMX412_ID) {
dev_err(imx412->dev, "chip id mismatch: %x!=%x",
dev_err(imx412->dev, "chip id mismatch: %x!=%x\n",
IMX412_ID, val);
return -ENXIO;
}
@ -927,7 +927,7 @@ static int imx412_parse_hw_config(struct imx412 *imx412)
imx412->reset_gpio = devm_gpiod_get_optional(imx412->dev, "reset",
GPIOD_OUT_LOW);
if (IS_ERR(imx412->reset_gpio)) {
dev_err(imx412->dev, "failed to get reset gpio %ld",
dev_err(imx412->dev, "failed to get reset gpio %ld\n",
PTR_ERR(imx412->reset_gpio));
return PTR_ERR(imx412->reset_gpio);
}
@ -935,13 +935,13 @@ static int imx412_parse_hw_config(struct imx412 *imx412)
/* Get sensor input clock */
imx412->inclk = devm_clk_get(imx412->dev, NULL);
if (IS_ERR(imx412->inclk)) {
dev_err(imx412->dev, "could not get inclk");
dev_err(imx412->dev, "could not get inclk\n");
return PTR_ERR(imx412->inclk);
}
rate = clk_get_rate(imx412->inclk);
if (rate != IMX412_INCLK_RATE) {
dev_err(imx412->dev, "inclk frequency mismatch");
dev_err(imx412->dev, "inclk frequency mismatch\n");
return -EINVAL;
}
@ -966,14 +966,14 @@ static int imx412_parse_hw_config(struct imx412 *imx412)
if (bus_cfg.bus.mipi_csi2.num_data_lanes != IMX412_NUM_DATA_LANES) {
dev_err(imx412->dev,
"number of CSI2 data lanes %d is not supported",
"number of CSI2 data lanes %d is not supported\n",
bus_cfg.bus.mipi_csi2.num_data_lanes);
ret = -EINVAL;
goto done_endpoint_free;
}
if (!bus_cfg.nr_of_link_frequencies) {
dev_err(imx412->dev, "no link frequencies defined");
dev_err(imx412->dev, "no link frequencies defined\n");
ret = -EINVAL;
goto done_endpoint_free;
}
@ -1034,7 +1034,7 @@ static int imx412_power_on(struct device *dev)
ret = clk_prepare_enable(imx412->inclk);
if (ret) {
dev_err(imx412->dev, "fail to enable inclk");
dev_err(imx412->dev, "fail to enable inclk\n");
goto error_reset;
}
@ -1145,7 +1145,7 @@ static int imx412_init_controls(struct imx412 *imx412)
imx412->hblank_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
if (ctrl_hdlr->error) {
dev_err(imx412->dev, "control init failed: %d",
dev_err(imx412->dev, "control init failed: %d\n",
ctrl_hdlr->error);
v4l2_ctrl_handler_free(ctrl_hdlr);
return ctrl_hdlr->error;
@ -1183,7 +1183,7 @@ static int imx412_probe(struct i2c_client *client)
ret = imx412_parse_hw_config(imx412);
if (ret) {
dev_err(imx412->dev, "HW configuration is not supported");
dev_err(imx412->dev, "HW configuration is not supported\n");
return ret;
}
@ -1191,14 +1191,14 @@ static int imx412_probe(struct i2c_client *client)
ret = imx412_power_on(imx412->dev);
if (ret) {
dev_err(imx412->dev, "failed to power-on the sensor");
dev_err(imx412->dev, "failed to power-on the sensor\n");
goto error_mutex_destroy;
}
/* Check module identity */
ret = imx412_detect(imx412);
if (ret) {
dev_err(imx412->dev, "failed to find sensor: %d", ret);
dev_err(imx412->dev, "failed to find sensor: %d\n", ret);
goto error_power_off;
}
@ -1208,7 +1208,7 @@ static int imx412_probe(struct i2c_client *client)
ret = imx412_init_controls(imx412);
if (ret) {
dev_err(imx412->dev, "failed to init controls: %d", ret);
dev_err(imx412->dev, "failed to init controls: %d\n", ret);
goto error_power_off;
}
@ -1222,14 +1222,14 @@ static int imx412_probe(struct i2c_client *client)
imx412->pad.flags = MEDIA_PAD_FL_SOURCE;
ret = media_entity_pads_init(&imx412->sd.entity, 1, &imx412->pad);
if (ret) {
dev_err(imx412->dev, "failed to init entity pads: %d", ret);
dev_err(imx412->dev, "failed to init entity pads: %d\n", ret);
goto error_handler_free;
}
ret = v4l2_async_register_subdev_sensor(&imx412->sd);
if (ret < 0) {
dev_err(imx412->dev,
"failed to register async subdev: %d", ret);
"failed to register async subdev: %d\n", ret);
goto error_media_entity;
}

58
drivers/media/i2c/ov2740.c
View File

@ -11,6 +11,7 @@
#include <linux/pm_runtime.h>
#include <linux/nvmem-provider.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-fwnode.h>
@ -76,6 +77,14 @@
/* OTP registers from sensor */
#define OV2740_REG_OTP_CUSTOMER 0x7010
static const char * const ov2740_supply_name[] = {
"AVDD",
"DOVDD",
"DVDD",
};
#define OV2740_NUM_SUPPLIES ARRAY_SIZE(ov2740_supply_name)
struct nvm_data {
struct nvmem_device *nvmem;
struct regmap *regmap;
@ -523,9 +532,11 @@ struct ov2740 {
struct v4l2_ctrl *hblank;
struct v4l2_ctrl *exposure;
/* GPIOs, clocks */
/* GPIOs, clocks, regulators */
struct gpio_desc *reset_gpio;
struct gpio_desc *powerdown_gpio;
struct clk *clk;
struct regulator_bulk_data supplies[OV2740_NUM_SUPPLIES];
/* Current mode */
const struct ov2740_mode *cur_mode;
@ -644,6 +655,8 @@ static int ov2740_identify_module(struct ov2740 *ov2740)
return -ENXIO;
}
dev_dbg(&client->dev, "chip id: %x\n", val);
ov2740->identified = true;
return 0;
@ -753,15 +766,17 @@ static const struct v4l2_ctrl_ops ov2740_ctrl_ops = {
static int ov2740_init_controls(struct ov2740 *ov2740)
{
struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
struct v4l2_ctrl_handler *ctrl_hdlr;
const struct ov2740_mode *cur_mode;
s64 exposure_max, h_blank, pixel_rate;
u32 vblank_min, vblank_max, vblank_default;
struct v4l2_fwnode_device_properties props;
int size;
int ret;
ctrl_hdlr = &ov2740->ctrl_handler;
ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
if (ret)
return ret;
@ -811,6 +826,13 @@ static int ov2740_init_controls(struct ov2740 *ov2740)
V4L2_CID_TEST_PATTERN,
ARRAY_SIZE(ov2740_test_pattern_menu) - 1,
0, 0, ov2740_test_pattern_menu);
ret = v4l2_fwnode_device_parse(&client->dev, &props);
if (ret)
return ret;
v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov2740_ctrl_ops, &props);
if (ctrl_hdlr->error) {
v4l2_ctrl_handler_free(ctrl_hdlr);
return ctrl_hdlr->error;
@ -1295,7 +1317,9 @@ static int ov2740_suspend(struct device *dev)
struct ov2740 *ov2740 = to_ov2740(sd);
gpiod_set_value_cansleep(ov2740->reset_gpio, 1);
gpiod_set_value_cansleep(ov2740->powerdown_gpio, 1);
clk_disable_unprepare(ov2740->clk);
regulator_bulk_disable(OV2740_NUM_SUPPLIES, ov2740->supplies);
return 0;
}
@ -1305,10 +1329,17 @@ static int ov2740_resume(struct device *dev)
struct ov2740 *ov2740 = to_ov2740(sd);
int ret;
ret = clk_prepare_enable(ov2740->clk);
ret = regulator_bulk_enable(OV2740_NUM_SUPPLIES, ov2740->supplies);
if (ret)
return ret;
ret = clk_prepare_enable(ov2740->clk);
if (ret) {
regulator_bulk_disable(OV2740_NUM_SUPPLIES, ov2740->supplies);
return ret;
}
gpiod_set_value_cansleep(ov2740->powerdown_gpio, 0);
gpiod_set_value_cansleep(ov2740->reset_gpio, 0);
msleep(20);
@ -1320,7 +1351,7 @@ static int ov2740_probe(struct i2c_client *client)
struct device *dev = &client->dev;
struct ov2740 *ov2740;
bool full_power;
int ret;
int i, ret;
ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL);
if (!ov2740)
@ -1337,9 +1368,17 @@ static int ov2740_probe(struct i2c_client *client)
if (IS_ERR(ov2740->reset_gpio)) {
return dev_err_probe(dev, PTR_ERR(ov2740->reset_gpio),
"failed to get reset GPIO\n");
} else if (ov2740->reset_gpio) {
}
ov2740->powerdown_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH);
if (IS_ERR(ov2740->powerdown_gpio)) {
return dev_err_probe(dev, PTR_ERR(ov2740->powerdown_gpio),
"failed to get powerdown GPIO\n");
}
if (ov2740->reset_gpio || ov2740->powerdown_gpio) {
/*
* Ensure reset is asserted for at least 20 ms before
* Ensure reset/powerdown is asserted for at least 20 ms before
* ov2740_resume() deasserts it.
*/
msleep(20);
@ -1350,6 +1389,13 @@ static int ov2740_probe(struct i2c_client *client)
return dev_err_probe(dev, PTR_ERR(ov2740->clk),
"failed to get clock\n");
for (i = 0; i < OV2740_NUM_SUPPLIES; i++)
ov2740->supplies[i].supply = ov2740_supply_name[i];
ret = devm_regulator_bulk_get(dev, OV2740_NUM_SUPPLIES, ov2740->supplies);
if (ret)
return dev_err_probe(dev, ret, "failed to get regulators\n");
full_power = acpi_dev_state_d0(&client->dev);
if (full_power) {
/* ACPI does not always clear the reset GPIO / enable the clock */

1
drivers/media/i2c/ov5640.c
View File

@ -1982,6 +1982,7 @@ static int ov5640_get_light_freq(struct ov5640_dev *sensor)
light_freq = 50;
} else {
/* 60Hz */
light_freq = 60;
}
}

2
drivers/media/i2c/ov9282.c
View File

@ -40,7 +40,7 @@
/* Exposure control */
#define OV9282_REG_EXPOSURE 0x3500
#define OV9282_EXPOSURE_MIN 1
#define OV9282_EXPOSURE_OFFSET 12
#define OV9282_EXPOSURE_OFFSET 25
#define OV9282_EXPOSURE_STEP 1
#define OV9282_EXPOSURE_DEFAULT 0x0282

17
drivers/media/pci/b2c2/flexcop-dma.c
View File

@ -123,23 +123,6 @@ static int flexcop_dma_remap(struct flexcop_device *fc,
return 0;
}
int flexcop_dma_control_size_irq(struct flexcop_device *fc,
flexcop_dma_index_t no,
int onoff)
{
flexcop_ibi_value v = fc->read_ibi_reg(fc, ctrl_208);
if (no & FC_DMA_1)
v.ctrl_208.DMA1_IRQ_Enable_sig = onoff;
if (no & FC_DMA_2)
v.ctrl_208.DMA2_IRQ_Enable_sig = onoff;
fc->write_ibi_reg(fc, ctrl_208, v);
return 0;
}
EXPORT_SYMBOL(flexcop_dma_control_size_irq);
int flexcop_dma_control_timer_irq(struct flexcop_device *fc,
flexcop_dma_index_t no,
int onoff)

15
drivers/media/pci/cx18/cx18-gpio.c
View File

@ -305,21 +305,6 @@ int cx18_gpio_register(struct cx18 *cx, u32 hw)
return v4l2_device_register_subdev(&cx->v4l2_dev, sd);
}
void cx18_reset_ir_gpio(void *data)
{
struct cx18 *cx = to_cx18(data);
if (cx->card->gpio_i2c_slave_reset.ir_reset_mask == 0)
return;
CX18_DEBUG_INFO("Resetting IR microcontroller\n");
v4l2_subdev_call(&cx->sd_resetctrl,
core, reset, CX18_GPIO_RESET_Z8F0811);
}
EXPORT_SYMBOL(cx18_reset_ir_gpio);
/* This symbol is exported for use by lirc_pvr150 for the IR-blaster */
/* Xceive tuner reset function */
int cx18_reset_tuner_gpio(void *dev, int component, int cmd, int value)
{

1
drivers/media/pci/cx18/cx18-gpio.h
View File

@ -17,5 +17,4 @@ enum cx18_gpio_reset_type {
CX18_GPIO_RESET_XC2028 = 2,
};
void cx18_reset_ir_gpio(void *data);
int cx18_reset_tuner_gpio(void *dev, int component, int cmd, int value);

8
drivers/media/pci/intel/ipu6/ipu6-buttress.c
View File

@ -847,10 +847,10 @@ int ipu6_buttress_init(struct ipu6_device *isp)
INIT_LIST_HEAD(&b->constraints);
isp->secure_mode = ipu6_buttress_get_secure_mode(isp);
dev_info(&isp->pdev->dev, "IPU6 in %s mode touch 0x%x mask 0x%x\n",
isp->secure_mode ? "secure" : "non-secure",
readl(isp->base + BUTTRESS_REG_SECURITY_TOUCH),
readl(isp->base + BUTTRESS_REG_CAMERA_MASK));
dev_dbg(&isp->pdev->dev, "IPU6 in %s mode touch 0x%x mask 0x%x\n",
isp->secure_mode ? "secure" : "non-secure",
readl(isp->base + BUTTRESS_REG_SECURITY_TOUCH),
readl(isp->base + BUTTRESS_REG_CAMERA_MASK));
b->wdt_cached_value = readl(isp->base + BUTTRESS_REG_WDT);
writel(BUTTRESS_IRQS, isp->base + BUTTRESS_REG_ISR_CLEAR);

2
drivers/media/pci/intel/ipu6/ipu6-cpd.c
View File

@ -275,7 +275,7 @@ static int ipu6_cpd_validate_moduledata(struct ipu6_device *isp,
return -EINVAL;
}
dev_info(&isp->pdev->dev, "FW version: %x\n", mod_hdr->fw_pkg_date);
dev_dbg(&isp->pdev->dev, "FW version: %x\n", mod_hdr->fw_pkg_date);
ret = ipu6_cpd_validate_cpd(isp, moduledata + mod_hdr->hdr_len,
moduledata_size - mod_hdr->hdr_len,
moduledata_size);

1
drivers/media/pci/intel/ipu6/ipu6-isys.c
View File

@ -1133,6 +1133,7 @@ static int isys_probe(struct auxiliary_device *auxdev,
free_fw_msg_bufs:
free_fw_msg_bufs(isys);
out_remove_pkg_dir_shared_buffer:
cpu_latency_qos_remove_request(&isys->pm_qos);
if (!isp->secure_mode)
ipu6_cpd_free_pkg_dir(adev);
remove_shared_buffer:

4
drivers/media/pci/mgb4/mgb4_core.c
View File

@ -40,7 +40,9 @@
#include "mgb4_trigger.h"
#include "mgb4_core.h"
#define MGB4_USER_IRQS 16
#define MGB4_USER_IRQS 16
#define MGB4_MGB4_BAR_ID 0
#define MGB4_XDMA_BAR_ID 1
#define DIGITEQ_VID 0x1ed8
#define T100_DID 0x0101

3
drivers/media/pci/mgb4/mgb4_core.h
View File

@ -18,9 +18,6 @@
#define MGB4_VIN_DEVICES 2
#define MGB4_VOUT_DEVICES 2
#define MGB4_MGB4_BAR_ID 0
#define MGB4_XDMA_BAR_ID 1
#define MGB4_IS_GMSL(mgbdev) \
((mgbdev)->module_version >> 4 == 2)
#define MGB4_IS_FPDL3(mgbdev) \

12
drivers/media/pci/mgb4/mgb4_sysfs_in.c
View File

@ -333,7 +333,7 @@ static ssize_t hsync_width_show(struct device *dev,
struct video_device *vdev = to_video_device(dev);
struct mgb4_vin_dev *vindev = video_get_drvdata(vdev);
u32 sig = mgb4_read_reg(&vindev->mgbdev->video,
vindev->config->regs.signal);
vindev->config->regs.hsync);
return sprintf(buf, "%u\n", (sig & 0x00FF0000) >> 16);
}
@ -344,7 +344,7 @@ static ssize_t vsync_width_show(struct device *dev,
struct video_device *vdev = to_video_device(dev);
struct mgb4_vin_dev *vindev = video_get_drvdata(vdev);
u32 sig = mgb4_read_reg(&vindev->mgbdev->video,
vindev->config->regs.signal2);
vindev->config->regs.vsync);
return sprintf(buf, "%u\n", (sig & 0x00FF0000) >> 16);
}
@ -355,7 +355,7 @@ static ssize_t hback_porch_show(struct device *dev,
struct video_device *vdev = to_video_device(dev);
struct mgb4_vin_dev *vindev = video_get_drvdata(vdev);
u32 sig = mgb4_read_reg(&vindev->mgbdev->video,
vindev->config->regs.signal);
vindev->config->regs.hsync);
return sprintf(buf, "%u\n", (sig & 0x0000FF00) >> 8);
}
@ -366,7 +366,7 @@ static ssize_t hfront_porch_show(struct device *dev,
struct video_device *vdev = to_video_device(dev);
struct mgb4_vin_dev *vindev = video_get_drvdata(vdev);
u32 sig = mgb4_read_reg(&vindev->mgbdev->video,
vindev->config->regs.signal);
vindev->config->regs.hsync);
return sprintf(buf, "%u\n", (sig & 0x000000FF));
}
@ -377,7 +377,7 @@ static ssize_t vback_porch_show(struct device *dev,
struct video_device *vdev = to_video_device(dev);
struct mgb4_vin_dev *vindev = video_get_drvdata(vdev);
u32 sig = mgb4_read_reg(&vindev->mgbdev->video,
vindev->config->regs.signal2);
vindev->config->regs.vsync);
return sprintf(buf, "%u\n", (sig & 0x0000FF00) >> 8);
}
@ -388,7 +388,7 @@ static ssize_t vfront_porch_show(struct device *dev,
struct video_device *vdev = to_video_device(dev);
struct mgb4_vin_dev *vindev = video_get_drvdata(vdev);
u32 sig = mgb4_read_reg(&vindev->mgbdev->video,
vindev->config->regs.signal2);
vindev->config->regs.vsync);
return sprintf(buf, "%u\n", (sig & 0x000000FF));
}

20
drivers/media/pci/mgb4/mgb4_vin.c
View File

@ -143,8 +143,8 @@ static int get_timings(struct mgb4_vin_dev *vindev,
u32 status = mgb4_read_reg(video, regs->status);
u32 pclk = mgb4_read_reg(video, regs->pclk);
u32 signal = mgb4_read_reg(video, regs->signal);
u32 signal2 = mgb4_read_reg(video, regs->signal2);
u32 hsync = mgb4_read_reg(video, regs->hsync);
u32 vsync = mgb4_read_reg(video, regs->vsync);
u32 resolution = mgb4_read_reg(video, regs->resolution);
if (!(status & (1U << 2)))
@ -161,12 +161,12 @@ static int get_timings(struct mgb4_vin_dev *vindev,
if (status & (1U << 13))
timings->bt.polarities |= V4L2_DV_VSYNC_POS_POL;
timings->bt.pixelclock = pclk * 1000;
timings->bt.hsync = (signal & 0x00FF0000) >> 16;
timings->bt.vsync = (signal2 & 0x00FF0000) >> 16;
timings->bt.hbackporch = (signal & 0x0000FF00) >> 8;
timings->bt.hfrontporch = signal & 0x000000FF;
timings->bt.vbackporch = (signal2 & 0x0000FF00) >> 8;
timings->bt.vfrontporch = signal2 & 0x000000FF;
timings->bt.hsync = (hsync & 0x00FF0000) >> 16;
timings->bt.vsync = (vsync & 0x00FF0000) >> 16;
timings->bt.hbackporch = (hsync & 0x0000FF00) >> 8;
timings->bt.hfrontporch = hsync & 0x000000FF;
timings->bt.vbackporch = (vsync & 0x0000FF00) >> 8;
timings->bt.vfrontporch = vsync & 0x000000FF;
return 0;
}
@ -864,9 +864,9 @@ static void create_debugfs(struct mgb4_vin_dev *vindev)
vindev->regs[5].name = "PCLK_FREQUENCY";
vindev->regs[5].offset = vindev->config->regs.pclk;
vindev->regs[6].name = "VIDEO_PARAMS_1";
vindev->regs[6].offset = vindev->config->regs.signal;
vindev->regs[6].offset = vindev->config->regs.hsync;
vindev->regs[7].name = "VIDEO_PARAMS_2";
vindev->regs[7].offset = vindev->config->regs.signal2;
vindev->regs[7].offset = vindev->config->regs.vsync;
vindev->regs[8].name = "PADDING_PIXELS";
vindev->regs[8].offset = vindev->config->regs.padding;
if (has_timeperframe(video)) {

4
drivers/media/pci/mgb4/mgb4_vin.h
View File

@ -22,8 +22,8 @@ struct mgb4_vin_regs {
u32 frame_period;
u32 sync;
u32 pclk;
u32 signal;
u32 signal2;
u32 hsync;
u32 vsync;
u32 padding;
u32 timer;
};

14
drivers/media/pci/mgb4/mgb4_vout.c
View File

@ -24,10 +24,6 @@
#include "mgb4_cmt.h"
#include "mgb4_vout.h"
#define DEFAULT_WIDTH 1280
#define DEFAULT_HEIGHT 640
#define DEFAULT_PERIOD (MGB4_HW_FREQ / 60)
ATTRIBUTE_GROUPS(mgb4_fpdl3_out);
ATTRIBUTE_GROUPS(mgb4_gmsl_out);
@ -180,7 +176,10 @@ static void stop_streaming(struct vb2_queue *vq)
xdma_disable_user_irq(mgbdev->xdev, irq);
cancel_work_sync(&voutdev->dma_work);
mgb4_mask_reg(&mgbdev->video, voutdev->config->regs.config, 0x2, 0x0);
mgb4_write_reg(&mgbdev->video, voutdev->config->regs.padding, 0);
return_all_buffers(voutdev, VB2_BUF_STATE_ERROR);
}
@ -196,6 +195,7 @@ static int start_streaming(struct vb2_queue *vq, unsigned int count)
int rv;
u32 addr;
mgb4_write_reg(video, config->regs.padding, voutdev->padding);
mgb4_mask_reg(video, config->regs.config, 0x2, 0x2);
addr = mgb4_read_reg(video, config->regs.address);
@ -359,7 +359,6 @@ static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
voutdev->padding = (f->fmt.pix.bytesperline - (f->fmt.pix.width
* pixelsize)) / pixelsize;
mgb4_write_reg(video, voutdev->config->regs.padding, voutdev->padding);
return 0;
}
@ -661,11 +660,10 @@ static void fpga_init(struct mgb4_vout_dev *voutdev)
const struct mgb4_vout_regs *regs = &voutdev->config->regs;
mgb4_write_reg(video, regs->config, 0x00000011);
mgb4_write_reg(video, regs->resolution,
(DEFAULT_WIDTH << 16) | DEFAULT_HEIGHT);
mgb4_write_reg(video, regs->resolution, (1280 << 16) | 640);
mgb4_write_reg(video, regs->hsync, 0x00283232);
mgb4_write_reg(video, regs->vsync, 0x40141F1E);
mgb4_write_reg(video, regs->frame_limit, DEFAULT_PERIOD);
mgb4_write_reg(video, regs->frame_limit, MGB4_HW_FREQ / 60);
mgb4_write_reg(video, regs->padding, 0x00000000);
voutdev->freq = mgb4_cmt_set_vout_freq(voutdev, 61150 >> 1) << 1;

42
drivers/media/platform/broadcom/bcm2835-unicam.c
View File

@ -199,6 +199,7 @@ struct unicam_device {
/* subdevice async notifier */
struct v4l2_async_notifier notifier;
unsigned int sequence;
bool frame_started;
/* Sensor node */
struct {
@ -546,7 +547,8 @@ unicam_find_format_by_fourcc(u32 fourcc, u32 pad)
}
for (i = 0; i < num_formats; ++i) {
if (formats[i].fourcc == fourcc)
if (formats[i].fourcc == fourcc ||
formats[i].unpacked_fourcc == fourcc)
return &formats[i];
}
@ -638,7 +640,14 @@ static inline void unicam_reg_write_field(struct unicam_device *unicam, u32 offs
static void unicam_wr_dma_addr(struct unicam_node *node,
struct unicam_buffer *buf)
{
dma_addr_t endaddr = buf->dma_addr + buf->size;
/*
* Due to a HW bug causing buffer overruns in circular buffer mode under
* certain (not yet fully known) conditions, the dummy buffer allocation
* is set to a a single page size, but the hardware gets programmed with
* a buffer size of 0.
*/
dma_addr_t endaddr = buf->dma_addr +
(buf != &node->dummy_buf ? buf->size : 0);
if (node->id == UNICAM_IMAGE_NODE) {
unicam_reg_write(node->dev, UNICAM_IBSA0, buf->dma_addr);
@ -742,6 +751,8 @@ static irqreturn_t unicam_isr(int irq, void *dev)
* buffer forever.
*/
if (fe) {
bool inc_seq = unicam->frame_started;
/*
* Ensure we have swapped buffers already as we can't
* stop the peripheral. If no buffer is available, use a
@ -761,11 +772,24 @@ static irqreturn_t unicam_isr(int irq, void *dev)
* + FS + LS). In this case, we cannot signal the buffer
* as complete, as the HW will reuse that buffer.
*/
if (node->cur_frm && node->cur_frm != node->next_frm)
if (node->cur_frm && node->cur_frm != node->next_frm) {
unicam_process_buffer_complete(node, sequence);
inc_seq = true;
}
node->cur_frm = node->next_frm;
}
unicam->sequence++;
/*
* Increment the sequence number conditionally on either a FS
* having already occurred, or in the FE + FS condition as
* caught in the FE handler above. This ensures the sequence
* number corresponds to the frames generated by the sensor, not
* the frames dequeued to userland.
*/
if (inc_seq) {
unicam->sequence++;
unicam->frame_started = false;
}
}
if (ista & UNICAM_FSI) {
@ -795,6 +819,7 @@ static irqreturn_t unicam_isr(int irq, void *dev)
}
unicam_queue_event_sof(unicam);
unicam->frame_started = true;
}
/*
@ -816,11 +841,6 @@ static irqreturn_t unicam_isr(int irq, void *dev)
}
}
if (unicam_reg_read(unicam, UNICAM_ICTL) & UNICAM_FCM) {
/* Switch out of trigger mode if selected */
unicam_reg_write_field(unicam, UNICAM_ICTL, 1, UNICAM_TFC);
unicam_reg_write_field(unicam, UNICAM_ICTL, 0, UNICAM_FCM);
}
return IRQ_HANDLED;
}
@ -984,8 +1004,7 @@ static void unicam_start_rx(struct unicam_device *unicam,
unicam_reg_write_field(unicam, UNICAM_ANA, 0, UNICAM_DDL);
/* Always start in trigger frame capture mode (UNICAM_FCM set) */
val = UNICAM_FSIE | UNICAM_FEIE | UNICAM_FCM | UNICAM_IBOB;
val = UNICAM_FSIE | UNICAM_FEIE | UNICAM_IBOB;
line_int_freq = max(fmt->height >> 2, 128);
unicam_set_field(&val, line_int_freq, UNICAM_LCIE_MASK);
unicam_reg_write(unicam, UNICAM_ICTL, val);
@ -1413,6 +1432,7 @@ static int unicam_sd_enable_streams(struct v4l2_subdev *sd,
if (unicam->pipe.nodes & BIT(UNICAM_METADATA_NODE))
unicam_start_metadata(unicam);
unicam->frame_started = false;
unicam_start_rx(unicam, state);
}

7
drivers/media/platform/marvell/mcam-core.c
View File

@ -935,7 +935,12 @@ static int mclk_enable(struct clk_hw *hw)
ret = pm_runtime_resume_and_get(cam->dev);
if (ret < 0)
return ret;
clk_enable(cam->clk[0]);
ret = clk_enable(cam->clk[0]);
if (ret) {
pm_runtime_put(cam->dev);
return ret;
}
mcam_reg_write(cam, REG_CLKCTRL, (mclk_src << 29) | mclk_div);
mcam_ctlr_power_up(cam);

77
drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
View File

@ -114,19 +114,15 @@ static struct img_config *__get_config_offset(struct mdp_dev *mdp,
if (pp_idx >= mdp->mdp_data->pp_used)
goto err_param;
if (CFG_CHECK(MT8183, p_id))
if (CFG_CHECK(MT8183, p_id)) {
cfg_c = CFG_OFST(MT8183, param->config, pp_idx);
else if (CFG_CHECK(MT8195, p_id))
cfg_c = CFG_OFST(MT8195, param->config, pp_idx);
else
goto err_param;
if (CFG_CHECK(MT8183, p_id))
cfg_n = CFG_OFST(MT8183, param->config, pp_idx + 1);
else if (CFG_CHECK(MT8195, p_id))
} else if (CFG_CHECK(MT8195, p_id)) {
cfg_c = CFG_OFST(MT8195, param->config, pp_idx);
cfg_n = CFG_OFST(MT8195, param->config, pp_idx + 1);
else
} else {
goto err_param;
}
if ((long)cfg_n - (long)mdp->vpu.config > bound) {
dev_err(dev, "config offset %ld OOB %ld\n", (long)cfg_n, bound);
@ -325,8 +321,7 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd,
/* Enable mux settings */
for (index = 0; index < ctrl->num_sets; index++) {
set = &ctrl->sets[index];
cmdq_pkt_write_mask(&cmd->pkt, set->subsys_id, set->reg,
set->value, 0xFFFFFFFF);
cmdq_pkt_write(&cmd->pkt, set->subsys_id, set->reg, set->value);
}
/* Config sub-frame information */
for (index = (num_comp - 1); index >= 0; index--) {
@ -381,8 +376,7 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd,
/* Disable mux settings */
for (index = 0; index < ctrl->num_sets; index++) {
set = &ctrl->sets[index];
cmdq_pkt_write_mask(&cmd->pkt, set->subsys_id, set->reg,
0, 0xFFFFFFFF);
cmdq_pkt_write(&cmd->pkt, set->subsys_id, set->reg, 0);
}
return 0;
@ -471,43 +465,6 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd,
return 0;
}
static int mdp_cmdq_pkt_create(struct cmdq_client *client, struct cmdq_pkt *pkt,
size_t size)
{
struct device *dev;
dma_addr_t dma_addr;
pkt->va_base = kzalloc(size, GFP_KERNEL);
if (!pkt->va_base)
return -ENOMEM;
pkt->buf_size = size;
pkt->cl = (void *)client;
dev = client->chan->mbox->dev;
dma_addr = dma_map_single(dev, pkt->va_base, pkt->buf_size,
DMA_TO_DEVICE);
if (dma_mapping_error(dev, dma_addr)) {
dev_err(dev, "dma map failed, size=%u\n", (u32)(u64)size);
kfree(pkt->va_base);
return -ENOMEM;
}
pkt->pa_base = dma_addr;
return 0;
}
static void mdp_cmdq_pkt_destroy(struct cmdq_pkt *pkt)
{
struct cmdq_client *client = (struct cmdq_client *)pkt->cl;
dma_unmap_single(client->chan->mbox->dev, pkt->pa_base, pkt->buf_size,
DMA_TO_DEVICE);
kfree(pkt->va_base);
pkt->va_base = NULL;
}
static void mdp_auto_release_work(struct work_struct *work)
{
struct mdp_cmdq_cmd *cmd;
@ -538,7 +495,7 @@ static void mdp_auto_release_work(struct work_struct *work)
wake_up(&mdp->callback_wq);
}
mdp_cmdq_pkt_destroy(&cmd->pkt);
cmdq_pkt_destroy(mdp->cmdq_clt[cmd->pp_idx], &cmd->pkt);
kfree(cmd->comps);
cmd->comps = NULL;
kfree(cmd);
@ -578,7 +535,7 @@ static void mdp_handle_cmdq_callback(struct mbox_client *cl, void *mssg)
if (refcount_dec_and_test(&mdp->job_count))
wake_up(&mdp->callback_wq);
mdp_cmdq_pkt_destroy(&cmd->pkt);
cmdq_pkt_destroy(mdp->cmdq_clt[cmd->pp_idx], &cmd->pkt);
kfree(cmd->comps);
cmd->comps = NULL;
kfree(cmd);
@ -607,20 +564,13 @@ static struct mdp_cmdq_cmd *mdp_cmdq_prepare(struct mdp_dev *mdp,
goto err_uninit;
}
if (CFG_CHECK(MT8183, p_id))
num_comp = CFG_GET(MT8183, config, num_components);
else if (CFG_CHECK(MT8195, p_id))
num_comp = CFG_GET(MT8195, config, num_components);
else
goto err_uninit;
cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
if (!cmd) {
ret = -ENOMEM;
goto err_uninit;
}
ret = mdp_cmdq_pkt_create(mdp->cmdq_clt[pp_idx], &cmd->pkt, SZ_16K);
ret = cmdq_pkt_create(mdp->cmdq_clt[pp_idx], &cmd->pkt, SZ_16K);
if (ret)
goto err_free_cmd;
@ -632,6 +582,7 @@ static struct mdp_cmdq_cmd *mdp_cmdq_prepare(struct mdp_dev *mdp,
ret = -EINVAL;
goto err_destroy_pkt;
}
comps = kcalloc(num_comp, sizeof(*comps), GFP_KERNEL);
if (!comps) {
ret = -ENOMEM;
@ -676,7 +627,8 @@ static struct mdp_cmdq_cmd *mdp_cmdq_prepare(struct mdp_dev *mdp,
dev_err(dev, "mdp_path_config error %d\n", pp_idx);
goto err_free_path;
}
cmdq_pkt_finalize(&cmd->pkt);
cmdq_pkt_eoc(&cmd->pkt);
cmdq_pkt_jump_rel(&cmd->pkt, CMDQ_INST_SIZE, mdp->cmdq_shift_pa[pp_idx]);
for (i = 0; i < num_comp; i++) {
s32 inner_id = MDP_COMP_NONE;
@ -699,6 +651,7 @@ static struct mdp_cmdq_cmd *mdp_cmdq_prepare(struct mdp_dev *mdp,
cmd->comps = comps;
cmd->num_comps = num_comp;
cmd->mdp_ctx = param->mdp_ctx;
cmd->pp_idx = pp_idx;
kfree(path);
return cmd;
@ -710,7 +663,7 @@ static struct mdp_cmdq_cmd *mdp_cmdq_prepare(struct mdp_dev *mdp,
err_free_comps:
kfree(comps);
err_destroy_pkt:
mdp_cmdq_pkt_destroy(&cmd->pkt);
cmdq_pkt_destroy(mdp->cmdq_clt[pp_idx], &cmd->pkt);
err_free_cmd:
kfree(cmd);
err_uninit:

1
drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.h
View File

@ -35,6 +35,7 @@ struct mdp_cmdq_cmd {
struct mdp_comp *comps;
void *mdp_ctx;
u8 num_comps;
u8 pp_idx;
};
struct mdp_dev;

537
drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c
View File

File diff suppressed because it is too large Load Diff

29
drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h
View File

@ -9,18 +9,18 @@
#include "mtk-mdp3-cmdq.h"
#define MM_REG_WRITE_MASK(cmd, id, base, ofst, val, mask, ...) \
cmdq_pkt_write_mask(&((cmd)->pkt), id, \
(base) + (ofst), (val), (mask), ##__VA_ARGS__)
#define MM_REG_WRITE(cmd, id, base, ofst, val, mask, ...) \
#define MM_REG_WRITE_MASK(cmd, id, base, ofst, val, mask) \
do { \
typeof(mask) (m) = (mask); \
MM_REG_WRITE_MASK(cmd, id, base, ofst, val, \
cmdq_pkt_write_mask(&((cmd)->pkt), id, (base) + (ofst), \
(val), \
(((m) & (ofst##_MASK)) == (ofst##_MASK)) ? \
(0xffffffff) : (m), ##__VA_ARGS__); \
(0xffffffff) : (m)); \
} while (0)
#define MM_REG_WRITE(cmd, id, base, ofst, val) \
cmdq_pkt_write(&((cmd)->pkt), id, (base) + (ofst), (val))
#define MM_REG_WAIT(cmd, evt) \
do { \
typeof(cmd) (c) = (cmd); \
@ -49,20 +49,17 @@ do { \
cmdq_pkt_set_event(&((c)->pkt), (e)); \
} while (0)
#define MM_REG_POLL_MASK(cmd, id, base, ofst, val, _mask, ...) \
#define MM_REG_POLL_MASK(cmd, id, base, ofst, val, _mask) \
do { \
typeof(_mask) (_m) = (_mask); \
cmdq_pkt_poll_mask(&((cmd)->pkt), id, \
(base) + (ofst), (val), (_m), ##__VA_ARGS__); \
(base) + (ofst), (val), \
(((_m) & (ofst##_MASK)) == (ofst##_MASK)) ? \
(0xffffffff) : (_m)); \
} while (0)
#define MM_REG_POLL(cmd, id, base, ofst, val, mask, ...) \
do { \
typeof(mask) (m) = (mask); \
MM_REG_POLL_MASK((cmd), id, base, ofst, val, \
(((m) & (ofst##_MASK)) == (ofst##_MASK)) ? \
(0xffffffff) : (m), ##__VA_ARGS__); \
} while (0)
#define MM_REG_POLL(cmd, id, base, ofst, val) \
cmdq_pkt_poll(&((cmd)->pkt), id, (base) + (ofst), (val))
enum mtk_mdp_comp_id {
MDP_COMP_NONE = -1, /* Invalid engine */

2
drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c
View File

@ -312,6 +312,8 @@ static int mdp_probe(struct platform_device *pdev)
ret = PTR_ERR(mdp->cmdq_clt[i]);
goto err_mbox_destroy;
}
mdp->cmdq_shift_pa[i] = cmdq_get_shift_pa(mdp->cmdq_clt[i]->chan);
}
init_waitqueue_head(&mdp->callback_wq);

1
drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
View File

@ -126,6 +126,7 @@ struct mdp_dev {
u32 id_count;
struct ida mdp_ida;
struct cmdq_client *cmdq_clt[MDP_PP_MAX];
u8 cmdq_shift_pa[MDP_PP_MAX];
wait_queue_head_t callback_wq;
struct v4l2_device v4l2_dev;

7
drivers/media/platform/nxp/imx-jpeg/mxc-jpeg.c
View File

@ -2677,11 +2677,12 @@ static void mxc_jpeg_detach_pm_domains(struct mxc_jpeg_dev *jpeg)
int i;
for (i = 0; i < jpeg->num_domains; i++) {
if (jpeg->pd_dev[i] && !pm_runtime_suspended(jpeg->pd_dev[i]))
if (!IS_ERR_OR_NULL(jpeg->pd_dev[i]) &&
!pm_runtime_suspended(jpeg->pd_dev[i]))
pm_runtime_force_suspend(jpeg->pd_dev[i]);
if (jpeg->pd_link[i] && !IS_ERR(jpeg->pd_link[i]))
if (!IS_ERR_OR_NULL(jpeg->pd_link[i]))
device_link_del(jpeg->pd_link[i]);
if (jpeg->pd_dev[i] && !IS_ERR(jpeg->pd_dev[i]))
if (!IS_ERR_OR_NULL(jpeg->pd_dev[i]))
dev_pm_domain_detach(jpeg->pd_dev[i], true);
jpeg->pd_dev[i] = NULL;
jpeg->pd_link[i] = NULL;

13
drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
View File

@ -505,9 +505,9 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
u32 val;
switch (csiphy->camss->res->version) {
case CAMSS_845:
r = &lane_regs_sdm845[0][0];
array_size = ARRAY_SIZE(lane_regs_sdm845[0]);
case CAMSS_7280:
r = &lane_regs_sm8250[0][0];
array_size = ARRAY_SIZE(lane_regs_sm8250[0]);
break;
case CAMSS_8250:
r = &lane_regs_sm8250[0][0];
@ -517,6 +517,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy,
r = &lane_regs_sc8280xp[0][0];
array_size = ARRAY_SIZE(lane_regs_sc8280xp[0]);
break;
case CAMSS_845:
r = &lane_regs_sdm845[0][0];
array_size = ARRAY_SIZE(lane_regs_sdm845[0]);
break;
default:
WARN(1, "unknown cspi version\n");
return;
@ -557,9 +561,10 @@ static bool csiphy_is_gen2(u32 version)
bool ret = false;
switch (version) {
case CAMSS_845:
case CAMSS_7280:
case CAMSS_8250:
case CAMSS_8280XP:
case CAMSS_845:
ret = true;
break;
}

5
drivers/media/platform/qcom/camss/camss-csiphy.c
View File

@ -103,6 +103,11 @@ const struct csiphy_formats csiphy_formats_8x96 = {
.formats = formats_8x96
};
const struct csiphy_formats csiphy_formats_sc7280 = {
.nformats = ARRAY_SIZE(formats_sdm845),
.formats = formats_sdm845
};
const struct csiphy_formats csiphy_formats_sdm845 = {
.nformats = ARRAY_SIZE(formats_sdm845),
.formats = formats_sdm845

7
drivers/media/platform/qcom/camss/camss-csiphy.h
View File

@ -26,6 +26,12 @@ struct csiphy_lane {
u8 pol;
};
/**
* struct csiphy_lanes_cfg - CSIPHY lanes configuration
* @num_data: number of data lanes
* @data: data lanes configuration
* @clk: clock lane configuration (only for D-PHY)
*/
struct csiphy_lanes_cfg {
int num_data;
struct csiphy_lane *data;
@ -111,6 +117,7 @@ void msm_csiphy_unregister_entity(struct csiphy_device *csiphy);
extern const struct csiphy_formats csiphy_formats_8x16;
extern const struct csiphy_formats csiphy_formats_8x96;
extern const struct csiphy_formats csiphy_formats_sc7280;
extern const struct csiphy_formats csiphy_formats_sdm845;
extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0;

8
drivers/media/platform/qcom/camss/camss-vfe.c
View File

@ -334,11 +334,12 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
return sink_code;
}
break;
case CAMSS_8x96:
case CAMSS_660:
case CAMSS_845:
case CAMSS_7280:
case CAMSS_8x96:
case CAMSS_8250:
case CAMSS_8280XP:
case CAMSS_845:
switch (sink_code) {
case MEDIA_BUS_FMT_YUYV8_1X16:
{
@ -1693,9 +1694,10 @@ static int vfe_bpl_align(struct vfe_device *vfe)
int ret = 8;
switch (vfe->camss->res->version) {
case CAMSS_845:
case CAMSS_7280:
case CAMSS_8250:
case CAMSS_8280XP:
case CAMSS_845:
ret = 16;
break;
default:

514
drivers/media/platform/qcom/camss/camss.c
View File

@ -1266,6 +1266,310 @@ static const struct resources_icc icc_res_sm8250[] = {
},
};
static const struct camss_subdev_resources csiphy_res_7280[] = {
/* CSIPHY0 */
{
.regulators = { "vdda-phy", "vdda-pll" },
.clock = { "csiphy0", "csiphy0_timer" },
.clock_rate = { { 300000000, 400000000 },
{ 300000000 } },
.reg = { "csiphy0" },
.interrupt = { "csiphy0" },
.csiphy = {
.hw_ops = &csiphy_ops_3ph_1_0,
.formats = &csiphy_formats_sc7280
}
},
/* CSIPHY1 */
{
.regulators = { "vdda-phy", "vdda-pll" },
.clock = { "csiphy1", "csiphy1_timer" },
.clock_rate = { { 300000000, 400000000 },
{ 300000000 } },
.reg = { "csiphy1" },
.interrupt = { "csiphy1" },
.csiphy = {
.hw_ops = &csiphy_ops_3ph_1_0,
.formats = &csiphy_formats_sc7280
}
},
/* CSIPHY2 */
{
.regulators = { "vdda-phy", "vdda-pll" },
.clock = { "csiphy2", "csiphy2_timer" },
.clock_rate = { { 300000000, 400000000 },
{ 300000000 } },
.reg = { "csiphy2" },
.interrupt = { "csiphy2" },
.csiphy = {
.hw_ops = &csiphy_ops_3ph_1_0,
.formats = &csiphy_formats_sc7280
}
},
/* CSIPHY3 */
{
.regulators = { "vdda-phy", "vdda-pll" },
.clock = { "csiphy3", "csiphy3_timer" },
.clock_rate = { { 300000000, 400000000 },
{ 300000000 } },
.reg = { "csiphy3" },
.interrupt = { "csiphy3" },
.csiphy = {
.hw_ops = &csiphy_ops_3ph_1_0,
.formats = &csiphy_formats_sc7280
}
},
/* CSIPHY4 */
{
.regulators = { "vdda-phy", "vdda-pll" },
.clock = { "csiphy4", "csiphy4_timer" },
.clock_rate = { { 300000000, 400000000 },
{ 300000000 } },
.reg = { "csiphy4" },
.interrupt = { "csiphy4" },
.csiphy = {
.hw_ops = &csiphy_ops_3ph_1_0,
.formats = &csiphy_formats_sc7280
}
},
};
static const struct camss_subdev_resources csid_res_7280[] = {
/* CSID0 */
{
.regulators = {},
.clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0" },
.clock_rate = { { 300000000, 400000000 },
{ 0 },
{ 380000000, 510000000, 637000000, 760000000 }
},
.reg = { "csid0" },
.interrupt = { "csid0" },
.csid = {
.is_lite = false,
.hw_ops = &csid_ops_gen2,
.parent_dev_ops = &vfe_parent_dev_ops,
.formats = &csid_formats_gen2
}
},
/* CSID1 */
{
.regulators = {},
.clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1" },
.clock_rate = { { 300000000, 400000000 },
{ 0 },
{ 380000000, 510000000, 637000000, 760000000 }
},
.reg = { "csid1" },
.interrupt = { "csid1" },
.csid = {
.is_lite = false,
.hw_ops = &csid_ops_gen2,
.parent_dev_ops = &vfe_parent_dev_ops,
.formats = &csid_formats_gen2
}
},
/* CSID2 */
{
.regulators = {},
.clock = { "vfe2_csid", "vfe2_cphy_rx", "vfe2" },
.clock_rate = { { 300000000, 400000000 },
{ 0 },
{ 380000000, 510000000, 637000000, 760000000 }
},
.reg = { "csid2" },
.interrupt = { "csid2" },
.csid = {
.is_lite = false,
.hw_ops = &csid_ops_gen2,
.parent_dev_ops = &vfe_parent_dev_ops,
.formats = &csid_formats_gen2
}
},
/* CSID3 */
{
.regulators = {},
.clock = { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" },
.clock_rate = { { 300000000, 400000000 },
{ 0 },
{ 320000000, 400000000, 480000000, 600000000 }
},
.reg = { "csid_lite0" },
.interrupt = { "csid_lite0" },
.csid = {
.is_lite = true,
.hw_ops = &csid_ops_gen2,
.parent_dev_ops = &vfe_parent_dev_ops,
.formats = &csid_formats_gen2
}
},
/* CSID4 */
{
.regulators = {},
.clock = { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" },
.clock_rate = { { 300000000, 400000000 },
{ 0 },
{ 320000000, 400000000, 480000000, 600000000 }
},
.reg = { "csid_lite1" },
.interrupt = { "csid_lite1" },
.csid = {
.is_lite = true,
.hw_ops = &csid_ops_gen2,
.parent_dev_ops = &vfe_parent_dev_ops,
.formats = &csid_formats_gen2
}
},
};
static const struct camss_subdev_resources vfe_res_7280[] = {
/* VFE0 */
{
.regulators = {},
.clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe0",
"vfe0_axi", "gcc_cam_hf_axi" },
.clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
{ 80000000 },
{ 0 },
{ 380000000, 510000000, 637000000, 760000000 },
{ 0 },
{ 0 } },
.reg = { "vfe0" },
.interrupt = { "vfe0" },
.vfe = {
.line_num = 3,
.is_lite = false,
.has_pd = true,
.pd_name = "ife0",
.hw_ops = &vfe_ops_170,
.formats_rdi = &vfe_formats_rdi_845,
.formats_pix = &vfe_formats_pix_845
}
},
/* VFE1 */
{
.regulators = {},
.clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe1",
"vfe1_axi", "gcc_cam_hf_axi" },
.clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
{ 80000000 },
{ 0 },
{ 380000000, 510000000, 637000000, 760000000 },
{ 0 },
{ 0 } },
.reg = { "vfe1" },
.interrupt = { "vfe1" },
.vfe = {
.line_num = 3,
.is_lite = false,
.has_pd = true,
.pd_name = "ife1",
.hw_ops = &vfe_ops_170,
.formats_rdi = &vfe_formats_rdi_845,
.formats_pix = &vfe_formats_pix_845
}
},
/* VFE2 */
{
.regulators = {},
.clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe2",
"vfe2_axi", "gcc_cam_hf_axi" },
.clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
{ 80000000 },
{ 0 },
{ 380000000, 510000000, 637000000, 760000000 },
{ 0 },
{ 0 } },
.reg = { "vfe2" },
.interrupt = { "vfe2" },
.vfe = {
.line_num = 3,
.is_lite = false,
.hw_ops = &vfe_ops_170,
.has_pd = true,
.pd_name = "ife2",
.formats_rdi = &vfe_formats_rdi_845,
.formats_pix = &vfe_formats_pix_845
}
},
/* VFE3 (lite) */
{
.clock = { "camnoc_axi", "cpas_ahb", "icp_ahb",
"vfe_lite0", "gcc_cam_hf_axi" },
.clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
{ 80000000 },
{ 0 },
{ 320000000, 400000000, 480000000, 600000000 },
{ 0 } },
.regulators = {},
.reg = { "vfe_lite0" },
.interrupt = { "vfe_lite0" },
.vfe = {
.line_num = 4,
.is_lite = true,
.hw_ops = &vfe_ops_170,
.formats_rdi = &vfe_formats_rdi_845,
.formats_pix = &vfe_formats_pix_845
}
},
/* VFE4 (lite) */
{
.clock = { "camnoc_axi", "cpas_ahb", "icp_ahb",
"vfe_lite1", "gcc_cam_hf_axi" },
.clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 },
{ 80000000 },
{ 0 },
{ 320000000, 400000000, 480000000, 600000000 },
{ 0 } },
.regulators = {},
.reg = { "vfe_lite1" },
.interrupt = { "vfe_lite1" },
.vfe = {
.line_num = 4,
.is_lite = true,
.hw_ops = &vfe_ops_170,
.formats_rdi = &vfe_formats_rdi_845,
.formats_pix = &vfe_formats_pix_845
}
},
};
static const struct resources_icc icc_res_sc7280[] = {
{
.name = "ahb",
.icc_bw_tbl.avg = 38400,
.icc_bw_tbl.peak = 76800,
},
{
.name = "hf_0",
.icc_bw_tbl.avg = 2097152,
.icc_bw_tbl.peak = 2097152,
},
};
static const struct camss_subdev_resources csiphy_res_sc8280xp[] = {
/* CSIPHY0 */
{
@ -1994,14 +2298,81 @@ static int camss_init_subdevices(struct camss *camss)
}
/*
* camss_link_entities - Register subdev nodes and create links
* camss_link_err - print error in case link creation fails
* @src_name: name for source of the link
* @sink_name: name for sink of the link
*/
inline void camss_link_err(struct camss *camss,
const char *src_name,
const char *sink_name,
int ret)
{
dev_err(camss->dev,
"Failed to link %s->%s entities: %d\n",
src_name,
sink_name,
ret);
}
/*
* camss_link_entities_csid - Register subdev nodes and create links
* @camss: CAMSS device
*
* Return 0 on success or a negative error code on failure
*/
static int camss_link_entities(struct camss *camss)
static int camss_link_entities_csid(struct camss *camss)
{
int i, j, k;
struct media_entity *src_entity;
struct media_entity *sink_entity;
int ret, line_num;
u16 sink_pad;
u16 src_pad;
int i, j;
for (i = 0; i < camss->res->csid_num; i++) {
if (camss->ispif)
line_num = camss->ispif->line_num;
else
line_num = camss->vfe[i].res->line_num;
src_entity = &camss->csid[i].subdev.entity;
for (j = 0; j < line_num; j++) {
if (camss->ispif) {
sink_entity = &camss->ispif->line[j].subdev.entity;
src_pad = MSM_CSID_PAD_SRC;
sink_pad = MSM_ISPIF_PAD_SINK;
} else {
sink_entity = &camss->vfe[i].line[j].subdev.entity;
src_pad = MSM_CSID_PAD_FIRST_SRC + j;
sink_pad = MSM_VFE_PAD_SINK;
}
ret = media_create_pad_link(src_entity,
src_pad,
sink_entity,
sink_pad,
0);
if (ret < 0) {
camss_link_err(camss, src_entity->name,
sink_entity->name,
ret);
return ret;
}
}
}
return 0;
}
/*
* camss_link_entities_csiphy - Register subdev nodes and create links
* @camss: CAMSS device
*
* Return 0 on success or a negative error code on failure
*/
static int camss_link_entities_csiphy(struct camss *camss)
{
int i, j;
int ret;
for (i = 0; i < camss->res->csiphy_num; i++) {
@ -2012,81 +2383,77 @@ static int camss_link_entities(struct camss *camss)
MSM_CSID_PAD_SINK,
0);
if (ret < 0) {
dev_err(camss->dev,
"Failed to link %s->%s entities: %d\n",
camss->csiphy[i].subdev.entity.name,
camss->csid[j].subdev.entity.name,
ret);
camss_link_err(camss,
camss->csiphy[i].subdev.entity.name,
camss->csid[j].subdev.entity.name,
ret);
return ret;
}
}
}
if (camss->ispif) {
for (i = 0; i < camss->res->csid_num; i++) {
for (j = 0; j < camss->ispif->line_num; j++) {
ret = media_create_pad_link(&camss->csid[i].subdev.entity,
MSM_CSID_PAD_SRC,
&camss->ispif->line[j].subdev.entity,
MSM_ISPIF_PAD_SINK,
return 0;
}
/*
* camss_link_entities_ispif - Register subdev nodes and create links
* @camss: CAMSS device
*
* Return 0 on success or a negative error code on failure
*/
static int camss_link_entities_ispif(struct camss *camss)
{
int i, j, k;
int ret;
for (i = 0; i < camss->ispif->line_num; i++) {
for (k = 0; k < camss->res->vfe_num; k++) {
for (j = 0; j < camss->vfe[k].res->line_num; j++) {
struct v4l2_subdev *ispif = &camss->ispif->line[i].subdev;
struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev;
ret = media_create_pad_link(&ispif->entity,
MSM_ISPIF_PAD_SRC,
&vfe->entity,
MSM_VFE_PAD_SINK,
0);
if (ret < 0) {
dev_err(camss->dev,
"Failed to link %s->%s entities: %d\n",
camss->csid[i].subdev.entity.name,
camss->ispif->line[j].subdev.entity.name,
ret);
camss_link_err(camss, ispif->entity.name,
vfe->entity.name,
ret);
return ret;
}
}
}
for (i = 0; i < camss->ispif->line_num; i++)
for (k = 0; k < camss->res->vfe_num; k++)
for (j = 0; j < camss->vfe[k].res->line_num; j++) {
struct v4l2_subdev *ispif = &camss->ispif->line[i].subdev;
struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev;
ret = media_create_pad_link(&ispif->entity,
MSM_ISPIF_PAD_SRC,
&vfe->entity,
MSM_VFE_PAD_SINK,
0);
if (ret < 0) {
dev_err(camss->dev,
"Failed to link %s->%s entities: %d\n",
ispif->entity.name,
vfe->entity.name,
ret);
return ret;
}
}
} else {
for (i = 0; i < camss->res->csid_num; i++)
for (k = 0; k < camss->res->vfe_num; k++)
for (j = 0; j < camss->vfe[k].res->line_num; j++) {
struct v4l2_subdev *csid = &camss->csid[i].subdev;
struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev;
ret = media_create_pad_link(&csid->entity,
MSM_CSID_PAD_FIRST_SRC + j,
&vfe->entity,
MSM_VFE_PAD_SINK,
0);
if (ret < 0) {
dev_err(camss->dev,
"Failed to link %s->%s entities: %d\n",
csid->entity.name,
vfe->entity.name,
ret);
return ret;
}
}
}
return 0;
}
/*
* camss_link_entities - Register subdev nodes and create links
* @camss: CAMSS device
*
* Return 0 on success or a negative error code on failure
*/
static int camss_link_entities(struct camss *camss)
{
int ret;
ret = camss_link_entities_csiphy(camss);
if (ret < 0)
return ret;
ret = camss_link_entities_csid(camss);
if (ret < 0)
return ret;
if (camss->ispif)
ret = camss_link_entities_ispif(camss);
return ret;
}
/*
* camss_register_entities - Register subdev nodes and create links
* @camss: CAMSS device
@ -2227,9 +2594,9 @@ static int camss_subdev_notifier_complete(struct v4l2_async_notifier *async)
input, MSM_CSIPHY_PAD_SINK,
MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
if (ret < 0) {
dev_err(camss->dev,
"Failed to link %s->%s entities: %d\n",
sensor->name, input->name, ret);
camss_link_err(camss, sensor->name,
input->name,
ret);
return ret;
}
}
@ -2622,14 +2989,29 @@ static const struct camss_resources sc8280xp_resources = {
.link_entities = camss_link_entities
};
static const struct camss_resources sc7280_resources = {
.version = CAMSS_7280,
.pd_name = "top",
.csiphy_res = csiphy_res_7280,
.csid_res = csid_res_7280,
.vfe_res = vfe_res_7280,
.icc_res = icc_res_sc7280,
.icc_path_num = ARRAY_SIZE(icc_res_sc7280),
.csiphy_num = ARRAY_SIZE(csiphy_res_7280),
.csid_num = ARRAY_SIZE(csid_res_7280),
.vfe_num = ARRAY_SIZE(vfe_res_7280),
.link_entities = camss_link_entities
};
static const struct of_device_id camss_dt_match[] = {
{ .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
{ .compatible = "qcom,msm8953-camss", .data = &msm8953_resources },
{ .compatible = "qcom,msm8996-camss", .data = &msm8996_resources },
{ .compatible = "qcom,sc7280-camss", .data = &sc7280_resources },
{ .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
{ .compatible = "qcom,sdm660-camss", .data = &sdm660_resources },
{ .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
{ .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
{ .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources },
{ }
};

5
drivers/media/platform/qcom/camss/camss.h
View File

@ -77,13 +77,14 @@ enum pm_domain {
};
enum camss_version {
CAMSS_660,
CAMSS_7280,
CAMSS_8x16,
CAMSS_8x53,
CAMSS_8x96,
CAMSS_660,
CAMSS_845,
CAMSS_8250,
CAMSS_8280XP,
CAMSS_845,
};
enum icc_count {

91
drivers/media/platform/renesas/rcar-csi2.c
View File

@ -183,17 +183,19 @@ struct rcar_csi2;
#define V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(n) (0x23840 + ((n) * 2)) /* n = 0 - 11 */
#define V4H_CORE_DIG_RW_COMMON_REG(n) (0x23880 + ((n) * 2)) /* n = 0 - 15 */
#define V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(n) (0x239e0 + ((n) * 2)) /* n = 0 - 3 */
#define V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG 0x2a400
#define V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG 0x2a60c
/* V4H C-PHY */
#define V4H_CORE_DIG_RW_TRIO0_REG(n) (0x22100 + ((n) * 2)) /* n = 0 - 3 */
#define V4H_CORE_DIG_RW_TRIO1_REG(n) (0x22500 + ((n) * 2)) /* n = 0 - 3 */
#define V4H_CORE_DIG_RW_TRIO2_REG(n) (0x22900 + ((n) * 2)) /* n = 0 - 3 */
#define V4H_CORE_DIG_CLANE_0_RW_CFG_0_REG 0x2a000
#define V4H_CORE_DIG_CLANE_0_RW_LP_0_REG 0x2a080
#define V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(n) (0x2a100 + ((n) * 2)) /* n = 0 - 6 */
#define V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG 0x2a400
#define V4H_CORE_DIG_CLANE_1_RW_LP_0_REG 0x2a480
#define V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(n) (0x2a500 + ((n) * 2)) /* n = 0 - 6 */
#define V4H_CORE_DIG_CLANE_2_RW_CFG_0_REG 0x2a800
#define V4H_CORE_DIG_CLANE_2_RW_LP_0_REG 0x2a880
#define V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(n) (0x2a900 + ((n) * 2)) /* n = 0 - 6 */
@ -672,6 +674,21 @@ static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code)
return NULL;
}
struct rcsi2_cphy_line_order {
enum v4l2_mbus_csi2_cphy_line_orders_type order;
u16 cfg;
u16 ctrl29;
};
static const struct rcsi2_cphy_line_order rcsi2_cphy_line_orders[] = {
{ .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_ABC, .cfg = 0x0, .ctrl29 = 0x0 },
{ .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_ACB, .cfg = 0xa, .ctrl29 = 0x1 },
{ .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_BAC, .cfg = 0xc, .ctrl29 = 0x1 },
{ .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_BCA, .cfg = 0x5, .ctrl29 = 0x0 },
{ .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_CAB, .cfg = 0x3, .ctrl29 = 0x0 },
{ .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_CBA, .cfg = 0x9, .ctrl29 = 0x1 }
};
enum rcar_csi2_pads {
RCAR_CSI2_SINK,
RCAR_CSI2_SOURCE_VC0,
@ -722,6 +739,7 @@ struct rcar_csi2 {
bool cphy;
unsigned short lanes;
unsigned char lane_swap[4];
enum v4l2_mbus_csi2_cphy_line_orders_type line_orders[3];
};
static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd)
@ -754,11 +772,24 @@ static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data)
iowrite32(data, priv->base + reg);
}
static u16 rcsi2_read16(struct rcar_csi2 *priv, unsigned int reg)
{
return ioread16(priv->base + reg);
}
static void rcsi2_write16(struct rcar_csi2 *priv, unsigned int reg, u16 data)
{
iowrite16(data, priv->base + reg);
}
static void rcsi2_modify16(struct rcar_csi2 *priv, unsigned int reg, u16 data, u16 mask)
{
u16 val;
val = rcsi2_read16(priv, reg) & ~mask;
rcsi2_write16(priv, reg, val | data);
}
static int rcsi2_phtw_write(struct rcar_csi2 *priv, u8 data, u8 code)
{
unsigned int timeout;
@ -1112,6 +1143,26 @@ static int rcsi2_start_receiver_gen3(struct rcar_csi2 *priv,
return 0;
}
static void rsci2_set_line_order(struct rcar_csi2 *priv,
enum v4l2_mbus_csi2_cphy_line_orders_type order,
unsigned int cfgreg, unsigned int ctrlreg)
{
const struct rcsi2_cphy_line_order *info = NULL;
for (unsigned int i = 0; i < ARRAY_SIZE(rcsi2_cphy_line_orders); i++) {
if (rcsi2_cphy_line_orders[i].order == order) {
info = &rcsi2_cphy_line_orders[i];
break;
}
}
if (!info)
return;
rcsi2_modify16(priv, cfgreg, info->cfg, 0x000f);
rcsi2_modify16(priv, ctrlreg, info->ctrl29, 0x0100);
}
static int rcsi2_wait_phy_start_v4h(struct rcar_csi2 *priv, u32 match)
{
unsigned int timeout;
@ -1189,12 +1240,18 @@ static int rcsi2_c_phy_setting_v4h(struct rcar_csi2 *priv, int msps)
rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(1), conf->trio1);
rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(1), conf->trio1);
/*
* Configure pin-swap.
* TODO: This registers is not documented yet, the values should depend
* on the 'clock-lanes' and 'data-lanes' devicetree properties.
*/
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG, 0xf5);
/* Configure data line order. */
rsci2_set_line_order(priv, priv->line_orders[0],
V4H_CORE_DIG_CLANE_0_RW_CFG_0_REG,
V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(9));
rsci2_set_line_order(priv, priv->line_orders[1],
V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG,
V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(9));
rsci2_set_line_order(priv, priv->line_orders[2],
V4H_CORE_DIG_CLANE_2_RW_CFG_0_REG,
V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(9));
/* TODO: This registers is not documented. */
rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG, 0x5000);
/* Leave Shutdown mode */
@ -1349,15 +1406,15 @@ static int rcsi2_init_common_v4m(struct rcar_csi2 *priv, unsigned int mbps)
static const struct phtw_value step2[] = {
{ .data = 0x00, .code = 0x00 },
{ .data = 0x80, .code = 0xe0 },
{ .data = 0x01, .code = 0xe1 },
{ .data = 0x31, .code = 0xe1 },
{ .data = 0x06, .code = 0x00 },
{ .data = 0x0f, .code = 0x11 },
{ .data = 0x11, .code = 0x11 },
{ .data = 0x08, .code = 0x00 },
{ .data = 0x0f, .code = 0x11 },
{ .data = 0x11, .code = 0x11 },
{ .data = 0x0a, .code = 0x00 },
{ .data = 0x0f, .code = 0x11 },
{ .data = 0x11, .code = 0x11 },
{ .data = 0x0c, .code = 0x00 },
{ .data = 0x0f, .code = 0x11 },
{ .data = 0x11, .code = 0x11 },
{ .data = 0x01, .code = 0x00 },
{ .data = 0x31, .code = 0xaa },
{ .data = 0x05, .code = 0x00 },
@ -1370,6 +1427,11 @@ static int rcsi2_init_common_v4m(struct rcar_csi2 *priv, unsigned int mbps)
{ .data = 0x05, .code = 0x09 },
};
static const struct phtw_value step3[] = {
{ .data = 0x01, .code = 0x00 },
{ .data = 0x06, .code = 0xab },
};
if (priv->info->hsfreqrange) {
ret = rcsi2_set_phypll(priv, mbps);
if (ret)
@ -1400,7 +1462,7 @@ static int rcsi2_init_common_v4m(struct rcar_csi2 *priv, unsigned int mbps)
return ret;
}
return ret;
return rcsi2_phtw_write_array(priv, step3, ARRAY_SIZE(step3));
}
static int rcsi2_start_receiver_v4m(struct rcar_csi2 *priv,
@ -1732,6 +1794,9 @@ static int rcsi2_parse_v4l2(struct rcar_csi2 *priv,
}
}
for (i = 0; i < ARRAY_SIZE(priv->line_orders); i++)
priv->line_orders[i] = vep->bus.mipi_csi2.line_orders[i];
return 0;
}

2
drivers/media/platform/rockchip/rga/rga-buf.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2017 Fuzhou Rockchip Electronics Co.Ltd
* Copyright (C) 2017 Rockchip Electronics Co., Ltd.
* Author: Jacob Chen <jacob-chen@iotwrt.com>
*/

2
drivers/media/platform/rockchip/rga/rga-hw.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
* Copyright (C) Rockchip Electronics Co., Ltd.
* Author: Jacob Chen <jacob-chen@iotwrt.com>
*/

2
drivers/media/platform/rockchip/rga/rga-hw.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
* Copyright (C) Rockchip Electronics Co., Ltd.
* Author: Jacob Chen <jacob-chen@iotwrt.com>
*/
#ifndef __RGA_HW_H__

2
drivers/media/platform/rockchip/rga/rga.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
* Copyright (C) Rockchip Electronics Co., Ltd.
* Author: Jacob Chen <jacob-chen@iotwrt.com>
*/

2
drivers/media/platform/rockchip/rga/rga.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
* Copyright (C) Rockchip Electronics Co., Ltd.
* Author: Jacob Chen <jacob-chen@iotwrt.com>
*/
#ifndef __RGA_H__

4
drivers/media/platform/rockchip/rkisp1/rkisp1-capture.c
View File

@ -35,8 +35,6 @@
#define RKISP1_SP_DEV_NAME RKISP1_DRIVER_NAME "_selfpath"
#define RKISP1_MP_DEV_NAME RKISP1_DRIVER_NAME "_mainpath"
#define RKISP1_MIN_BUFFERS_NEEDED 3
enum rkisp1_plane {
RKISP1_PLANE_Y = 0,
RKISP1_PLANE_CB = 1,
@ -1561,7 +1559,7 @@ static int rkisp1_register_capture(struct rkisp1_capture *cap)
q->ops = &rkisp1_vb2_ops;
q->mem_ops = &vb2_dma_contig_memops;
q->buf_struct_size = sizeof(struct rkisp1_buffer);
q->min_queued_buffers = RKISP1_MIN_BUFFERS_NEEDED;
q->min_queued_buffers = 1;
q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
q->lock = &node->vlock;
q->dev = cap->rkisp1->dev;

3
drivers/media/platform/rockchip/rkisp1/rkisp1-dev.c
View File

@ -228,6 +228,9 @@ static int rkisp1_subdev_notifier_register(struct rkisp1_device *rkisp1)
break;
}
if (ret)
break;
/* Parse the endpoint and validate the bus type. */
ret = v4l2_fwnode_endpoint_parse(ep, &vep);
if (ret) {

131
drivers/media/platform/samsung/exynos4-is/fimc-is-errno.c
View File

@ -12,137 +12,6 @@
#include "fimc-is-errno.h"
const char *fimc_is_param_strerr(unsigned int error)
{
switch (error) {
case ERROR_COMMON_CMD:
return "ERROR_COMMON_CMD: Invalid Command";
case ERROR_COMMON_PARAMETER:
return "ERROR_COMMON_PARAMETER: Invalid Parameter";
case ERROR_COMMON_SETFILE_LOAD:
return "ERROR_COMMON_SETFILE_LOAD: Illegal Setfile Loading";
case ERROR_COMMON_SETFILE_ADJUST:
return "ERROR_COMMON_SETFILE_ADJUST: Setfile isn't adjusted";
case ERROR_COMMON_SETFILE_INDEX:
return "ERROR_COMMON_SETFILE_INDEX: Invalid setfile index";
case ERROR_COMMON_INPUT_PATH:
return "ERROR_COMMON_INPUT_PATH: Input path can be changed in ready state";
case ERROR_COMMON_INPUT_INIT:
return "ERROR_COMMON_INPUT_INIT: IP can not start if input path is not set";
case ERROR_COMMON_OUTPUT_PATH:
return "ERROR_COMMON_OUTPUT_PATH: Output path can be changed in ready state (stop)";
case ERROR_COMMON_OUTPUT_INIT:
return "ERROR_COMMON_OUTPUT_INIT: IP can not start if output path is not set";
case ERROR_CONTROL_BYPASS:
return "ERROR_CONTROL_BYPASS";
case ERROR_OTF_INPUT_FORMAT:
return "ERROR_OTF_INPUT_FORMAT: Invalid format (DRC: YUV444, FD: YUV444, 422, 420)";
case ERROR_OTF_INPUT_WIDTH:
return "ERROR_OTF_INPUT_WIDTH: Invalid width (DRC: 128~8192, FD: 32~8190)";
case ERROR_OTF_INPUT_HEIGHT:
return "ERROR_OTF_INPUT_HEIGHT: Invalid bit-width (DRC: 8~12bits, FD: 8bit)";
case ERROR_OTF_INPUT_BIT_WIDTH:
return "ERROR_OTF_INPUT_BIT_WIDTH: Invalid bit-width (DRC: 8~12bits, FD: 8bit)";
case ERROR_DMA_INPUT_WIDTH:
return "ERROR_DMA_INPUT_WIDTH: Invalid width (DRC: 128~8192, FD: 32~8190)";
case ERROR_DMA_INPUT_HEIGHT:
return "ERROR_DMA_INPUT_HEIGHT: Invalid height (DRC: 64~8192, FD: 16~8190)";
case ERROR_DMA_INPUT_FORMAT:
return "ERROR_DMA_INPUT_FORMAT: Invalid format (DRC: YUV444 or YUV422, FD: YUV444,422,420)";
case ERROR_DMA_INPUT_BIT_WIDTH:
return "ERROR_DMA_INPUT_BIT_WIDTH: Invalid bit-width (DRC: 8~12bits, FD: 8bit)";
case ERROR_DMA_INPUT_ORDER:
return "ERROR_DMA_INPUT_ORDER: Invalid order(DRC: YYCbCr,YCbYCr,FD:NO,YYCbCr,YCbYCr,CbCr,CrCb)";
case ERROR_DMA_INPUT_PLANE:
return "ERROR_DMA_INPUT_PLANE: Invalid plane (DRC: 3, FD: 1, 2, 3)";
case ERROR_OTF_OUTPUT_WIDTH:
return "ERROR_OTF_OUTPUT_WIDTH: Invalid width (DRC: 128~8192)";
case ERROR_OTF_OUTPUT_HEIGHT:
return "ERROR_OTF_OUTPUT_HEIGHT: Invalid height (DRC: 64~8192)";
case ERROR_OTF_OUTPUT_FORMAT:
return "ERROR_OTF_OUTPUT_FORMAT: Invalid format (DRC: YUV444)";
case ERROR_OTF_OUTPUT_BIT_WIDTH:
return "ERROR_OTF_OUTPUT_BIT_WIDTH: Invalid bit-width (DRC: 8~12bits, FD: 8bit)";
case ERROR_DMA_OUTPUT_WIDTH:
return "ERROR_DMA_OUTPUT_WIDTH";
case ERROR_DMA_OUTPUT_HEIGHT:
return "ERROR_DMA_OUTPUT_HEIGHT";
case ERROR_DMA_OUTPUT_FORMAT:
return "ERROR_DMA_OUTPUT_FORMAT";
case ERROR_DMA_OUTPUT_BIT_WIDTH:
return "ERROR_DMA_OUTPUT_BIT_WIDTH";
case ERROR_DMA_OUTPUT_PLANE:
return "ERROR_DMA_OUTPUT_PLANE";
case ERROR_DMA_OUTPUT_ORDER:
return "ERROR_DMA_OUTPUT_ORDER";
/* Sensor Error(100~199) */
case ERROR_SENSOR_I2C_FAIL:
return "ERROR_SENSOR_I2C_FAIL";
case ERROR_SENSOR_INVALID_FRAMERATE:
return "ERROR_SENSOR_INVALID_FRAMERATE";
case ERROR_SENSOR_INVALID_EXPOSURETIME:
return "ERROR_SENSOR_INVALID_EXPOSURETIME";
case ERROR_SENSOR_INVALID_SIZE:
return "ERROR_SENSOR_INVALID_SIZE";
case ERROR_SENSOR_INVALID_SETTING:
return "ERROR_SENSOR_INVALID_SETTING";
case ERROR_SENSOR_ACTUATOR_INIT_FAIL:
return "ERROR_SENSOR_ACTUATOR_INIT_FAIL";
case ERROR_SENSOR_INVALID_AF_POS:
return "ERROR_SENSOR_INVALID_AF_POS";
case ERROR_SENSOR_UNSUPPORT_FUNC:
return "ERROR_SENSOR_UNSUPPORT_FUNC";
case ERROR_SENSOR_UNSUPPORT_PERI:
return "ERROR_SENSOR_UNSUPPORT_PERI";
case ERROR_SENSOR_UNSUPPORT_AF:
return "ERROR_SENSOR_UNSUPPORT_AF";
/* ISP Error (200~299) */
case ERROR_ISP_AF_BUSY:
return "ERROR_ISP_AF_BUSY";
case ERROR_ISP_AF_INVALID_COMMAND:
return "ERROR_ISP_AF_INVALID_COMMAND";
case ERROR_ISP_AF_INVALID_MODE:
return "ERROR_ISP_AF_INVALID_MODE";
/* DRC Error (300~399) */
/* FD Error (400~499) */
case ERROR_FD_CONFIG_MAX_NUMBER_STATE:
return "ERROR_FD_CONFIG_MAX_NUMBER_STATE";
case ERROR_FD_CONFIG_MAX_NUMBER_INVALID:
return "ERROR_FD_CONFIG_MAX_NUMBER_INVALID";
case ERROR_FD_CONFIG_YAW_ANGLE_STATE:
return "ERROR_FD_CONFIG_YAW_ANGLE_STATE";
case ERROR_FD_CONFIG_YAW_ANGLE_INVALID:
return "ERROR_FD_CONFIG_YAW_ANGLE_INVALID\n";
case ERROR_FD_CONFIG_ROLL_ANGLE_STATE:
return "ERROR_FD_CONFIG_ROLL_ANGLE_STATE";
case ERROR_FD_CONFIG_ROLL_ANGLE_INVALID:
return "ERROR_FD_CONFIG_ROLL_ANGLE_INVALID";
case ERROR_FD_CONFIG_SMILE_MODE_INVALID:
return "ERROR_FD_CONFIG_SMILE_MODE_INVALID";
case ERROR_FD_CONFIG_BLINK_MODE_INVALID:
return "ERROR_FD_CONFIG_BLINK_MODE_INVALID";
case ERROR_FD_CONFIG_EYES_DETECT_INVALID:
return "ERROR_FD_CONFIG_EYES_DETECT_INVALID";
case ERROR_FD_CONFIG_MOUTH_DETECT_INVALID:
return "ERROR_FD_CONFIG_MOUTH_DETECT_INVALID";
case ERROR_FD_CONFIG_ORIENTATION_STATE:
return "ERROR_FD_CONFIG_ORIENTATION_STATE";
case ERROR_FD_CONFIG_ORIENTATION_INVALID:
return "ERROR_FD_CONFIG_ORIENTATION_INVALID";
case ERROR_FD_CONFIG_ORIENTATION_VALUE_INVALID:
return "ERROR_FD_CONFIG_ORIENTATION_VALUE_INVALID";
case ERROR_FD_RESULT:
return "ERROR_FD_RESULT";
case ERROR_FD_MODE:
return "ERROR_FD_MODE";
default:
return "Unknown";
}
}
const char *fimc_is_strerr(unsigned int error)
{
error &= ~IS_ERROR_TIME_OUT_FLAG;

1
drivers/media/platform/samsung/exynos4-is/fimc-is-errno.h
View File

@ -240,6 +240,5 @@ enum fimc_is_error {
};
const char *fimc_is_strerr(unsigned int error);
const char *fimc_is_param_strerr(unsigned int error);
#endif /* FIMC_IS_ERR_H_ */

10
drivers/media/platform/samsung/exynos4-is/mipi-csis.c
View File

@ -940,13 +940,19 @@ static int s5pcsis_pm_resume(struct device *dev, bool runtime)
state->supplies);
goto unlock;
}
clk_enable(state->clock[CSIS_CLK_GATE]);
ret = clk_enable(state->clock[CSIS_CLK_GATE]);
if (ret) {
phy_power_off(state->phy);
regulator_bulk_disable(CSIS_NUM_SUPPLIES,
state->supplies);
goto unlock;
}
}
if (state->flags & ST_STREAMING)
s5pcsis_start_stream(state);
state->flags &= ~ST_SUSPENDED;
unlock:
unlock:
mutex_unlock(&state->lock);
return ret ? -EAGAIN : 0;
}

13
drivers/media/platform/samsung/s3c-camif/camif-core.c
View File

@ -527,10 +527,19 @@ static void s3c_camif_remove(struct platform_device *pdev)
static int s3c_camif_runtime_resume(struct device *dev)
{
struct camif_dev *camif = dev_get_drvdata(dev);
int ret;
ret = clk_enable(camif->clock[CLK_GATE]);
if (ret)
return ret;
clk_enable(camif->clock[CLK_GATE]);
/* null op on s3c244x */
clk_enable(camif->clock[CLK_CAM]);
ret = clk_enable(camif->clock[CLK_CAM]);
if (ret) {
clk_disable(camif->clock[CLK_GATE]);
return ret;
}
return 0;
}

7
drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c
View File

@ -774,8 +774,10 @@ static int s5p_mfc_open(struct file *file)
int ret = 0;
mfc_debug_enter();
if (mutex_lock_interruptible(&dev->mfc_mutex))
return -ERESTARTSYS;
if (mutex_lock_interruptible(&dev->mfc_mutex)) {
ret = -ERESTARTSYS;
goto err_enter;
}
dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
/* Allocate memory for context */
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
@ -946,6 +948,7 @@ static int s5p_mfc_open(struct file *file)
err_alloc:
dev->num_inst--;
mutex_unlock(&dev->mfc_mutex);
err_enter:
mfc_debug_leave();
return ret;
}

14
drivers/media/platform/st/stm32/Kconfig
View File

@ -1,6 +1,20 @@
# SPDX-License-Identifier: GPL-2.0-only
# V4L drivers
config VIDEO_STM32_CSI
tristate "STM32 Camera Serial Interface (CSI) support"
depends on V4L_PLATFORM_DRIVERS
depends on VIDEO_DEV && OF
depends on ARCH_STM32 || COMPILE_TEST
select MEDIA_CONTROLLER
select V4L2_FWNODE
help
This module makes the STM32 Camera Serial Interface (CSI)
available as a v4l2 device.
To compile this driver as a module, choose M here: the module
will be called stm32-csi.
config VIDEO_STM32_DCMI
tristate "STM32 Digital Camera Memory Interface (DCMI) support"
depends on V4L_PLATFORM_DRIVERS

1
drivers/media/platform/st/stm32/Makefile
View File

@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_VIDEO_STM32_CSI) += stm32-csi.o
obj-$(CONFIG_VIDEO_STM32_DCMI) += stm32-dcmi.o
obj-$(CONFIG_VIDEO_STM32_DCMIPP) += stm32-dcmipp/
stm32-dma2d-objs := dma2d/dma2d.o dma2d/dma2d-hw.o

1137
drivers/media/platform/st/stm32/stm32-csi.c Normal file
View File

File diff suppressed because it is too large Load Diff

2
drivers/media/platform/st/stm32/stm32-dcmipp/Makefile
View File

@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
stm32-dcmipp-y := dcmipp-core.o dcmipp-common.o dcmipp-parallel.o dcmipp-byteproc.o dcmipp-bytecap.o
stm32-dcmipp-y := dcmipp-core.o dcmipp-common.o dcmipp-input.o dcmipp-byteproc.o dcmipp-bytecap.o
obj-$(CONFIG_VIDEO_STM32_DCMIPP) += stm32-dcmipp.o

128
drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-bytecap.c
View File

@ -56,15 +56,32 @@ struct dcmipp_bytecap_pix_map {
static const struct dcmipp_bytecap_pix_map dcmipp_bytecap_pix_map_list[] = {
PIXMAP_MBUS_PFMT(RGB565_2X8_LE, RGB565),
PIXMAP_MBUS_PFMT(RGB565_1X16, RGB565),
PIXMAP_MBUS_PFMT(YUYV8_2X8, YUYV),
PIXMAP_MBUS_PFMT(YUYV8_1X16, YUYV),
PIXMAP_MBUS_PFMT(YVYU8_2X8, YVYU),
PIXMAP_MBUS_PFMT(YVYU8_1X16, YVYU),
PIXMAP_MBUS_PFMT(UYVY8_2X8, UYVY),
PIXMAP_MBUS_PFMT(UYVY8_1X16, UYVY),
PIXMAP_MBUS_PFMT(VYUY8_2X8, VYUY),
PIXMAP_MBUS_PFMT(VYUY8_1X16, VYUY),
PIXMAP_MBUS_PFMT(Y8_1X8, GREY),
PIXMAP_MBUS_PFMT(SBGGR8_1X8, SBGGR8),
PIXMAP_MBUS_PFMT(SGBRG8_1X8, SGBRG8),
PIXMAP_MBUS_PFMT(SGRBG8_1X8, SGRBG8),
PIXMAP_MBUS_PFMT(SRGGB8_1X8, SRGGB8),
PIXMAP_MBUS_PFMT(SBGGR10_1X10, SBGGR10),
PIXMAP_MBUS_PFMT(SGBRG10_1X10, SGBRG10),
PIXMAP_MBUS_PFMT(SGRBG10_1X10, SGRBG10),
PIXMAP_MBUS_PFMT(SRGGB10_1X10, SRGGB10),
PIXMAP_MBUS_PFMT(SBGGR12_1X12, SBGGR12),
PIXMAP_MBUS_PFMT(SGBRG12_1X12, SGBRG12),
PIXMAP_MBUS_PFMT(SGRBG12_1X12, SGRBG12),
PIXMAP_MBUS_PFMT(SRGGB12_1X12, SRGGB12),
PIXMAP_MBUS_PFMT(SBGGR14_1X14, SBGGR14),
PIXMAP_MBUS_PFMT(SGBRG14_1X14, SGBRG14),
PIXMAP_MBUS_PFMT(SGRBG14_1X14, SGRBG14),
PIXMAP_MBUS_PFMT(SRGGB14_1X14, SRGGB14),
PIXMAP_MBUS_PFMT(JPEG_1X8, JPEG),
};
@ -112,6 +129,7 @@ struct dcmipp_bytecap_device {
u32 sequence;
struct media_pipeline pipe;
struct v4l2_subdev *s_subdev;
u32 s_subdev_pad_nb;
enum dcmipp_state state;
@ -250,34 +268,34 @@ static int dcmipp_bytecap_enum_fmt_vid_cap(struct file *file, void *priv,
{
const struct dcmipp_bytecap_pix_map *vpix;
unsigned int index = f->index;
unsigned int i;
unsigned int i, prev_pixelformat = 0;
if (f->mbus_code) {
/*
* If a media bus code is specified, only enumerate formats
* compatible with it.
*/
for (i = 0; i < ARRAY_SIZE(dcmipp_bytecap_pix_map_list); i++) {
vpix = &dcmipp_bytecap_pix_map_list[i];
if (vpix->code != f->mbus_code)
continue;
/*
* List up all formats (or only ones matching f->mbus_code), taking
* care of removing duplicated entries (due to support of both
* parallel & csi 16 bits formats
*/
for (i = 0; i < ARRAY_SIZE(dcmipp_bytecap_pix_map_list); i++) {
vpix = &dcmipp_bytecap_pix_map_list[i];
/* Skip formats not matching requested mbus code */
if (f->mbus_code && vpix->code != f->mbus_code)
continue;
if (index == 0)
break;
/* Skip duplicated pixelformat */
if (vpix->pixelformat == prev_pixelformat)
continue;
index--;
}
prev_pixelformat = vpix->pixelformat;
if (i == ARRAY_SIZE(dcmipp_bytecap_pix_map_list))
return -EINVAL;
} else {
/* Otherwise, enumerate all formats. */
if (f->index >= ARRAY_SIZE(dcmipp_bytecap_pix_map_list))
return -EINVAL;
if (index == 0)
break;
vpix = &dcmipp_bytecap_pix_map_list[f->index];
index--;
}
if (i == ARRAY_SIZE(dcmipp_bytecap_pix_map_list))
return -EINVAL;
f->pixelformat = vpix->pixelformat;
return 0;
@ -337,33 +355,6 @@ static const struct v4l2_ioctl_ops dcmipp_bytecap_ioctl_ops = {
.vidioc_streamoff = vb2_ioctl_streamoff,
};
static int dcmipp_pipeline_s_stream(struct dcmipp_bytecap_device *vcap,
int state)
{
struct media_pad *pad;
int ret;
/*
* Get source subdev - since link is IMMUTABLE, pointer is cached
* within the dcmipp_bytecap_device structure
*/
if (!vcap->s_subdev) {
pad = media_pad_remote_pad_first(&vcap->vdev.entity.pads[0]);
if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
return -EINVAL;
vcap->s_subdev = media_entity_to_v4l2_subdev(pad->entity);
}
ret = v4l2_subdev_call(vcap->s_subdev, video, s_stream, state);
if (ret < 0) {
dev_err(vcap->dev, "failed to %s streaming (%d)\n",
state ? "start" : "stop", ret);
return ret;
}
return 0;
}
static void dcmipp_start_capture(struct dcmipp_bytecap_device *vcap,
struct dcmipp_buf *buf)
{
@ -395,11 +386,24 @@ static int dcmipp_bytecap_start_streaming(struct vb2_queue *vq,
struct dcmipp_bytecap_device *vcap = vb2_get_drv_priv(vq);
struct media_entity *entity = &vcap->vdev.entity;
struct dcmipp_buf *buf;
struct media_pad *pad;
int ret;
vcap->sequence = 0;
memset(&vcap->count, 0, sizeof(vcap->count));
/*
* Get source subdev - since link is IMMUTABLE, pointer is cached
* within the dcmipp_bytecap_device structure
*/
if (!vcap->s_subdev) {
pad = media_pad_remote_pad_first(&vcap->vdev.entity.pads[0]);
if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
return -EINVAL;
vcap->s_subdev = media_entity_to_v4l2_subdev(pad->entity);
vcap->s_subdev_pad_nb = pad->index;
}
ret = pm_runtime_resume_and_get(vcap->dev);
if (ret < 0) {
dev_err(vcap->dev, "%s: Failed to start streaming, cannot get sync (%d)\n",
@ -414,7 +418,8 @@ static int dcmipp_bytecap_start_streaming(struct vb2_queue *vq,
goto err_pm_put;
}
ret = dcmipp_pipeline_s_stream(vcap, 1);
ret = v4l2_subdev_enable_streams(vcap->s_subdev,
vcap->s_subdev_pad_nb, BIT_ULL(0));
if (ret)
goto err_media_pipeline_stop;
@ -482,7 +487,10 @@ static void dcmipp_bytecap_stop_streaming(struct vb2_queue *vq)
int ret;
u32 status;
dcmipp_pipeline_s_stream(vcap, 0);
ret = v4l2_subdev_disable_streams(vcap->s_subdev,
vcap->s_subdev_pad_nb, BIT_ULL(0));
if (ret)
dev_warn(vcap->dev, "Failed to disable stream\n");
/* Stop the media pipeline */
media_pipeline_stop(vcap->vdev.entity.pads);
@ -810,8 +818,7 @@ static int dcmipp_bytecap_link_validate(struct media_link *link)
.which = V4L2_SUBDEV_FORMAT_ACTIVE,
.pad = link->source->index,
};
const struct dcmipp_bytecap_pix_map *vpix;
int ret;
int ret, i;
ret = v4l2_subdev_call(source_sd, pad, get_fmt, NULL, &source_fmt);
if (ret < 0)
@ -825,10 +832,17 @@ static int dcmipp_bytecap_link_validate(struct media_link *link)
return -EINVAL;
}
vpix = dcmipp_bytecap_pix_map_by_pixelformat(vcap->format.pixelformat);
if (source_fmt.format.code != vpix->code) {
dev_err(vcap->dev, "Wrong mbus_code 0x%x, (0x%x expected)\n",
vpix->code, source_fmt.format.code);
for (i = 0; i < ARRAY_SIZE(dcmipp_bytecap_pix_map_list); i++) {
if (dcmipp_bytecap_pix_map_list[i].pixelformat ==
vcap->format.pixelformat &&
dcmipp_bytecap_pix_map_list[i].code ==
source_fmt.format.code)
break;
}
if (i == ARRAY_SIZE(dcmipp_bytecap_pix_map_list)) {
dev_err(vcap->dev, "mbus code 0x%x do not match capture device format (0x%x)\n",
vcap->format.pixelformat, source_fmt.format.code);
return -EINVAL;
}
@ -887,7 +901,7 @@ struct dcmipp_ent_device *dcmipp_bytecap_ent_init(struct device *dev,
q->dev = dev;
/* DCMIPP requires 16 bytes aligned buffers */
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32) & ~0x0f);
ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
if (ret) {
dev_err(dev, "Failed to set DMA mask\n");
goto err_mutex_destroy;

117
drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-byteproc.c
View File

@ -48,15 +48,32 @@ struct dcmipp_byteproc_pix_map {
}
static const struct dcmipp_byteproc_pix_map dcmipp_byteproc_pix_map_list[] = {
PIXMAP_MBUS_BPP(RGB565_2X8_LE, 2),
PIXMAP_MBUS_BPP(RGB565_1X16, 2),
PIXMAP_MBUS_BPP(YUYV8_2X8, 2),
PIXMAP_MBUS_BPP(YUYV8_1X16, 2),
PIXMAP_MBUS_BPP(YVYU8_2X8, 2),
PIXMAP_MBUS_BPP(YVYU8_1X16, 2),
PIXMAP_MBUS_BPP(UYVY8_2X8, 2),
PIXMAP_MBUS_BPP(UYVY8_1X16, 2),
PIXMAP_MBUS_BPP(VYUY8_2X8, 2),
PIXMAP_MBUS_BPP(VYUY8_1X16, 2),
PIXMAP_MBUS_BPP(Y8_1X8, 1),
PIXMAP_MBUS_BPP(SBGGR8_1X8, 1),
PIXMAP_MBUS_BPP(SGBRG8_1X8, 1),
PIXMAP_MBUS_BPP(SGRBG8_1X8, 1),
PIXMAP_MBUS_BPP(SRGGB8_1X8, 1),
PIXMAP_MBUS_BPP(SBGGR10_1X10, 2),
PIXMAP_MBUS_BPP(SGBRG10_1X10, 2),
PIXMAP_MBUS_BPP(SGRBG10_1X10, 2),
PIXMAP_MBUS_BPP(SRGGB10_1X10, 2),
PIXMAP_MBUS_BPP(SBGGR12_1X12, 2),
PIXMAP_MBUS_BPP(SGBRG12_1X12, 2),
PIXMAP_MBUS_BPP(SGRBG12_1X12, 2),
PIXMAP_MBUS_BPP(SRGGB12_1X12, 2),
PIXMAP_MBUS_BPP(SBGGR14_1X14, 2),
PIXMAP_MBUS_BPP(SGBRG14_1X14, 2),
PIXMAP_MBUS_BPP(SGRBG14_1X14, 2),
PIXMAP_MBUS_BPP(SRGGB14_1X14, 2),
PIXMAP_MBUS_BPP(JPEG_1X8, 1),
};
@ -78,7 +95,6 @@ struct dcmipp_byteproc_device {
struct v4l2_subdev sd;
struct device *dev;
void __iomem *regs;
bool streaming;
};
static const struct v4l2_mbus_framefmt fmt_default = {
@ -239,11 +255,10 @@ static int dcmipp_byteproc_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *fmt)
{
struct dcmipp_byteproc_device *byteproc = v4l2_get_subdevdata(sd);
struct v4l2_mbus_framefmt *mf;
struct v4l2_rect *crop, *compose;
if (byteproc->streaming)
if (v4l2_subdev_is_streaming(sd))
return -EBUSY;
mf = v4l2_subdev_state_get_format(sd_state, fmt->pad);
@ -382,30 +397,19 @@ static int dcmipp_byteproc_set_selection(struct v4l2_subdev *sd,
return 0;
}
static const struct v4l2_subdev_pad_ops dcmipp_byteproc_pad_ops = {
.enum_mbus_code = dcmipp_byteproc_enum_mbus_code,
.enum_frame_size = dcmipp_byteproc_enum_frame_size,
.get_fmt = v4l2_subdev_get_fmt,
.set_fmt = dcmipp_byteproc_set_fmt,
.get_selection = dcmipp_byteproc_get_selection,
.set_selection = dcmipp_byteproc_set_selection,
};
static int dcmipp_byteproc_configure_scale_crop
(struct dcmipp_byteproc_device *byteproc)
(struct dcmipp_byteproc_device *byteproc,
struct v4l2_subdev_state *state)
{
const struct dcmipp_byteproc_pix_map *vpix;
struct v4l2_subdev_state *state;
struct v4l2_mbus_framefmt *sink_fmt;
u32 hprediv, vprediv;
struct v4l2_rect *compose, *crop;
u32 val = 0;
state = v4l2_subdev_lock_and_get_active_state(&byteproc->sd);
sink_fmt = v4l2_subdev_state_get_format(state, 0);
compose = v4l2_subdev_state_get_compose(state, 0);
crop = v4l2_subdev_state_get_crop(state, 1);
v4l2_subdev_unlock_state(state);
/* find output format bpp */
vpix = dcmipp_byteproc_pix_map_by_code(sink_fmt->code);
@ -460,48 +464,73 @@ static int dcmipp_byteproc_configure_scale_crop
return 0;
}
static int dcmipp_byteproc_s_stream(struct v4l2_subdev *sd, int enable)
static int dcmipp_byteproc_enable_streams(struct v4l2_subdev *sd,
struct v4l2_subdev_state *state,
u32 pad, u64 streams_mask)
{
struct dcmipp_byteproc_device *byteproc = v4l2_get_subdevdata(sd);
struct v4l2_subdev *s_subdev;
struct media_pad *pad;
int ret = 0;
struct media_pad *s_pad;
int ret;
/* Get source subdev */
pad = media_pad_remote_pad_first(&sd->entity.pads[0]);
if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
s_pad = media_pad_remote_pad_first(&sd->entity.pads[0]);
if (!s_pad || !is_media_entity_v4l2_subdev(s_pad->entity))
return -EINVAL;
s_subdev = media_entity_to_v4l2_subdev(pad->entity);
s_subdev = media_entity_to_v4l2_subdev(s_pad->entity);
if (enable) {
ret = dcmipp_byteproc_configure_scale_crop(byteproc);
if (ret)
return ret;
ret = dcmipp_byteproc_configure_scale_crop(byteproc, state);
if (ret)
return ret;
ret = v4l2_subdev_call(s_subdev, video, s_stream, enable);
if (ret < 0) {
dev_err(byteproc->dev,
"failed to start source subdev streaming (%d)\n",
ret);
return ret;
}
} else {
ret = v4l2_subdev_call(s_subdev, video, s_stream, enable);
if (ret < 0) {
dev_err(byteproc->dev,
"failed to stop source subdev streaming (%d)\n",
ret);
return ret;
}
ret = v4l2_subdev_enable_streams(s_subdev, s_pad->index, BIT_ULL(0));
if (ret < 0) {
dev_err(byteproc->dev,
"failed to start source subdev streaming (%d)\n", ret);
return ret;
}
byteproc->streaming = enable;
return 0;
}
static int dcmipp_byteproc_disable_streams(struct v4l2_subdev *sd,
struct v4l2_subdev_state *state,
u32 pad, u64 streams_mask)
{
struct dcmipp_byteproc_device *byteproc = v4l2_get_subdevdata(sd);
struct v4l2_subdev *s_subdev;
struct media_pad *s_pad;
int ret;
/* Get source subdev */
s_pad = media_pad_remote_pad_first(&sd->entity.pads[0]);
if (!s_pad || !is_media_entity_v4l2_subdev(s_pad->entity))
return -EINVAL;
s_subdev = media_entity_to_v4l2_subdev(s_pad->entity);
ret = v4l2_subdev_disable_streams(s_subdev, s_pad->index, BIT_ULL(0));
if (ret < 0) {
dev_err(byteproc->dev,
"failed to start source subdev streaming (%d)\n", ret);
return ret;
}
return 0;
}
static const struct v4l2_subdev_pad_ops dcmipp_byteproc_pad_ops = {
.enum_mbus_code = dcmipp_byteproc_enum_mbus_code,
.enum_frame_size = dcmipp_byteproc_enum_frame_size,
.get_fmt = v4l2_subdev_get_fmt,
.set_fmt = dcmipp_byteproc_set_fmt,
.get_selection = dcmipp_byteproc_get_selection,
.set_selection = dcmipp_byteproc_set_selection,
.enable_streams = dcmipp_byteproc_enable_streams,
.disable_streams = dcmipp_byteproc_disable_streams,
};
static const struct v4l2_subdev_video_ops dcmipp_byteproc_video_ops = {
.s_stream = dcmipp_byteproc_s_stream,
.s_stream = v4l2_subdev_s_stream_helper,
};
static const struct v4l2_subdev_ops dcmipp_byteproc_ops = {

4
drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-common.h
View File

@ -199,11 +199,11 @@ static inline void __reg_clear(struct device *dev, void __iomem *base, u32 reg,
}
/* DCMIPP subdev init / release entry points */
struct dcmipp_ent_device *dcmipp_par_ent_init(struct device *dev,
struct dcmipp_ent_device *dcmipp_inp_ent_init(struct device *dev,
const char *entity_name,
struct v4l2_device *v4l2_dev,
void __iomem *regs);
void dcmipp_par_ent_release(struct dcmipp_ent_device *ved);
void dcmipp_inp_ent_release(struct dcmipp_ent_device *ved);
struct dcmipp_ent_device *
dcmipp_byteproc_ent_init(struct device *dev, const char *entity_name,
struct v4l2_device *v4l2_dev, void __iomem *regs);

122
drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-core.c
View File

@ -40,6 +40,7 @@ struct dcmipp_device {
/* Hardware resources */
void __iomem *regs;
struct clk *mclk;
struct clk *kclk;
/* The pipeline configuration */
@ -87,6 +88,7 @@ struct dcmipp_pipeline_config {
size_t num_ents;
const struct dcmipp_ent_link *links;
size_t num_links;
u32 hw_revision;
};
/* --------------------------------------------------------------------------
@ -95,9 +97,9 @@ struct dcmipp_pipeline_config {
static const struct dcmipp_ent_config stm32mp13_ent_config[] = {
{
.name = "dcmipp_parallel",
.init = dcmipp_par_ent_init,
.release = dcmipp_par_ent_release,
.name = "dcmipp_input",
.init = dcmipp_inp_ent_init,
.release = dcmipp_inp_ent_release,
},
{
.name = "dcmipp_dump_postproc",
@ -111,22 +113,58 @@ static const struct dcmipp_ent_config stm32mp13_ent_config[] = {
},
};
#define ID_PARALLEL 0
#define ID_INPUT 0
#define ID_DUMP_BYTEPROC 1
#define ID_DUMP_CAPTURE 2
static const struct dcmipp_ent_link stm32mp13_ent_links[] = {
DCMIPP_ENT_LINK(ID_PARALLEL, 1, ID_DUMP_BYTEPROC, 0,
DCMIPP_ENT_LINK(ID_INPUT, 1, ID_DUMP_BYTEPROC, 0,
MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE),
DCMIPP_ENT_LINK(ID_DUMP_BYTEPROC, 1, ID_DUMP_CAPTURE, 0,
MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE),
};
#define DCMIPP_STM32MP13_VERR 0x10
static const struct dcmipp_pipeline_config stm32mp13_pipe_cfg = {
.ents = stm32mp13_ent_config,
.num_ents = ARRAY_SIZE(stm32mp13_ent_config),
.links = stm32mp13_ent_links,
.num_links = ARRAY_SIZE(stm32mp13_ent_links)
.num_links = ARRAY_SIZE(stm32mp13_ent_links),
.hw_revision = DCMIPP_STM32MP13_VERR
};
static const struct dcmipp_ent_config stm32mp25_ent_config[] = {
{
.name = "dcmipp_input",
.init = dcmipp_inp_ent_init,
.release = dcmipp_inp_ent_release,
},
{
.name = "dcmipp_dump_postproc",
.init = dcmipp_byteproc_ent_init,
.release = dcmipp_byteproc_ent_release,
},
{
.name = "dcmipp_dump_capture",
.init = dcmipp_bytecap_ent_init,
.release = dcmipp_bytecap_ent_release,
},
};
static const struct dcmipp_ent_link stm32mp25_ent_links[] = {
DCMIPP_ENT_LINK(ID_INPUT, 1, ID_DUMP_BYTEPROC, 0,
MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE),
DCMIPP_ENT_LINK(ID_DUMP_BYTEPROC, 1, ID_DUMP_CAPTURE, 0,
MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE),
};
#define DCMIPP_STM32MP25_VERR 0x30
static const struct dcmipp_pipeline_config stm32mp25_pipe_cfg = {
.ents = stm32mp25_ent_config,
.num_ents = ARRAY_SIZE(stm32mp25_ent_config),
.links = stm32mp25_ent_links,
.num_links = ARRAY_SIZE(stm32mp25_ent_links),
.hw_revision = DCMIPP_STM32MP25_VERR
};
#define LINK_FLAG_TO_STR(f) ((f) == 0 ? "" :\
@ -209,6 +247,7 @@ static int dcmipp_create_subdevs(struct dcmipp_device *dcmipp)
static const struct of_device_id dcmipp_of_match[] = {
{ .compatible = "st,stm32mp13-dcmipp", .data = &stm32mp13_pipe_cfg },
{ .compatible = "st,stm32mp25-dcmipp", .data = &stm32mp25_pipe_cfg },
{ /* end node */ },
};
MODULE_DEVICE_TABLE(of, dcmipp_of_match);
@ -258,13 +297,22 @@ static int dcmipp_graph_notify_bound(struct v4l2_async_notifier *notifier,
{
struct dcmipp_device *dcmipp = notifier_to_dcmipp(notifier);
unsigned int ret;
int src_pad;
int src_pad, i;
struct dcmipp_ent_device *sink;
struct v4l2_fwnode_endpoint vep = { .bus_type = V4L2_MBUS_PARALLEL };
struct v4l2_fwnode_endpoint vep = { 0 };
struct fwnode_handle *ep;
enum v4l2_mbus_type supported_types[] = {
V4L2_MBUS_PARALLEL, V4L2_MBUS_BT656, V4L2_MBUS_CSI2_DPHY
};
int supported_types_nb = ARRAY_SIZE(supported_types);
dev_dbg(dcmipp->dev, "Subdev \"%s\" bound\n", subdev->name);
/* Only MP25 supports CSI input */
if (!of_device_is_compatible(dcmipp->dev->of_node,
"st,stm32mp25-dcmipp"))
supported_types_nb--;
/*
* Link this sub-device to DCMIPP, it could be
* a parallel camera sensor or a CSI-2 to parallel bridge
@ -281,21 +329,23 @@ static int dcmipp_graph_notify_bound(struct v4l2_async_notifier *notifier,
return -ENODEV;
}
/* Check for parallel bus-type first, then bt656 */
ret = v4l2_fwnode_endpoint_parse(ep, &vep);
if (ret) {
vep.bus_type = V4L2_MBUS_BT656;
/* Check for supported MBUS type */
for (i = 0; i < supported_types_nb; i++) {
vep.bus_type = supported_types[i];
ret = v4l2_fwnode_endpoint_parse(ep, &vep);
if (ret) {
dev_err(dcmipp->dev, "Could not parse the endpoint\n");
fwnode_handle_put(ep);
return ret;
}
if (!ret)
break;
}
fwnode_handle_put(ep);
if (vep.bus.parallel.bus_width == 0) {
if (ret) {
dev_err(dcmipp->dev, "Could not parse the endpoint\n");
return ret;
}
if (vep.bus_type != V4L2_MBUS_CSI2_DPHY &&
vep.bus.parallel.bus_width == 0) {
dev_err(dcmipp->dev, "Invalid parallel interface bus-width\n");
return -ENODEV;
}
@ -308,11 +358,13 @@ static int dcmipp_graph_notify_bound(struct v4l2_async_notifier *notifier,
return -ENODEV;
}
/* Parallel input device detected, connect it to parallel subdev */
sink = dcmipp->entity[ID_PARALLEL];
sink->bus.flags = vep.bus.parallel.flags;
sink->bus.bus_width = vep.bus.parallel.bus_width;
sink->bus.data_shift = vep.bus.parallel.data_shift;
/* Connect input device to the dcmipp_input subdev */
sink = dcmipp->entity[ID_INPUT];
if (vep.bus_type != V4L2_MBUS_CSI2_DPHY) {
sink->bus.flags = vep.bus.parallel.flags;
sink->bus.bus_width = vep.bus.parallel.bus_width;
sink->bus.data_shift = vep.bus.parallel.data_shift;
}
sink->bus_type = vep.bus_type;
ret = media_create_pad_link(&subdev->entity, src_pad, sink->ent, 0,
MEDIA_LNK_FL_IMMUTABLE |
@ -411,7 +463,7 @@ static int dcmipp_graph_init(struct dcmipp_device *dcmipp)
static int dcmipp_probe(struct platform_device *pdev)
{
struct dcmipp_device *dcmipp;
struct clk *kclk;
struct clk *kclk, *mclk;
const struct dcmipp_pipeline_config *pipe_cfg;
struct reset_control *rstc;
int irq;
@ -471,12 +523,20 @@ static int dcmipp_probe(struct platform_device *pdev)
return ret;
}
kclk = devm_clk_get(&pdev->dev, NULL);
kclk = devm_clk_get(&pdev->dev, "kclk");
if (IS_ERR(kclk))
return dev_err_probe(&pdev->dev, PTR_ERR(kclk),
"Unable to get kclk\n");
dcmipp->kclk = kclk;
if (!of_device_is_compatible(pdev->dev.of_node, "st,stm32mp13-dcmipp")) {
mclk = devm_clk_get(&pdev->dev, "mclk");
if (IS_ERR(mclk))
return dev_err_probe(&pdev->dev, PTR_ERR(mclk),
"Unable to get mclk\n");
dcmipp->mclk = mclk;
}
dcmipp->entity = devm_kcalloc(&pdev->dev, dcmipp->pipe_cfg->num_ents,
sizeof(*dcmipp->entity), GFP_KERNEL);
if (!dcmipp->entity)
@ -496,6 +556,7 @@ static int dcmipp_probe(struct platform_device *pdev)
/* Initialize media device */
strscpy(dcmipp->mdev.model, DCMIPP_MDEV_MODEL_NAME,
sizeof(dcmipp->mdev.model));
dcmipp->mdev.hw_revision = pipe_cfg->hw_revision;
dcmipp->mdev.dev = &pdev->dev;
media_device_init(&dcmipp->mdev);
@ -538,6 +599,7 @@ static int dcmipp_runtime_suspend(struct device *dev)
struct dcmipp_device *dcmipp = dev_get_drvdata(dev);
clk_disable_unprepare(dcmipp->kclk);
clk_disable_unprepare(dcmipp->mclk);
return 0;
}
@ -547,9 +609,17 @@ static int dcmipp_runtime_resume(struct device *dev)
struct dcmipp_device *dcmipp = dev_get_drvdata(dev);
int ret;
ret = clk_prepare_enable(dcmipp->mclk);
if (ret) {
dev_err(dev, "%s: Failed to prepare_enable mclk\n", __func__);
return ret;
}
ret = clk_prepare_enable(dcmipp->kclk);
if (ret)
if (ret) {
clk_disable_unprepare(dcmipp->mclk);
dev_err(dev, "%s: Failed to prepare_enable kclk\n", __func__);
}
return ret;
}

540
drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-input.c Normal file
View File

@ -0,0 +1,540 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for STM32 Digital Camera Memory Interface Pixel Processor
*
* Copyright (C) STMicroelectronics SA 2023
* Authors: Hugues Fruchet <hugues.fruchet@foss.st.com>
* Alain Volmat <alain.volmat@foss.st.com>
* for STMicroelectronics.
*/
#include <linux/v4l2-mediabus.h>
#include <media/mipi-csi2.h>
#include <media/v4l2-event.h>
#include <media/v4l2-subdev.h>
#include "dcmipp-common.h"
#define DCMIPP_PRCR 0x104
#define DCMIPP_PRCR_FORMAT_SHIFT 16
#define DCMIPP_PRCR_FORMAT_YUV422 0x1e
#define DCMIPP_PRCR_FORMAT_RGB565 0x22
#define DCMIPP_PRCR_FORMAT_RAW8 0x2a
#define DCMIPP_PRCR_FORMAT_RAW10 0x2b
#define DCMIPP_PRCR_FORMAT_RAW12 0x2c
#define DCMIPP_PRCR_FORMAT_RAW14 0x2d
#define DCMIPP_PRCR_FORMAT_G8 0x4a
#define DCMIPP_PRCR_FORMAT_BYTE_STREAM 0x5a
#define DCMIPP_PRCR_ESS BIT(4)
#define DCMIPP_PRCR_PCKPOL BIT(5)
#define DCMIPP_PRCR_HSPOL BIT(6)
#define DCMIPP_PRCR_VSPOL BIT(7)
#define DCMIPP_PRCR_ENABLE BIT(14)
#define DCMIPP_PRCR_SWAPCYCLES BIT(25)
#define DCMIPP_PRESCR 0x108
#define DCMIPP_PRESUR 0x10c
#define DCMIPP_CMCR 0x204
#define DCMIPP_CMCR_INSEL BIT(0)
#define DCMIPP_P0FSCR 0x404
#define DCMIPP_P0FSCR_DTMODE_MASK GENMASK(17, 16)
#define DCMIPP_P0FSCR_DTMODE_SHIFT 16
#define DCMIPP_P0FSCR_DTMODE_DTIDA 0x00
#define DCMIPP_P0FSCR_DTMODE_ALLDT 0x03
#define DCMIPP_P0FSCR_DTIDA_MASK GENMASK(5, 0)
#define DCMIPP_P0FSCR_DTIDA_SHIFT 0
#define IS_SINK(pad) (!(pad))
#define IS_SRC(pad) ((pad))
struct dcmipp_inp_pix_map {
unsigned int code_sink;
unsigned int code_src;
/* Parallel related information */
u8 prcr_format;
u8 prcr_swapcycles;
/* CSI related information */
unsigned int dt;
};
#define PIXMAP_SINK_SRC_PRCR_SWAP(sink, src, prcr, swap, data_type) \
{ \
.code_sink = MEDIA_BUS_FMT_##sink, \
.code_src = MEDIA_BUS_FMT_##src, \
.prcr_format = DCMIPP_PRCR_FORMAT_##prcr, \
.prcr_swapcycles = swap, \
.dt = data_type, \
}
static const struct dcmipp_inp_pix_map dcmipp_inp_pix_map_list[] = {
/* RGB565 */
PIXMAP_SINK_SRC_PRCR_SWAP(RGB565_2X8_LE, RGB565_2X8_LE, RGB565, 1, MIPI_CSI2_DT_RGB565),
PIXMAP_SINK_SRC_PRCR_SWAP(RGB565_2X8_BE, RGB565_2X8_LE, RGB565, 0, MIPI_CSI2_DT_RGB565),
PIXMAP_SINK_SRC_PRCR_SWAP(RGB565_1X16, RGB565_1X16, RGB565, 0, MIPI_CSI2_DT_RGB565),
/* YUV422 */
PIXMAP_SINK_SRC_PRCR_SWAP(YUYV8_2X8, YUYV8_2X8, YUV422, 1, MIPI_CSI2_DT_YUV422_8B),
PIXMAP_SINK_SRC_PRCR_SWAP(YUYV8_1X16, YUYV8_1X16, YUV422, 0, MIPI_CSI2_DT_YUV422_8B),
PIXMAP_SINK_SRC_PRCR_SWAP(YUYV8_2X8, UYVY8_2X8, YUV422, 0, MIPI_CSI2_DT_YUV422_8B),
PIXMAP_SINK_SRC_PRCR_SWAP(UYVY8_2X8, UYVY8_2X8, YUV422, 1, MIPI_CSI2_DT_YUV422_8B),
PIXMAP_SINK_SRC_PRCR_SWAP(UYVY8_1X16, UYVY8_1X16, YUV422, 0, MIPI_CSI2_DT_YUV422_8B),
PIXMAP_SINK_SRC_PRCR_SWAP(UYVY8_2X8, YUYV8_2X8, YUV422, 0, MIPI_CSI2_DT_YUV422_8B),
PIXMAP_SINK_SRC_PRCR_SWAP(YVYU8_2X8, YVYU8_2X8, YUV422, 1, MIPI_CSI2_DT_YUV422_8B),
PIXMAP_SINK_SRC_PRCR_SWAP(YVYU8_1X16, YVYU8_1X16, YUV422, 0, MIPI_CSI2_DT_YUV422_8B),
PIXMAP_SINK_SRC_PRCR_SWAP(VYUY8_2X8, VYUY8_2X8, YUV422, 1, MIPI_CSI2_DT_YUV422_8B),
PIXMAP_SINK_SRC_PRCR_SWAP(VYUY8_1X16, VYUY8_1X16, YUV422, 0, MIPI_CSI2_DT_YUV422_8B),
/* GREY */
PIXMAP_SINK_SRC_PRCR_SWAP(Y8_1X8, Y8_1X8, G8, 0, MIPI_CSI2_DT_RAW8),
/* Raw Bayer */
PIXMAP_SINK_SRC_PRCR_SWAP(SBGGR8_1X8, SBGGR8_1X8, RAW8, 0, MIPI_CSI2_DT_RAW8),
PIXMAP_SINK_SRC_PRCR_SWAP(SGBRG8_1X8, SGBRG8_1X8, RAW8, 0, MIPI_CSI2_DT_RAW8),
PIXMAP_SINK_SRC_PRCR_SWAP(SGRBG8_1X8, SGRBG8_1X8, RAW8, 0, MIPI_CSI2_DT_RAW8),
PIXMAP_SINK_SRC_PRCR_SWAP(SRGGB8_1X8, SRGGB8_1X8, RAW8, 0, MIPI_CSI2_DT_RAW8),
PIXMAP_SINK_SRC_PRCR_SWAP(SBGGR10_1X10, SBGGR10_1X10, RAW10, 0, MIPI_CSI2_DT_RAW10),
PIXMAP_SINK_SRC_PRCR_SWAP(SGBRG10_1X10, SGBRG10_1X10, RAW10, 0, MIPI_CSI2_DT_RAW10),
PIXMAP_SINK_SRC_PRCR_SWAP(SGRBG10_1X10, SGRBG10_1X10, RAW10, 0, MIPI_CSI2_DT_RAW10),
PIXMAP_SINK_SRC_PRCR_SWAP(SRGGB10_1X10, SRGGB10_1X10, RAW10, 0, MIPI_CSI2_DT_RAW10),
PIXMAP_SINK_SRC_PRCR_SWAP(SBGGR12_1X12, SBGGR12_1X12, RAW12, 0, MIPI_CSI2_DT_RAW12),
PIXMAP_SINK_SRC_PRCR_SWAP(SGBRG12_1X12, SGBRG12_1X12, RAW12, 0, MIPI_CSI2_DT_RAW12),
PIXMAP_SINK_SRC_PRCR_SWAP(SGRBG12_1X12, SGRBG12_1X12, RAW12, 0, MIPI_CSI2_DT_RAW12),
PIXMAP_SINK_SRC_PRCR_SWAP(SRGGB12_1X12, SRGGB12_1X12, RAW12, 0, MIPI_CSI2_DT_RAW12),
PIXMAP_SINK_SRC_PRCR_SWAP(SBGGR14_1X14, SBGGR14_1X14, RAW14, 0, MIPI_CSI2_DT_RAW14),
PIXMAP_SINK_SRC_PRCR_SWAP(SGBRG14_1X14, SGBRG14_1X14, RAW14, 0, MIPI_CSI2_DT_RAW14),
PIXMAP_SINK_SRC_PRCR_SWAP(SGRBG14_1X14, SGRBG14_1X14, RAW14, 0, MIPI_CSI2_DT_RAW14),
PIXMAP_SINK_SRC_PRCR_SWAP(SRGGB14_1X14, SRGGB14_1X14, RAW14, 0, MIPI_CSI2_DT_RAW14),
/* JPEG */
PIXMAP_SINK_SRC_PRCR_SWAP(JPEG_1X8, JPEG_1X8, BYTE_STREAM, 0, 0),
};
/*
* Search through the pix_map table, skipping two consecutive entry with the
* same code
*/
static inline const struct dcmipp_inp_pix_map *dcmipp_inp_pix_map_by_index
(unsigned int index,
unsigned int pad)
{
unsigned int i = 0;
u32 prev_code = 0, cur_code;
while (i < ARRAY_SIZE(dcmipp_inp_pix_map_list)) {
if (IS_SRC(pad))
cur_code = dcmipp_inp_pix_map_list[i].code_src;
else
cur_code = dcmipp_inp_pix_map_list[i].code_sink;
if (cur_code == prev_code) {
i++;
continue;
}
prev_code = cur_code;
if (index == 0)
break;
i++;
index--;
}
if (i >= ARRAY_SIZE(dcmipp_inp_pix_map_list))
return NULL;
return &dcmipp_inp_pix_map_list[i];
}
static inline const struct dcmipp_inp_pix_map *dcmipp_inp_pix_map_by_code
(u32 code_sink, u32 code_src)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(dcmipp_inp_pix_map_list); i++) {
if ((dcmipp_inp_pix_map_list[i].code_sink == code_sink &&
dcmipp_inp_pix_map_list[i].code_src == code_src) ||
(dcmipp_inp_pix_map_list[i].code_sink == code_src &&
dcmipp_inp_pix_map_list[i].code_src == code_sink) ||
(dcmipp_inp_pix_map_list[i].code_sink == code_sink &&
code_src == 0) ||
(code_sink == 0 &&
dcmipp_inp_pix_map_list[i].code_src == code_src))
return &dcmipp_inp_pix_map_list[i];
}
return NULL;
}
struct dcmipp_inp_device {
struct dcmipp_ent_device ved;
struct v4l2_subdev sd;
struct device *dev;
void __iomem *regs;
};
static const struct v4l2_mbus_framefmt fmt_default = {
.width = DCMIPP_FMT_WIDTH_DEFAULT,
.height = DCMIPP_FMT_HEIGHT_DEFAULT,
.code = MEDIA_BUS_FMT_RGB565_2X8_LE,
.field = V4L2_FIELD_NONE,
.colorspace = DCMIPP_COLORSPACE_DEFAULT,
.ycbcr_enc = DCMIPP_YCBCR_ENC_DEFAULT,
.quantization = DCMIPP_QUANTIZATION_DEFAULT,
.xfer_func = DCMIPP_XFER_FUNC_DEFAULT,
};
static int dcmipp_inp_init_state(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state)
{
unsigned int i;
for (i = 0; i < sd->entity.num_pads; i++) {
struct v4l2_mbus_framefmt *mf;
mf = v4l2_subdev_state_get_format(sd_state, i);
*mf = fmt_default;
}
return 0;
}
static int dcmipp_inp_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_mbus_code_enum *code)
{
const struct dcmipp_inp_pix_map *vpix =
dcmipp_inp_pix_map_by_index(code->index, code->pad);
if (!vpix)
return -EINVAL;
code->code = IS_SRC(code->pad) ? vpix->code_src : vpix->code_sink;
return 0;
}
static int dcmipp_inp_enum_frame_size(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_frame_size_enum *fse)
{
const struct dcmipp_inp_pix_map *vpix;
if (fse->index)
return -EINVAL;
/* Only accept code in the pix map table */
vpix = dcmipp_inp_pix_map_by_code(IS_SINK(fse->pad) ? fse->code : 0,
IS_SRC(fse->pad) ? fse->code : 0);
if (!vpix)
return -EINVAL;
fse->min_width = DCMIPP_FRAME_MIN_WIDTH;
fse->max_width = DCMIPP_FRAME_MAX_WIDTH;
fse->min_height = DCMIPP_FRAME_MIN_HEIGHT;
fse->max_height = DCMIPP_FRAME_MAX_HEIGHT;
return 0;
}
static void dcmipp_inp_adjust_fmt(struct dcmipp_inp_device *inp,
struct v4l2_mbus_framefmt *fmt, __u32 pad)
{
const struct dcmipp_inp_pix_map *vpix;
/* Only accept code in the pix map table */
vpix = dcmipp_inp_pix_map_by_code(IS_SINK(pad) ? fmt->code : 0,
IS_SRC(pad) ? fmt->code : 0);
if (!vpix)
fmt->code = fmt_default.code;
/* Exclude JPEG if BT656 bus is selected */
if (vpix && vpix->code_sink == MEDIA_BUS_FMT_JPEG_1X8 &&
inp->ved.bus_type == V4L2_MBUS_BT656)
fmt->code = fmt_default.code;
fmt->width = clamp_t(u32, fmt->width, DCMIPP_FRAME_MIN_WIDTH,
DCMIPP_FRAME_MAX_WIDTH) & ~1;
fmt->height = clamp_t(u32, fmt->height, DCMIPP_FRAME_MIN_HEIGHT,
DCMIPP_FRAME_MAX_HEIGHT) & ~1;
if (fmt->field == V4L2_FIELD_ANY || fmt->field == V4L2_FIELD_ALTERNATE)
fmt->field = fmt_default.field;
dcmipp_colorimetry_clamp(fmt);
}
static int dcmipp_inp_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *fmt)
{
struct dcmipp_inp_device *inp = v4l2_get_subdevdata(sd);
struct v4l2_mbus_framefmt *mf;
if (v4l2_subdev_is_streaming(sd))
return -EBUSY;
mf = v4l2_subdev_state_get_format(sd_state, fmt->pad);
/* Set the new format */
dcmipp_inp_adjust_fmt(inp, &fmt->format, fmt->pad);
dev_dbg(inp->dev, "%s: format update: old:%dx%d (0x%x, %d, %d, %d, %d) new:%dx%d (0x%x, %d, %d, %d, %d)\n",
inp->sd.name,
/* old */
mf->width, mf->height, mf->code,
mf->colorspace, mf->quantization,
mf->xfer_func, mf->ycbcr_enc,
/* new */
fmt->format.width, fmt->format.height, fmt->format.code,
fmt->format.colorspace, fmt->format.quantization,
fmt->format.xfer_func, fmt->format.ycbcr_enc);
*mf = fmt->format;
/* When setting the sink format, report that format on the src pad */
if (IS_SINK(fmt->pad)) {
mf = v4l2_subdev_state_get_format(sd_state, 1);
*mf = fmt->format;
dcmipp_inp_adjust_fmt(inp, mf, 1);
}
return 0;
}
static int dcmipp_inp_configure_parallel(struct dcmipp_inp_device *inp,
struct v4l2_subdev_state *state)
{
u32 val = 0;
const struct dcmipp_inp_pix_map *vpix;
struct v4l2_mbus_framefmt *sink_fmt;
struct v4l2_mbus_framefmt *src_fmt;
/* Set vertical synchronization polarity */
if (inp->ved.bus.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
val |= DCMIPP_PRCR_VSPOL;
/* Set horizontal synchronization polarity */
if (inp->ved.bus.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
val |= DCMIPP_PRCR_HSPOL;
/* Set pixel clock polarity */
if (inp->ved.bus.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
val |= DCMIPP_PRCR_PCKPOL;
/*
* BT656 embedded synchronisation bus mode.
*
* Default SAV/EAV mode is supported here with default codes
* SAV=0xff000080 & EAV=0xff00009d.
* With DCMIPP this means LSC=SAV=0x80 & LEC=EAV=0x9d.
*/
if (inp->ved.bus_type == V4L2_MBUS_BT656) {
val |= DCMIPP_PRCR_ESS;
/* Unmask all codes */
reg_write(inp, DCMIPP_PRESUR, 0xffffffff);/* FEC:LEC:LSC:FSC */
/* Trig on LSC=0x80 & LEC=0x9d codes, ignore FSC and FEC */
reg_write(inp, DCMIPP_PRESCR, 0xff9d80ff);/* FEC:LEC:LSC:FSC */
}
/* Set format */
sink_fmt = v4l2_subdev_state_get_format(state, 0);
src_fmt = v4l2_subdev_state_get_format(state, 1);
vpix = dcmipp_inp_pix_map_by_code(sink_fmt->code, src_fmt->code);
if (!vpix) {
dev_err(inp->dev, "Invalid sink/src format configuration\n");
return -EINVAL;
}
val |= vpix->prcr_format << DCMIPP_PRCR_FORMAT_SHIFT;
/* swap cycles */
if (vpix->prcr_swapcycles)
val |= DCMIPP_PRCR_SWAPCYCLES;
reg_write(inp, DCMIPP_PRCR, val);
/* Select the DCMIPP parallel interface */
reg_write(inp, DCMIPP_CMCR, 0);
/* Enable parallel interface */
reg_set(inp, DCMIPP_PRCR, DCMIPP_PRCR_ENABLE);
return 0;
}
static int dcmipp_inp_configure_csi(struct dcmipp_inp_device *inp,
struct v4l2_subdev_state *state)
{
const struct dcmipp_inp_pix_map *vpix;
struct v4l2_mbus_framefmt *sink_fmt;
struct v4l2_mbus_framefmt *src_fmt;
/* Get format information */
sink_fmt = v4l2_subdev_state_get_format(state, 0);
src_fmt = v4l2_subdev_state_get_format(state, 1);
vpix = dcmipp_inp_pix_map_by_code(sink_fmt->code, src_fmt->code);
if (!vpix) {
dev_err(inp->dev, "Invalid sink/src format configuration\n");
return -EINVAL;
}
/* Apply configuration on each input pipe */
reg_clear(inp, DCMIPP_P0FSCR,
DCMIPP_P0FSCR_DTMODE_MASK | DCMIPP_P0FSCR_DTIDA_MASK);
/* In case of JPEG we don't know the DT so we allow all data */
/*
* TODO - check instead dt == 0 for the time being to allow other
* unknown data-type
*/
if (!vpix->dt)
reg_set(inp, DCMIPP_P0FSCR,
DCMIPP_P0FSCR_DTMODE_ALLDT << DCMIPP_P0FSCR_DTMODE_SHIFT);
else
reg_set(inp, DCMIPP_P0FSCR,
vpix->dt << DCMIPP_P0FSCR_DTIDA_SHIFT |
DCMIPP_P0FSCR_DTMODE_DTIDA);
/* Select the DCMIPP CSI interface */
reg_write(inp, DCMIPP_CMCR, DCMIPP_CMCR_INSEL);
return 0;
}
static int dcmipp_inp_enable_streams(struct v4l2_subdev *sd,
struct v4l2_subdev_state *state,
u32 pad, u64 streams_mask)
{
struct dcmipp_inp_device *inp =
container_of(sd, struct dcmipp_inp_device, sd);
struct v4l2_subdev *s_subdev;
struct media_pad *s_pad;
int ret = 0;
/* Get source subdev */
s_pad = media_pad_remote_pad_first(&sd->entity.pads[0]);
if (!s_pad || !is_media_entity_v4l2_subdev(s_pad->entity))
return -EINVAL;
s_subdev = media_entity_to_v4l2_subdev(s_pad->entity);
if (inp->ved.bus_type == V4L2_MBUS_PARALLEL ||
inp->ved.bus_type == V4L2_MBUS_BT656)
ret = dcmipp_inp_configure_parallel(inp, state);
else if (inp->ved.bus_type == V4L2_MBUS_CSI2_DPHY)
ret = dcmipp_inp_configure_csi(inp, state);
if (ret)
return ret;
ret = v4l2_subdev_enable_streams(s_subdev, s_pad->index, BIT_ULL(0));
if (ret < 0) {
dev_err(inp->dev,
"failed to start source subdev streaming (%d)\n", ret);
return ret;
}
return 0;
}
static int dcmipp_inp_disable_streams(struct v4l2_subdev *sd,
struct v4l2_subdev_state *state,
u32 pad, u64 streams_mask)
{
struct dcmipp_inp_device *inp =
container_of(sd, struct dcmipp_inp_device, sd);
struct v4l2_subdev *s_subdev;
struct media_pad *s_pad;
int ret;
/* Get source subdev */
s_pad = media_pad_remote_pad_first(&sd->entity.pads[0]);
if (!s_pad || !is_media_entity_v4l2_subdev(s_pad->entity))
return -EINVAL;
s_subdev = media_entity_to_v4l2_subdev(s_pad->entity);
ret = v4l2_subdev_disable_streams(s_subdev, s_pad->index, BIT_ULL(0));
if (ret < 0) {
dev_err(inp->dev,
"failed to stop source subdev streaming (%d)\n", ret);
return ret;
}
if (inp->ved.bus_type == V4L2_MBUS_PARALLEL ||
inp->ved.bus_type == V4L2_MBUS_BT656) {
/* Disable parallel interface */
reg_clear(inp, DCMIPP_PRCR, DCMIPP_PRCR_ENABLE);
}
return 0;
}
static const struct v4l2_subdev_pad_ops dcmipp_inp_pad_ops = {
.enum_mbus_code = dcmipp_inp_enum_mbus_code,
.enum_frame_size = dcmipp_inp_enum_frame_size,
.get_fmt = v4l2_subdev_get_fmt,
.set_fmt = dcmipp_inp_set_fmt,
.enable_streams = dcmipp_inp_enable_streams,
.disable_streams = dcmipp_inp_disable_streams,
};
static const struct v4l2_subdev_video_ops dcmipp_inp_video_ops = {
.s_stream = v4l2_subdev_s_stream_helper,
};
static const struct v4l2_subdev_ops dcmipp_inp_ops = {
.pad = &dcmipp_inp_pad_ops,
.video = &dcmipp_inp_video_ops,
};
static void dcmipp_inp_release(struct v4l2_subdev *sd)
{
struct dcmipp_inp_device *inp =
container_of(sd, struct dcmipp_inp_device, sd);
kfree(inp);
}
static const struct v4l2_subdev_internal_ops dcmipp_inp_int_ops = {
.init_state = dcmipp_inp_init_state,
.release = dcmipp_inp_release,
};
void dcmipp_inp_ent_release(struct dcmipp_ent_device *ved)
{
struct dcmipp_inp_device *inp =
container_of(ved, struct dcmipp_inp_device, ved);
dcmipp_ent_sd_unregister(ved, &inp->sd);
}
struct dcmipp_ent_device *dcmipp_inp_ent_init(struct device *dev,
const char *entity_name,
struct v4l2_device *v4l2_dev,
void __iomem *regs)
{
struct dcmipp_inp_device *inp;
const unsigned long pads_flag[] = {
MEDIA_PAD_FL_SINK, MEDIA_PAD_FL_SOURCE,
};
int ret;
/* Allocate the inp struct */
inp = kzalloc(sizeof(*inp), GFP_KERNEL);
if (!inp)
return ERR_PTR(-ENOMEM);
inp->regs = regs;
/* Initialize ved and sd */
ret = dcmipp_ent_sd_register(&inp->ved, &inp->sd, v4l2_dev,
entity_name, MEDIA_ENT_F_VID_IF_BRIDGE,
ARRAY_SIZE(pads_flag), pads_flag,
&dcmipp_inp_int_ops, &dcmipp_inp_ops,
NULL, NULL);
if (ret) {
kfree(inp);
return ERR_PTR(ret);
}
inp->dev = dev;
return &inp->ved;
}

440
drivers/media/platform/st/stm32/stm32-dcmipp/dcmipp-parallel.c
View File

@ -1,440 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Driver for STM32 Digital Camera Memory Interface Pixel Processor
*
* Copyright (C) STMicroelectronics SA 2023
* Authors: Hugues Fruchet <hugues.fruchet@foss.st.com>
* Alain Volmat <alain.volmat@foss.st.com>
* for STMicroelectronics.
*/
#include <linux/v4l2-mediabus.h>
#include <media/v4l2-event.h>
#include <media/v4l2-subdev.h>
#include "dcmipp-common.h"
#define DCMIPP_PRCR 0x104
#define DCMIPP_PRCR_FORMAT_SHIFT 16
#define DCMIPP_PRCR_FORMAT_YUV422 0x1e
#define DCMIPP_PRCR_FORMAT_RGB565 0x22
#define DCMIPP_PRCR_FORMAT_RAW8 0x2a
#define DCMIPP_PRCR_FORMAT_G8 0x4a
#define DCMIPP_PRCR_FORMAT_BYTE_STREAM 0x5a
#define DCMIPP_PRCR_ESS BIT(4)
#define DCMIPP_PRCR_PCKPOL BIT(5)
#define DCMIPP_PRCR_HSPOL BIT(6)
#define DCMIPP_PRCR_VSPOL BIT(7)
#define DCMIPP_PRCR_ENABLE BIT(14)
#define DCMIPP_PRCR_SWAPCYCLES BIT(25)
#define DCMIPP_PRESCR 0x108
#define DCMIPP_PRESUR 0x10c
#define IS_SINK(pad) (!(pad))
#define IS_SRC(pad) ((pad))
struct dcmipp_par_pix_map {
unsigned int code_sink;
unsigned int code_src;
u8 prcr_format;
u8 prcr_swapcycles;
};
#define PIXMAP_SINK_SRC_PRCR_SWAP(sink, src, prcr, swap) \
{ \
.code_sink = MEDIA_BUS_FMT_##sink, \
.code_src = MEDIA_BUS_FMT_##src, \
.prcr_format = DCMIPP_PRCR_FORMAT_##prcr, \
.prcr_swapcycles = swap, \
}
static const struct dcmipp_par_pix_map dcmipp_par_pix_map_list[] = {
/* RGB565 */
PIXMAP_SINK_SRC_PRCR_SWAP(RGB565_2X8_LE, RGB565_2X8_LE, RGB565, 1),
PIXMAP_SINK_SRC_PRCR_SWAP(RGB565_2X8_BE, RGB565_2X8_LE, RGB565, 0),
/* YUV422 */
PIXMAP_SINK_SRC_PRCR_SWAP(YUYV8_2X8, YUYV8_2X8, YUV422, 1),
PIXMAP_SINK_SRC_PRCR_SWAP(YUYV8_2X8, UYVY8_2X8, YUV422, 0),
PIXMAP_SINK_SRC_PRCR_SWAP(UYVY8_2X8, UYVY8_2X8, YUV422, 1),
PIXMAP_SINK_SRC_PRCR_SWAP(UYVY8_2X8, YUYV8_2X8, YUV422, 0),
PIXMAP_SINK_SRC_PRCR_SWAP(YVYU8_2X8, YVYU8_2X8, YUV422, 1),
PIXMAP_SINK_SRC_PRCR_SWAP(VYUY8_2X8, VYUY8_2X8, YUV422, 1),
/* GREY */
PIXMAP_SINK_SRC_PRCR_SWAP(Y8_1X8, Y8_1X8, G8, 0),
/* Raw Bayer */
PIXMAP_SINK_SRC_PRCR_SWAP(SBGGR8_1X8, SBGGR8_1X8, RAW8, 0),
PIXMAP_SINK_SRC_PRCR_SWAP(SGBRG8_1X8, SGBRG8_1X8, RAW8, 0),
PIXMAP_SINK_SRC_PRCR_SWAP(SGRBG8_1X8, SGRBG8_1X8, RAW8, 0),
PIXMAP_SINK_SRC_PRCR_SWAP(SRGGB8_1X8, SRGGB8_1X8, RAW8, 0),
/* JPEG */
PIXMAP_SINK_SRC_PRCR_SWAP(JPEG_1X8, JPEG_1X8, BYTE_STREAM, 0),
};
/*
* Search through the pix_map table, skipping two consecutive entry with the
* same code
*/
static inline const struct dcmipp_par_pix_map *dcmipp_par_pix_map_by_index
(unsigned int index,
unsigned int pad)
{
unsigned int i = 0;
u32 prev_code = 0, cur_code;
while (i < ARRAY_SIZE(dcmipp_par_pix_map_list)) {
if (IS_SRC(pad))
cur_code = dcmipp_par_pix_map_list[i].code_src;
else
cur_code = dcmipp_par_pix_map_list[i].code_sink;
if (cur_code == prev_code) {
i++;
continue;
}
prev_code = cur_code;
if (index == 0)
break;
i++;
index--;
}
if (i >= ARRAY_SIZE(dcmipp_par_pix_map_list))
return NULL;
return &dcmipp_par_pix_map_list[i];
}
static inline const struct dcmipp_par_pix_map *dcmipp_par_pix_map_by_code
(u32 code_sink, u32 code_src)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE(dcmipp_par_pix_map_list); i++) {
if ((dcmipp_par_pix_map_list[i].code_sink == code_sink &&
dcmipp_par_pix_map_list[i].code_src == code_src) ||
(dcmipp_par_pix_map_list[i].code_sink == code_src &&
dcmipp_par_pix_map_list[i].code_src == code_sink) ||
(dcmipp_par_pix_map_list[i].code_sink == code_sink &&
code_src == 0) ||
(code_sink == 0 &&
dcmipp_par_pix_map_list[i].code_src == code_src))
return &dcmipp_par_pix_map_list[i];
}
return NULL;
}
struct dcmipp_par_device {
struct dcmipp_ent_device ved;
struct v4l2_subdev sd;
struct device *dev;
void __iomem *regs;
bool streaming;
};
static const struct v4l2_mbus_framefmt fmt_default = {
.width = DCMIPP_FMT_WIDTH_DEFAULT,
.height = DCMIPP_FMT_HEIGHT_DEFAULT,
.code = MEDIA_BUS_FMT_RGB565_2X8_LE,
.field = V4L2_FIELD_NONE,
.colorspace = DCMIPP_COLORSPACE_DEFAULT,
.ycbcr_enc = DCMIPP_YCBCR_ENC_DEFAULT,
.quantization = DCMIPP_QUANTIZATION_DEFAULT,
.xfer_func = DCMIPP_XFER_FUNC_DEFAULT,
};
static int dcmipp_par_init_state(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state)
{
unsigned int i;
for (i = 0; i < sd->entity.num_pads; i++) {
struct v4l2_mbus_framefmt *mf;
mf = v4l2_subdev_state_get_format(sd_state, i);
*mf = fmt_default;
}
return 0;
}
static int dcmipp_par_enum_mbus_code(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_mbus_code_enum *code)
{
const struct dcmipp_par_pix_map *vpix =
dcmipp_par_pix_map_by_index(code->index, code->pad);
if (!vpix)
return -EINVAL;
code->code = IS_SRC(code->pad) ? vpix->code_src : vpix->code_sink;
return 0;
}
static int dcmipp_par_enum_frame_size(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_frame_size_enum *fse)
{
const struct dcmipp_par_pix_map *vpix;
if (fse->index)
return -EINVAL;
/* Only accept code in the pix map table */
vpix = dcmipp_par_pix_map_by_code(IS_SINK(fse->pad) ? fse->code : 0,
IS_SRC(fse->pad) ? fse->code : 0);
if (!vpix)
return -EINVAL;
fse->min_width = DCMIPP_FRAME_MIN_WIDTH;
fse->max_width = DCMIPP_FRAME_MAX_WIDTH;
fse->min_height = DCMIPP_FRAME_MIN_HEIGHT;
fse->max_height = DCMIPP_FRAME_MAX_HEIGHT;
return 0;
}
static void dcmipp_par_adjust_fmt(struct dcmipp_par_device *par,
struct v4l2_mbus_framefmt *fmt, __u32 pad)
{
const struct dcmipp_par_pix_map *vpix;
/* Only accept code in the pix map table */
vpix = dcmipp_par_pix_map_by_code(IS_SINK(pad) ? fmt->code : 0,
IS_SRC(pad) ? fmt->code : 0);
if (!vpix)
fmt->code = fmt_default.code;
/* Exclude JPEG if BT656 bus is selected */
if (vpix && vpix->code_sink == MEDIA_BUS_FMT_JPEG_1X8 &&
par->ved.bus_type == V4L2_MBUS_BT656)
fmt->code = fmt_default.code;
fmt->width = clamp_t(u32, fmt->width, DCMIPP_FRAME_MIN_WIDTH,
DCMIPP_FRAME_MAX_WIDTH) & ~1;
fmt->height = clamp_t(u32, fmt->height, DCMIPP_FRAME_MIN_HEIGHT,
DCMIPP_FRAME_MAX_HEIGHT) & ~1;
if (fmt->field == V4L2_FIELD_ANY || fmt->field == V4L2_FIELD_ALTERNATE)
fmt->field = fmt_default.field;
dcmipp_colorimetry_clamp(fmt);
}
static int dcmipp_par_set_fmt(struct v4l2_subdev *sd,
struct v4l2_subdev_state *sd_state,
struct v4l2_subdev_format *fmt)
{
struct dcmipp_par_device *par = v4l2_get_subdevdata(sd);
struct v4l2_mbus_framefmt *mf;
if (par->streaming)
return -EBUSY;
mf = v4l2_subdev_state_get_format(sd_state, fmt->pad);
/* Set the new format */
dcmipp_par_adjust_fmt(par, &fmt->format, fmt->pad);
dev_dbg(par->dev, "%s: format update: old:%dx%d (0x%x, %d, %d, %d, %d) new:%dx%d (0x%x, %d, %d, %d, %d)\n",
par->sd.name,
/* old */
mf->width, mf->height, mf->code,
mf->colorspace, mf->quantization,
mf->xfer_func, mf->ycbcr_enc,
/* new */
fmt->format.width, fmt->format.height, fmt->format.code,
fmt->format.colorspace, fmt->format.quantization,
fmt->format.xfer_func, fmt->format.ycbcr_enc);
*mf = fmt->format;
/* When setting the sink format, report that format on the src pad */
if (IS_SINK(fmt->pad)) {
mf = v4l2_subdev_state_get_format(sd_state, 1);
*mf = fmt->format;
dcmipp_par_adjust_fmt(par, mf, 1);
}
return 0;
}
static const struct v4l2_subdev_pad_ops dcmipp_par_pad_ops = {
.enum_mbus_code = dcmipp_par_enum_mbus_code,
.enum_frame_size = dcmipp_par_enum_frame_size,
.get_fmt = v4l2_subdev_get_fmt,
.set_fmt = dcmipp_par_set_fmt,
};
static int dcmipp_par_configure(struct dcmipp_par_device *par)
{
u32 val = 0;
const struct dcmipp_par_pix_map *vpix;
struct v4l2_subdev_state *state;
struct v4l2_mbus_framefmt *sink_fmt;
struct v4l2_mbus_framefmt *src_fmt;
/* Set vertical synchronization polarity */
if (par->ved.bus.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
val |= DCMIPP_PRCR_VSPOL;
/* Set horizontal synchronization polarity */
if (par->ved.bus.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
val |= DCMIPP_PRCR_HSPOL;
/* Set pixel clock polarity */
if (par->ved.bus.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
val |= DCMIPP_PRCR_PCKPOL;
/*
* BT656 embedded synchronisation bus mode.
*
* Default SAV/EAV mode is supported here with default codes
* SAV=0xff000080 & EAV=0xff00009d.
* With DCMIPP this means LSC=SAV=0x80 & LEC=EAV=0x9d.
*/
if (par->ved.bus_type == V4L2_MBUS_BT656) {
val |= DCMIPP_PRCR_ESS;
/* Unmask all codes */
reg_write(par, DCMIPP_PRESUR, 0xffffffff);/* FEC:LEC:LSC:FSC */
/* Trig on LSC=0x80 & LEC=0x9d codes, ignore FSC and FEC */
reg_write(par, DCMIPP_PRESCR, 0xff9d80ff);/* FEC:LEC:LSC:FSC */
}
/* Set format */
state = v4l2_subdev_lock_and_get_active_state(&par->sd);
sink_fmt = v4l2_subdev_state_get_format(state, 0);
src_fmt = v4l2_subdev_state_get_format(state, 1);
v4l2_subdev_unlock_state(state);
vpix = dcmipp_par_pix_map_by_code(sink_fmt->code, src_fmt->code);
if (!vpix) {
dev_err(par->dev, "Invalid sink/src format configuration\n");
return -EINVAL;
}
val |= vpix->prcr_format << DCMIPP_PRCR_FORMAT_SHIFT;
/* swap cycles */
if (vpix->prcr_swapcycles)
val |= DCMIPP_PRCR_SWAPCYCLES;
reg_write(par, DCMIPP_PRCR, val);
return 0;
}
static int dcmipp_par_s_stream(struct v4l2_subdev *sd, int enable)
{
struct dcmipp_par_device *par =
container_of(sd, struct dcmipp_par_device, sd);
struct v4l2_subdev *s_subdev;
struct media_pad *pad;
int ret = 0;
/* Get source subdev */
pad = media_pad_remote_pad_first(&sd->entity.pads[0]);
if (!pad || !is_media_entity_v4l2_subdev(pad->entity))
return -EINVAL;
s_subdev = media_entity_to_v4l2_subdev(pad->entity);
if (enable) {
ret = dcmipp_par_configure(par);
if (ret)
return ret;
/* Enable parallel interface */
reg_set(par, DCMIPP_PRCR, DCMIPP_PRCR_ENABLE);
ret = v4l2_subdev_call(s_subdev, video, s_stream, enable);
if (ret < 0) {
dev_err(par->dev,
"failed to start source subdev streaming (%d)\n",
ret);
return ret;
}
} else {
ret = v4l2_subdev_call(s_subdev, video, s_stream, enable);
if (ret < 0) {
dev_err(par->dev,
"failed to stop source subdev streaming (%d)\n",
ret);
return ret;
}
/* Disable parallel interface */
reg_clear(par, DCMIPP_PRCR, DCMIPP_PRCR_ENABLE);
}
par->streaming = enable;
return ret;
}
static const struct v4l2_subdev_video_ops dcmipp_par_video_ops = {
.s_stream = dcmipp_par_s_stream,
};
static const struct v4l2_subdev_ops dcmipp_par_ops = {
.pad = &dcmipp_par_pad_ops,
.video = &dcmipp_par_video_ops,
};
static void dcmipp_par_release(struct v4l2_subdev *sd)
{
struct dcmipp_par_device *par =
container_of(sd, struct dcmipp_par_device, sd);
kfree(par);
}
static const struct v4l2_subdev_internal_ops dcmipp_par_int_ops = {
.init_state = dcmipp_par_init_state,
.release = dcmipp_par_release,
};
void dcmipp_par_ent_release(struct dcmipp_ent_device *ved)
{
struct dcmipp_par_device *par =
container_of(ved, struct dcmipp_par_device, ved);
dcmipp_ent_sd_unregister(ved, &par->sd);
}
struct dcmipp_ent_device *dcmipp_par_ent_init(struct device *dev,
const char *entity_name,
struct v4l2_device *v4l2_dev,
void __iomem *regs)
{
struct dcmipp_par_device *par;
const unsigned long pads_flag[] = {
MEDIA_PAD_FL_SINK, MEDIA_PAD_FL_SOURCE,
};
int ret;
/* Allocate the par struct */
par = kzalloc(sizeof(*par), GFP_KERNEL);
if (!par)
return ERR_PTR(-ENOMEM);
par->regs = regs;
/* Initialize ved and sd */
ret = dcmipp_ent_sd_register(&par->ved, &par->sd, v4l2_dev,
entity_name, MEDIA_ENT_F_VID_IF_BRIDGE,
ARRAY_SIZE(pads_flag), pads_flag,
&dcmipp_par_int_ops, &dcmipp_par_ops,
NULL, NULL);
if (ret) {
kfree(par);
return ERR_PTR(ret);
}
par->dev = dev;
return &par->ved;
}

9
drivers/media/platform/verisilicon/hantro.h
View File

@ -227,6 +227,7 @@ struct hantro_dev {
* @src_fmt: V4L2 pixel format of active source format.
* @vpu_dst_fmt: Descriptor of active destination format.
* @dst_fmt: V4L2 pixel format of active destination format.
* @ref_fmt: V4L2 pixel format of the reference frames format.
*
* @ctrl_handler: Control handler used to register controls.
* @jpeg_quality: User-specified JPEG compression quality.
@ -255,6 +256,7 @@ struct hantro_ctx {
struct v4l2_pix_format_mplane src_fmt;
const struct hantro_fmt *vpu_dst_fmt;
struct v4l2_pix_format_mplane dst_fmt;
struct v4l2_pix_format_mplane ref_fmt;
struct v4l2_ctrl_handler ctrl_handler;
int jpeg_quality;
@ -332,12 +334,19 @@ struct hantro_vp9_decoded_buffer_info {
u32 bit_depth : 4;
};
struct hantro_av1_decoded_buffer_info {
/* Info needed when the decoded frame serves as a reference frame. */
size_t chroma_offset;
size_t mv_offset;
};
struct hantro_decoded_buffer {
/* Must be the first field in this struct. */
struct v4l2_m2m_buffer base;
union {
struct hantro_vp9_decoded_buffer_info vp9;
struct hantro_av1_decoded_buffer_info av1;
};
};

2
drivers/media/platform/verisilicon/hantro_g2.c
View File

@ -47,7 +47,7 @@ irqreturn_t hantro_g2_irq(int irq, void *dev_id)
size_t hantro_g2_chroma_offset(struct hantro_ctx *ctx)
{
return ctx->dst_fmt.width * ctx->dst_fmt.height * ctx->bit_depth / 8;
return ctx->ref_fmt.plane_fmt[0].bytesperline * ctx->ref_fmt.height;
}
size_t hantro_g2_motion_vectors_offset(struct hantro_ctx *ctx)

32
drivers/media/platform/verisilicon/hantro_postproc.c
View File

@ -194,35 +194,25 @@ void hantro_postproc_free(struct hantro_ctx *ctx)
static unsigned int hantro_postproc_buffer_size(struct hantro_ctx *ctx)
{
struct v4l2_pix_format_mplane pix_mp;
const struct hantro_fmt *fmt;
unsigned int buf_size;
/* this should always pick native format */
fmt = hantro_get_default_fmt(ctx, false, ctx->bit_depth, HANTRO_AUTO_POSTPROC);
if (!fmt)
return 0;
v4l2_fill_pixfmt_mp(&pix_mp, fmt->fourcc, ctx->src_fmt.width,
ctx->src_fmt.height);
buf_size = pix_mp.plane_fmt[0].sizeimage;
buf_size = ctx->ref_fmt.plane_fmt[0].sizeimage;
if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE)
buf_size += hantro_h264_mv_size(pix_mp.width,
pix_mp.height);
buf_size += hantro_h264_mv_size(ctx->ref_fmt.width,
ctx->ref_fmt.height);
else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME)
buf_size += hantro_vp9_mv_size(pix_mp.width,
pix_mp.height);
buf_size += hantro_vp9_mv_size(ctx->ref_fmt.width,
ctx->ref_fmt.height);
else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE) {
buf_size += hantro_hevc_mv_size(pix_mp.width,
pix_mp.height);
buf_size += hantro_hevc_mv_size(ctx->ref_fmt.width,
ctx->ref_fmt.height);
if (ctx->hevc_dec.use_compression)
buf_size += hantro_hevc_compressed_size(pix_mp.width,
pix_mp.height);
buf_size += hantro_hevc_compressed_size(ctx->ref_fmt.width,
ctx->ref_fmt.height);
}
else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_AV1_FRAME)
buf_size += hantro_av1_mv_size(pix_mp.width,
pix_mp.height);
buf_size += hantro_av1_mv_size(ctx->ref_fmt.width,
ctx->ref_fmt.height);
return buf_size;
}

21
drivers/media/platform/verisilicon/hantro_v4l2.c
View File

@ -126,6 +126,24 @@ hantro_find_format(const struct hantro_ctx *ctx, u32 fourcc)
return NULL;
}
static int
hantro_set_reference_frames_format(struct hantro_ctx *ctx)
{
const struct hantro_fmt *fmt;
int dst_bit_depth = hantro_get_format_depth(ctx->vpu_dst_fmt->fourcc);
fmt = hantro_get_default_fmt(ctx, false, dst_bit_depth, HANTRO_AUTO_POSTPROC);
if (!fmt)
return -EINVAL;
ctx->ref_fmt.width = ctx->src_fmt.width;
ctx->ref_fmt.height = ctx->src_fmt.height;
v4l2_apply_frmsize_constraints(&ctx->ref_fmt.width, &ctx->ref_fmt.height, &fmt->frmsize);
return v4l2_fill_pixfmt_mp(&ctx->ref_fmt, fmt->fourcc,
ctx->ref_fmt.width, ctx->ref_fmt.height);
}
const struct hantro_fmt *
hantro_get_default_fmt(const struct hantro_ctx *ctx, bool bitstream,
int bit_depth, bool need_postproc)
@ -595,6 +613,9 @@ static int hantro_set_fmt_cap(struct hantro_ctx *ctx,
ctx->vpu_dst_fmt = hantro_find_format(ctx, pix_mp->pixelformat);
ctx->dst_fmt = *pix_mp;
ret = hantro_set_reference_frames_format(ctx);
if (ret)
return ret;
/*
* Current raw format might have become invalid with newly

10
drivers/media/platform/verisilicon/imx8m_vpu_hw.c
View File

@ -187,23 +187,23 @@ static const struct hantro_fmt imx8m_vpu_g2_dec_fmts[] = {
.frmsize = {
.min_width = FMT_MIN_WIDTH,
.max_width = FMT_UHD_WIDTH,
.step_width = TILE_MB_DIM,
.step_width = 8,
.min_height = FMT_MIN_HEIGHT,
.max_height = FMT_UHD_HEIGHT,
.step_height = TILE_MB_DIM,
.step_height = 32,
},
},
{
.fourcc = V4L2_PIX_FMT_P010_4L4,
.fourcc = V4L2_PIX_FMT_NV15_4L4,
.codec_mode = HANTRO_MODE_NONE,
.match_depth = true,
.frmsize = {
.min_width = FMT_MIN_WIDTH,
.max_width = FMT_UHD_WIDTH,
.step_width = TILE_MB_DIM,
.step_width = 8,
.min_height = FMT_MIN_HEIGHT,
.max_height = FMT_UHD_HEIGHT,
.step_height = TILE_MB_DIM,
.step_height = 32,
},
},
{

9
drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
View File

@ -686,8 +686,6 @@ rockchip_vpu981_av1_dec_set_ref(struct hantro_ctx *ctx, int ref, int idx,
struct hantro_dev *vpu = ctx->dev;
struct hantro_decoded_buffer *dst;
dma_addr_t luma_addr, chroma_addr, mv_addr = 0;
size_t cr_offset = rockchip_vpu981_av1_dec_luma_size(ctx);
size_t mv_offset = rockchip_vpu981_av1_dec_chroma_size(ctx);
int cur_width = frame->frame_width_minus_1 + 1;
int cur_height = frame->frame_height_minus_1 + 1;
int scale_width =
@ -744,8 +742,8 @@ rockchip_vpu981_av1_dec_set_ref(struct hantro_ctx *ctx, int ref, int idx,
dst = vb2_to_hantro_decoded_buf(&av1_dec->frame_refs[idx].vb2_ref->vb2_buf);
luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);
chroma_addr = luma_addr + cr_offset;
mv_addr = luma_addr + mv_offset;
chroma_addr = luma_addr + dst->av1.chroma_offset;
mv_addr = luma_addr + dst->av1.mv_offset;
hantro_write_addr(vpu, AV1_REFERENCE_Y(ref), luma_addr);
hantro_write_addr(vpu, AV1_REFERENCE_CB(ref), chroma_addr);
@ -2089,6 +2087,9 @@ rockchip_vpu981_av1_dec_set_output_buffer(struct hantro_ctx *ctx)
chroma_addr = luma_addr + cr_offset;
mv_addr = luma_addr + mv_offset;
dst->av1.chroma_offset = cr_offset;
dst->av1.mv_offset = mv_offset;
hantro_write_addr(vpu, AV1_TILE_OUT_LU, luma_addr);
hantro_write_addr(vpu, AV1_TILE_OUT_CH, chroma_addr);
hantro_write_addr(vpu, AV1_TILE_OUT_MV, mv_addr);

4
drivers/media/radio/Kconfig
View File

@ -221,10 +221,6 @@ config USB_RAREMONO
source "drivers/media/radio/si470x/Kconfig"
source "drivers/media/radio/si4713/Kconfig"
# TI's ST based wl128x FM radio
source "drivers/media/radio/wl128x/Kconfig"
#
# ISA drivers configuration
#

1
drivers/media/radio/Makefile
View File

@ -31,7 +31,6 @@ obj-$(CONFIG_RADIO_TIMBERDALE) += radio-timb.o
obj-$(CONFIG_RADIO_TRUST) += radio-trust.o
obj-$(CONFIG_RADIO_TYPHOON) += radio-typhoon.o
obj-$(CONFIG_RADIO_WL1273) += radio-wl1273.o
obj-$(CONFIG_RADIO_WL128X) += wl128x/
obj-$(CONFIG_RADIO_ZOLTRIX) += radio-zoltrix.o
obj-$(CONFIG_USB_DSBR) += dsbr100.o

15
drivers/media/radio/wl128x/Kconfig
View File

@ -1,15 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# TI's wl128x FM driver based on TI's ST driver.
#
config RADIO_WL128X
tristate "Texas Instruments WL128x FM Radio"
depends on VIDEO_DEV && RFKILL && TTY && TI_ST
depends on GPIOLIB || COMPILE_TEST
help
Choose Y here if you have this FM radio chip.
In order to control your radio card, you will need to use programs
that are compatible with the Video For Linux 2 API. Information on
this API and pointers to "v4l2" programs may be found at
<file:Documentation/userspace-api/media/index.rst>.

7
drivers/media/radio/wl128x/Makefile
View File

@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Makefile for TI's shared transport driver based wl128x
# FM radio.
#
obj-$(CONFIG_RADIO_WL128X) += fm_drv.o
fm_drv-objs := fmdrv_common.o fmdrv_rx.o fmdrv_tx.o fmdrv_v4l2.o

229
drivers/media/radio/wl128x/fmdrv.h
View File

@ -1,229 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* FM Driver for Connectivity chip of Texas Instruments.
*
* Common header for all FM driver sub-modules.
*
* Copyright (C) 2011 Texas Instruments
*/
#ifndef _FM_DRV_H
#define _FM_DRV_H
#include <linux/skbuff.h>
#include <linux/interrupt.h>
#include <sound/core.h>
#include <sound/initval.h>
#include <linux/timer.h>
#include <linux/workqueue.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-common.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ctrls.h>
#define FM_DRV_VERSION "0.1.1"
#define FM_DRV_NAME "ti_fmdrv"
#define FM_DRV_CARD_SHORT_NAME "TI FM Radio"
#define FM_DRV_CARD_LONG_NAME "Texas Instruments FM Radio"
/* Flag info */
#define FM_INTTASK_RUNNING 0
#define FM_INTTASK_SCHEDULE_PENDING 1
#define FM_FW_DW_INPROGRESS 2
#define FM_CORE_READY 3
#define FM_CORE_TRANSPORT_READY 4
#define FM_AF_SWITCH_INPROGRESS 5
#define FM_CORE_TX_XMITING 6
#define FM_TUNE_COMPLETE 0x1
#define FM_BAND_LIMIT 0x2
#define FM_DRV_TX_TIMEOUT (5*HZ) /* 5 seconds */
#define FM_DRV_RX_SEEK_TIMEOUT (20*HZ) /* 20 seconds */
#define fmerr(format, ...) \
printk(KERN_ERR "fmdrv: " format, ## __VA_ARGS__)
#define fmwarn(format, ...) \
printk(KERN_WARNING "fmdrv: " format, ##__VA_ARGS__)
#ifdef DEBUG
#define fmdbg(format, ...) \
printk(KERN_DEBUG "fmdrv: " format, ## __VA_ARGS__)
#else /* DEBUG */
#define fmdbg(format, ...) do {} while(0)
#endif
enum {
FM_MODE_OFF,
FM_MODE_TX,
FM_MODE_RX,
FM_MODE_ENTRY_MAX
};
#define FM_RX_RDS_INFO_FIELD_MAX 8 /* 4 Group * 2 Bytes */
/* RX RDS data format */
struct fm_rdsdata_format {
union {
struct {
u8 buff[FM_RX_RDS_INFO_FIELD_MAX];
} groupdatabuff;
struct {
u16 pidata;
u8 blk_b[2];
u8 blk_c[2];
u8 blk_d[2];
} groupgeneral;
struct {
u16 pidata;
u8 blk_b[2];
u8 af[2];
u8 ps[2];
} group0A;
struct {
u16 pi[2];
u8 blk_b[2];
u8 ps[2];
} group0B;
} data;
};
/* FM region (Europe/US, Japan) info */
struct region_info {
u32 chanl_space;
u32 bot_freq;
u32 top_freq;
u8 fm_band;
};
struct fmdev;
typedef void (*int_handler_prototype) (struct fmdev *);
/* FM Interrupt processing related info */
struct fm_irq {
u8 stage;
u16 flag; /* FM interrupt flag */
u16 mask; /* FM interrupt mask */
/* Interrupt process timeout handler */
struct timer_list timer;
u8 retry;
int_handler_prototype *handlers;
};
/* RDS info */
struct fm_rds {
u8 flag; /* RX RDS on/off status */
u8 last_blk_idx; /* Last received RDS block */
/* RDS buffer */
wait_queue_head_t read_queue;
u32 buf_size; /* Size is always multiple of 3 */
u32 wr_idx;
u32 rd_idx;
u8 *buff;
};
#define FM_RDS_MAX_AF_LIST 25
/*
* Current RX channel Alternate Frequency cache.
* This info is used to switch to other freq (AF)
* when current channel signal strength is below RSSI threshold.
*/
struct tuned_station_info {
u16 picode;
u32 af_cache[FM_RDS_MAX_AF_LIST];
u8 afcache_size;
u8 af_list_max;
};
/* FM RX mode info */
struct fm_rx {
struct region_info region; /* Current selected band */
u32 freq; /* Current RX frquency */
u8 mute_mode; /* Current mute mode */
u8 deemphasis_mode; /* Current deemphasis mode */
/* RF dependent soft mute mode */
u8 rf_depend_mute;
u16 volume; /* Current volume level */
u16 rssi_threshold; /* Current RSSI threshold level */
/* Holds the index of the current AF jump */
u8 afjump_idx;
/* Will hold the frequency before the jump */
u32 freq_before_jump;
u8 rds_mode; /* RDS operation mode (RDS/RDBS) */
u8 af_mode; /* Alternate frequency on/off */
struct tuned_station_info stat_info;
struct fm_rds rds;
};
#define FMTX_RDS_TXT_STR_SIZE 25
/*
* FM TX RDS data
*
* @ text_type: is the text following PS or RT
* @ text: radio text string which could either be PS or RT
* @ af_freq: alternate frequency for Tx
* TODO: to be declared in application
*/
struct tx_rds {
u8 text_type;
u8 text[FMTX_RDS_TXT_STR_SIZE];
u8 flag;
u32 af_freq;
};
/*
* FM TX global data
*
* @ pwr_lvl: Power Level of the Transmission from mixer control
* @ xmit_state: Transmission state = Updated locally upon Start/Stop
* @ audio_io: i2S/Analog
* @ tx_frq: Transmission frequency
*/
struct fmtx_data {
u8 pwr_lvl;
u8 xmit_state;
u8 audio_io;
u8 region;
u16 aud_mode;
u32 preemph;
u32 tx_frq;
struct tx_rds rds;
};
/* FM driver operation structure */
struct fmdev {
struct video_device *radio_dev; /* V4L2 video device pointer */
struct v4l2_device v4l2_dev; /* V4L2 top level struct */
struct snd_card *card; /* Card which holds FM mixer controls */
u16 asci_id;
spinlock_t rds_buff_lock; /* To protect access to RDS buffer */
spinlock_t resp_skb_lock; /* To protect access to received SKB */
long flag; /* FM driver state machine info */
int streg_cbdata; /* status of ST registration */
struct sk_buff_head rx_q; /* RX queue */
struct work_struct rx_bh_work; /* RX BH Work */
struct sk_buff_head tx_q; /* TX queue */
struct work_struct tx_bh_work; /* TX BH Work */
unsigned long last_tx_jiffies; /* Timestamp of last pkt sent */
atomic_t tx_cnt; /* Number of packets can send at a time */
struct sk_buff *resp_skb; /* Response from the chip */
/* Main task completion handler */
struct completion maintask_comp;
/* Opcode of last command sent to the chip */
u8 pre_op;
/* Handler used for wakeup when response packet is received */
struct completion *resp_comp;
struct fm_irq irq_info;
u8 curr_fmmode; /* Current FM chip mode (TX, RX, OFF) */
struct fm_rx rx; /* FM receiver info */
struct fmtx_data tx_data;
/* V4L2 ctrl framework handler*/
struct v4l2_ctrl_handler ctrl_handler;
/* For core assisted locking */
struct mutex mutex;
};
#endif

1676
drivers/media/radio/wl128x/fmdrv_common.c
View File

File diff suppressed because it is too large Load Diff

389
drivers/media/radio/wl128x/fmdrv_common.h
View File

@ -1,389 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* FM Driver for Connectivity chip of Texas Instruments.
* FM Common module header file
*
* Copyright (C) 2011 Texas Instruments
*/
#ifndef _FMDRV_COMMON_H
#define _FMDRV_COMMON_H
#define FM_ST_REG_TIMEOUT msecs_to_jiffies(6000) /* 6 sec */
#define FM_PKT_LOGICAL_CHAN_NUMBER 0x08 /* Logical channel 8 */
#define REG_RD 0x1
#define REG_WR 0x0
struct fm_reg_table {
u8 opcode;
u8 type;
u8 *name;
};
#define STEREO_GET 0
#define RSSI_LVL_GET 1
#define IF_COUNT_GET 2
#define FLAG_GET 3
#define RDS_SYNC_GET 4
#define RDS_DATA_GET 5
#define FREQ_SET 10
#define AF_FREQ_SET 11
#define MOST_MODE_SET 12
#define MOST_BLEND_SET 13
#define DEMPH_MODE_SET 14
#define SEARCH_LVL_SET 15
#define BAND_SET 16
#define MUTE_STATUS_SET 17
#define RDS_PAUSE_LVL_SET 18
#define RDS_PAUSE_DUR_SET 19
#define RDS_MEM_SET 20
#define RDS_BLK_B_SET 21
#define RDS_MSK_B_SET 22
#define RDS_PI_MASK_SET 23
#define RDS_PI_SET 24
#define RDS_SYSTEM_SET 25
#define INT_MASK_SET 26
#define SEARCH_DIR_SET 27
#define VOLUME_SET 28
#define AUDIO_ENABLE_SET 29
#define PCM_MODE_SET 30
#define I2S_MODE_CONFIG_SET 31
#define POWER_SET 32
#define INTX_CONFIG_SET 33
#define PULL_EN_SET 34
#define HILO_SET 35
#define SWITCH2FREF 36
#define FREQ_DRIFT_REPORT 37
#define PCE_GET 40
#define FIRM_VER_GET 41
#define ASIC_VER_GET 42
#define ASIC_ID_GET 43
#define MAN_ID_GET 44
#define TUNER_MODE_SET 45
#define STOP_SEARCH 46
#define RDS_CNTRL_SET 47
#define WRITE_HARDWARE_REG 100
#define CODE_DOWNLOAD 101
#define RESET 102
#define FM_POWER_MODE 254
#define FM_INTERRUPT 255
/* Transmitter API */
#define CHANL_SET 55
#define CHANL_BW_SET 56
#define REF_SET 57
#define POWER_ENB_SET 90
#define POWER_ATT_SET 58
#define POWER_LEV_SET 59
#define AUDIO_DEV_SET 60
#define PILOT_DEV_SET 61
#define RDS_DEV_SET 62
#define TX_BAND_SET 65
#define PUPD_SET 91
#define AUDIO_IO_SET 63
#define PREMPH_SET 64
#define MONO_SET 66
#define MUTE 92
#define MPX_LMT_ENABLE 67
#define PI_SET 93
#define ECC_SET 69
#define PTY 70
#define AF 71
#define DISPLAY_MODE 74
#define RDS_REP_SET 77
#define RDS_CONFIG_DATA_SET 98
#define RDS_DATA_SET 99
#define RDS_DATA_ENB 94
#define TA_SET 78
#define TP_SET 79
#define DI_SET 80
#define MS_SET 81
#define PS_SCROLL_SPEED 82
#define TX_AUDIO_LEVEL_TEST 96
#define TX_AUDIO_LEVEL_TEST_THRESHOLD 73
#define TX_AUDIO_INPUT_LEVEL_RANGE_SET 54
#define RX_ANTENNA_SELECT 87
#define I2C_DEV_ADDR_SET 86
#define REF_ERR_CALIB_PARAM_SET 88
#define REF_ERR_CALIB_PERIODICITY_SET 89
#define SOC_INT_TRIGGER 52
#define SOC_AUDIO_PATH_SET 83
#define SOC_PCMI_OVERRIDE 84
#define SOC_I2S_OVERRIDE 85
#define RSSI_BLOCK_SCAN_FREQ_SET 95
#define RSSI_BLOCK_SCAN_START 97
#define RSSI_BLOCK_SCAN_DATA_GET 5
#define READ_FMANT_TUNE_VALUE 104
/* SKB helpers */
struct fm_skb_cb {
__u8 fm_op;
struct completion *completion;
};
#define fm_cb(skb) ((struct fm_skb_cb *)(skb->cb))
/* FM Channel-8 command message format */
struct fm_cmd_msg_hdr {
__u8 hdr; /* Logical Channel-8 */
__u8 len; /* Number of bytes follows */
__u8 op; /* FM Opcode */
__u8 rd_wr; /* Read/Write command */
__u8 dlen; /* Length of payload */
} __attribute__ ((packed));
#define FM_CMD_MSG_HDR_SIZE 5 /* sizeof(struct fm_cmd_msg_hdr) */
/* FM Channel-8 event messgage format */
struct fm_event_msg_hdr {
__u8 header; /* Logical Channel-8 */
__u8 len; /* Number of bytes follows */
__u8 status; /* Event status */
__u8 num_fm_hci_cmds; /* Number of pkts the host allowed to send */
__u8 op; /* FM Opcode */
__u8 rd_wr; /* Read/Write command */
__u8 dlen; /* Length of payload */
} __attribute__ ((packed));
#define FM_EVT_MSG_HDR_SIZE 7 /* sizeof(struct fm_event_msg_hdr) */
/* TI's magic number in firmware file */
#define FM_FW_FILE_HEADER_MAGIC 0x42535442
#define FM_ENABLE 1
#define FM_DISABLE 0
/* FLAG_GET register bits */
#define FM_FR_EVENT BIT(0)
#define FM_BL_EVENT BIT(1)
#define FM_RDS_EVENT BIT(2)
#define FM_BBLK_EVENT BIT(3)
#define FM_LSYNC_EVENT BIT(4)
#define FM_LEV_EVENT BIT(5)
#define FM_IFFR_EVENT BIT(6)
#define FM_PI_EVENT BIT(7)
#define FM_PD_EVENT BIT(8)
#define FM_STIC_EVENT BIT(9)
#define FM_MAL_EVENT BIT(10)
#define FM_POW_ENB_EVENT BIT(11)
/*
* Firmware files of FM. ASIC ID and ASIC version will be appened to this,
* later.
*/
#define FM_FMC_FW_FILE_START ("fmc_ch8")
#define FM_RX_FW_FILE_START ("fm_rx_ch8")
#define FM_TX_FW_FILE_START ("fm_tx_ch8")
#define FM_UNDEFINED_FREQ 0xFFFFFFFF
/* Band types */
#define FM_BAND_EUROPE_US 0
#define FM_BAND_JAPAN 1
/* Seek directions */
#define FM_SEARCH_DIRECTION_DOWN 0
#define FM_SEARCH_DIRECTION_UP 1
/* Tunner modes */
#define FM_TUNER_STOP_SEARCH_MODE 0
#define FM_TUNER_PRESET_MODE 1
#define FM_TUNER_AUTONOMOUS_SEARCH_MODE 2
#define FM_TUNER_AF_JUMP_MODE 3
/* Min and Max volume */
#define FM_RX_VOLUME_MIN 0
#define FM_RX_VOLUME_MAX 70
/* Volume gain step */
#define FM_RX_VOLUME_GAIN_STEP 0x370
/* Mute modes */
#define FM_MUTE_ON 0
#define FM_MUTE_OFF 1
#define FM_MUTE_ATTENUATE 2
#define FM_RX_UNMUTE_MODE 0x00
#define FM_RX_RF_DEP_MODE 0x01
#define FM_RX_AC_MUTE_MODE 0x02
#define FM_RX_HARD_MUTE_LEFT_MODE 0x04
#define FM_RX_HARD_MUTE_RIGHT_MODE 0x08
#define FM_RX_SOFT_MUTE_FORCE_MODE 0x10
/* RF dependent mute mode */
#define FM_RX_RF_DEPENDENT_MUTE_ON 1
#define FM_RX_RF_DEPENDENT_MUTE_OFF 0
/* RSSI threshold min and max */
#define FM_RX_RSSI_THRESHOLD_MIN -128
#define FM_RX_RSSI_THRESHOLD_MAX 127
/* Stereo/Mono mode */
#define FM_STEREO_MODE 0
#define FM_MONO_MODE 1
#define FM_STEREO_SOFT_BLEND 1
/* FM RX De-emphasis filter modes */
#define FM_RX_EMPHASIS_FILTER_50_USEC 0
#define FM_RX_EMPHASIS_FILTER_75_USEC 1
/* FM RDS modes */
#define FM_RDS_DISABLE 0
#define FM_RDS_ENABLE 1
#define FM_NO_PI_CODE 0
/* FM and RX RDS block enable/disable */
#define FM_RX_PWR_SET_FM_ON_RDS_OFF 0x1
#define FM_RX_PWR_SET_FM_AND_RDS_BLK_ON 0x3
#define FM_RX_PWR_SET_FM_AND_RDS_BLK_OFF 0x0
/* RX RDS */
#define FM_RX_RDS_FLUSH_FIFO 0x1
#define FM_RX_RDS_FIFO_THRESHOLD 64 /* tuples */
#define FM_RDS_BLK_SIZE 3 /* 3 bytes */
/* RDS block types */
#define FM_RDS_BLOCK_A 0
#define FM_RDS_BLOCK_B 1
#define FM_RDS_BLOCK_C 2
#define FM_RDS_BLOCK_Ctag 3
#define FM_RDS_BLOCK_D 4
#define FM_RDS_BLOCK_E 5
#define FM_RDS_BLK_IDX_A 0
#define FM_RDS_BLK_IDX_B 1
#define FM_RDS_BLK_IDX_C 2
#define FM_RDS_BLK_IDX_D 3
#define FM_RDS_BLK_IDX_UNKNOWN 0xF0
#define FM_RDS_STATUS_ERR_MASK 0x18
/*
* Represents an RDS group type & version.
* There are 15 groups, each group has 2 versions: A and B.
*/
#define FM_RDS_GROUP_TYPE_MASK_0A BIT(0)
#define FM_RDS_GROUP_TYPE_MASK_0B BIT(1)
#define FM_RDS_GROUP_TYPE_MASK_1A BIT(2)
#define FM_RDS_GROUP_TYPE_MASK_1B BIT(3)
#define FM_RDS_GROUP_TYPE_MASK_2A BIT(4)
#define FM_RDS_GROUP_TYPE_MASK_2B BIT(5)
#define FM_RDS_GROUP_TYPE_MASK_3A BIT(6)
#define FM_RDS_GROUP_TYPE_MASK_3B BIT(7)
#define FM_RDS_GROUP_TYPE_MASK_4A BIT(8)
#define FM_RDS_GROUP_TYPE_MASK_4B BIT(9)
#define FM_RDS_GROUP_TYPE_MASK_5A BIT(10)
#define FM_RDS_GROUP_TYPE_MASK_5B BIT(11)
#define FM_RDS_GROUP_TYPE_MASK_6A BIT(12)
#define FM_RDS_GROUP_TYPE_MASK_6B BIT(13)
#define FM_RDS_GROUP_TYPE_MASK_7A BIT(14)
#define FM_RDS_GROUP_TYPE_MASK_7B BIT(15)
#define FM_RDS_GROUP_TYPE_MASK_8A BIT(16)
#define FM_RDS_GROUP_TYPE_MASK_8B BIT(17)
#define FM_RDS_GROUP_TYPE_MASK_9A BIT(18)
#define FM_RDS_GROUP_TYPE_MASK_9B BIT(19)
#define FM_RDS_GROUP_TYPE_MASK_10A BIT(20)
#define FM_RDS_GROUP_TYPE_MASK_10B BIT(21)
#define FM_RDS_GROUP_TYPE_MASK_11A BIT(22)
#define FM_RDS_GROUP_TYPE_MASK_11B BIT(23)
#define FM_RDS_GROUP_TYPE_MASK_12A BIT(24)
#define FM_RDS_GROUP_TYPE_MASK_12B BIT(25)
#define FM_RDS_GROUP_TYPE_MASK_13A BIT(26)
#define FM_RDS_GROUP_TYPE_MASK_13B BIT(27)
#define FM_RDS_GROUP_TYPE_MASK_14A BIT(28)
#define FM_RDS_GROUP_TYPE_MASK_14B BIT(29)
#define FM_RDS_GROUP_TYPE_MASK_15A BIT(30)
#define FM_RDS_GROUP_TYPE_MASK_15B BIT(31)
/* RX Alternate Frequency info */
#define FM_RDS_MIN_AF 1
#define FM_RDS_MAX_AF 204
#define FM_RDS_MAX_AF_JAPAN 140
#define FM_RDS_1_AF_FOLLOWS 225
#define FM_RDS_25_AF_FOLLOWS 249
/* RDS system type (RDS/RBDS) */
#define FM_RDS_SYSTEM_RDS 0
#define FM_RDS_SYSTEM_RBDS 1
/* AF on/off */
#define FM_RX_RDS_AF_SWITCH_MODE_ON 1
#define FM_RX_RDS_AF_SWITCH_MODE_OFF 0
/* Retry count when interrupt process goes wrong */
#define FM_IRQ_TIMEOUT_RETRY_MAX 5 /* 5 times */
/* Audio IO set values */
#define FM_RX_AUDIO_ENABLE_I2S 0x01
#define FM_RX_AUDIO_ENABLE_ANALOG 0x02
#define FM_RX_AUDIO_ENABLE_I2S_AND_ANALOG 0x03
#define FM_RX_AUDIO_ENABLE_DISABLE 0x00
/* HI/LO set values */
#define FM_RX_IFFREQ_TO_HI_SIDE 0x0
#define FM_RX_IFFREQ_TO_LO_SIDE 0x1
#define FM_RX_IFFREQ_HILO_AUTOMATIC 0x2
/*
* Default RX mode configuration. Chip will be configured
* with this default values after loading RX firmware.
*/
#define FM_DEFAULT_RX_VOLUME 10
#define FM_DEFAULT_RSSI_THRESHOLD 3
/* Range for TX power level in units for dB/uV */
#define FM_PWR_LVL_LOW 91
#define FM_PWR_LVL_HIGH 122
/* Chip specific default TX power level value */
#define FM_PWR_LVL_DEF 4
/* FM TX Pre-emphasis filter values */
#define FM_TX_PREEMPH_OFF 1
#define FM_TX_PREEMPH_50US 0
#define FM_TX_PREEMPH_75US 2
/* FM TX antenna impedance values */
#define FM_TX_ANT_IMP_50 0
#define FM_TX_ANT_IMP_200 1
#define FM_TX_ANT_IMP_500 2
/* Functions exported by FM common sub-module */
int fmc_prepare(struct fmdev *);
int fmc_release(struct fmdev *);
void fmc_update_region_info(struct fmdev *, u8);
int fmc_send_cmd(struct fmdev *, u8, u16,
void *, unsigned int, void *, int *);
int fmc_is_rds_data_available(struct fmdev *, struct file *,
struct poll_table_struct *);
int fmc_transfer_rds_from_internal_buff(struct fmdev *, struct file *,
u8 __user *, size_t);
int fmc_set_freq(struct fmdev *, u32);
int fmc_set_mode(struct fmdev *, u8);
int fmc_set_region(struct fmdev *, u8);
int fmc_set_mute_mode(struct fmdev *, u8);
int fmc_set_stereo_mono(struct fmdev *, u16);
int fmc_set_rds_mode(struct fmdev *, u8);
int fmc_get_freq(struct fmdev *, u32 *);
int fmc_get_region(struct fmdev *, u8 *);
int fmc_get_mode(struct fmdev *, u8 *);
/*
* channel spacing
*/
#define FM_CHANNEL_SPACING_50KHZ 1
#define FM_CHANNEL_SPACING_100KHZ 2
#define FM_CHANNEL_SPACING_200KHZ 4
#define FM_FREQ_MUL 50
#endif

820
drivers/media/radio/wl128x/fmdrv_rx.c
View File

@ -1,820 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* FM Driver for Connectivity chip of Texas Instruments.
* This sub-module of FM driver implements FM RX functionality.
*
* Copyright (C) 2011 Texas Instruments
* Author: Raja Mani <raja_mani@ti.com>
* Author: Manjunatha Halli <manjunatha_halli@ti.com>
*/
#include "fmdrv.h"
#include "fmdrv_common.h"
#include "fmdrv_rx.h"
void fm_rx_reset_rds_cache(struct fmdev *fmdev)
{
fmdev->rx.rds.flag = FM_RDS_DISABLE;
fmdev->rx.rds.last_blk_idx = 0;
fmdev->rx.rds.wr_idx = 0;
fmdev->rx.rds.rd_idx = 0;
if (fmdev->rx.af_mode == FM_RX_RDS_AF_SWITCH_MODE_ON)
fmdev->irq_info.mask |= FM_LEV_EVENT;
}
void fm_rx_reset_station_info(struct fmdev *fmdev)
{
fmdev->rx.stat_info.picode = FM_NO_PI_CODE;
fmdev->rx.stat_info.afcache_size = 0;
fmdev->rx.stat_info.af_list_max = 0;
}
int fm_rx_set_freq(struct fmdev *fmdev, u32 freq)
{
unsigned long timeleft;
u16 payload, curr_frq, intr_flag;
u32 curr_frq_in_khz;
u32 resp_len;
int ret;
if (freq < fmdev->rx.region.bot_freq || freq > fmdev->rx.region.top_freq) {
fmerr("Invalid frequency %d\n", freq);
return -EINVAL;
}
/* Set audio enable */
payload = FM_RX_AUDIO_ENABLE_I2S_AND_ANALOG;
ret = fmc_send_cmd(fmdev, AUDIO_ENABLE_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Set hilo to automatic selection */
payload = FM_RX_IFFREQ_HILO_AUTOMATIC;
ret = fmc_send_cmd(fmdev, HILO_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Calculate frequency index and set*/
payload = (freq - fmdev->rx.region.bot_freq) / FM_FREQ_MUL;
ret = fmc_send_cmd(fmdev, FREQ_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Read flags - just to clear any pending interrupts if we had */
ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2, NULL, NULL);
if (ret < 0)
return ret;
/* Enable FR, BL interrupts */
intr_flag = fmdev->irq_info.mask;
fmdev->irq_info.mask = (FM_FR_EVENT | FM_BL_EVENT);
payload = fmdev->irq_info.mask;
ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Start tune */
payload = FM_TUNER_PRESET_MODE;
ret = fmc_send_cmd(fmdev, TUNER_MODE_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
goto exit;
/* Wait for tune ended interrupt */
init_completion(&fmdev->maintask_comp);
timeleft = wait_for_completion_timeout(&fmdev->maintask_comp,
FM_DRV_TX_TIMEOUT);
if (!timeleft) {
fmerr("Timeout(%d sec),didn't get tune ended int\n",
jiffies_to_msecs(FM_DRV_TX_TIMEOUT) / 1000);
ret = -ETIMEDOUT;
goto exit;
}
/* Read freq back to confirm */
ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, 2, &curr_frq, &resp_len);
if (ret < 0)
goto exit;
curr_frq = be16_to_cpu((__force __be16)curr_frq);
curr_frq_in_khz = (fmdev->rx.region.bot_freq + ((u32)curr_frq * FM_FREQ_MUL));
if (curr_frq_in_khz != freq) {
pr_info("Frequency is set to (%d) but requested freq is (%d)\n",
curr_frq_in_khz, freq);
}
/* Update local cache */
fmdev->rx.freq = curr_frq_in_khz;
exit:
/* Re-enable default FM interrupts */
fmdev->irq_info.mask = intr_flag;
payload = fmdev->irq_info.mask;
ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Reset RDS cache and current station pointers */
fm_rx_reset_rds_cache(fmdev);
fm_rx_reset_station_info(fmdev);
return ret;
}
static int fm_rx_set_channel_spacing(struct fmdev *fmdev, u32 spacing)
{
u16 payload;
int ret;
if (spacing > 0 && spacing <= 50000)
spacing = FM_CHANNEL_SPACING_50KHZ;
else if (spacing > 50000 && spacing <= 100000)
spacing = FM_CHANNEL_SPACING_100KHZ;
else
spacing = FM_CHANNEL_SPACING_200KHZ;
/* set channel spacing */
payload = spacing;
ret = fmc_send_cmd(fmdev, CHANL_BW_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
fmdev->rx.region.chanl_space = spacing * FM_FREQ_MUL;
return ret;
}
int fm_rx_seek(struct fmdev *fmdev, u32 seek_upward,
u32 wrap_around, u32 spacing)
{
u32 resp_len;
u16 curr_frq, next_frq, last_frq;
u16 payload, int_reason, intr_flag;
u16 offset, space_idx;
unsigned long timeleft;
int ret;
/* Set channel spacing */
ret = fm_rx_set_channel_spacing(fmdev, spacing);
if (ret < 0) {
fmerr("Failed to set channel spacing\n");
return ret;
}
/* Read the current frequency from chip */
ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL,
sizeof(curr_frq), &curr_frq, &resp_len);
if (ret < 0)
return ret;
curr_frq = be16_to_cpu((__force __be16)curr_frq);
last_frq = (fmdev->rx.region.top_freq - fmdev->rx.region.bot_freq) / FM_FREQ_MUL;
/* Check the offset in order to be aligned to the channel spacing*/
space_idx = fmdev->rx.region.chanl_space / FM_FREQ_MUL;
offset = curr_frq % space_idx;
next_frq = seek_upward ? curr_frq + space_idx /* Seek Up */ :
curr_frq - space_idx /* Seek Down */ ;
/*
* Add or subtract offset in order to stay aligned to the channel
* spacing.
*/
if ((short)next_frq < 0)
next_frq = last_frq - offset;
else if (next_frq > last_frq)
next_frq = 0 + offset;
again:
/* Set calculated next frequency to perform seek */
payload = next_frq;
ret = fmc_send_cmd(fmdev, FREQ_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Set search direction (0:Seek Down, 1:Seek Up) */
payload = (seek_upward ? FM_SEARCH_DIRECTION_UP : FM_SEARCH_DIRECTION_DOWN);
ret = fmc_send_cmd(fmdev, SEARCH_DIR_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Read flags - just to clear any pending interrupts if we had */
ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2, NULL, NULL);
if (ret < 0)
return ret;
/* Enable FR, BL interrupts */
intr_flag = fmdev->irq_info.mask;
fmdev->irq_info.mask = (FM_FR_EVENT | FM_BL_EVENT);
payload = fmdev->irq_info.mask;
ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Start seek */
payload = FM_TUNER_AUTONOMOUS_SEARCH_MODE;
ret = fmc_send_cmd(fmdev, TUNER_MODE_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Wait for tune ended/band limit reached interrupt */
init_completion(&fmdev->maintask_comp);
timeleft = wait_for_completion_timeout(&fmdev->maintask_comp,
FM_DRV_RX_SEEK_TIMEOUT);
if (!timeleft) {
fmerr("Timeout(%d sec),didn't get tune ended int\n",
jiffies_to_msecs(FM_DRV_RX_SEEK_TIMEOUT) / 1000);
return -ENODATA;
}
int_reason = fmdev->irq_info.flag & (FM_TUNE_COMPLETE | FM_BAND_LIMIT);
/* Re-enable default FM interrupts */
fmdev->irq_info.mask = intr_flag;
payload = fmdev->irq_info.mask;
ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
if (int_reason & FM_BL_EVENT) {
if (wrap_around == 0) {
fmdev->rx.freq = seek_upward ?
fmdev->rx.region.top_freq :
fmdev->rx.region.bot_freq;
} else {
fmdev->rx.freq = seek_upward ?
fmdev->rx.region.bot_freq :
fmdev->rx.region.top_freq;
/* Calculate frequency index to write */
next_frq = (fmdev->rx.freq -
fmdev->rx.region.bot_freq) / FM_FREQ_MUL;
goto again;
}
} else {
/* Read freq to know where operation tune operation stopped */
ret = fmc_send_cmd(fmdev, FREQ_SET, REG_RD, NULL, 2,
&curr_frq, &resp_len);
if (ret < 0)
return ret;
curr_frq = be16_to_cpu((__force __be16)curr_frq);
fmdev->rx.freq = (fmdev->rx.region.bot_freq +
((u32)curr_frq * FM_FREQ_MUL));
}
/* Reset RDS cache and current station pointers */
fm_rx_reset_rds_cache(fmdev);
fm_rx_reset_station_info(fmdev);
return ret;
}
int fm_rx_set_volume(struct fmdev *fmdev, u16 vol_to_set)
{
u16 payload;
int ret;
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (vol_to_set > FM_RX_VOLUME_MAX) {
fmerr("Volume is not within(%d-%d) range\n",
FM_RX_VOLUME_MIN, FM_RX_VOLUME_MAX);
return -EINVAL;
}
vol_to_set *= FM_RX_VOLUME_GAIN_STEP;
payload = vol_to_set;
ret = fmc_send_cmd(fmdev, VOLUME_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
fmdev->rx.volume = vol_to_set;
return ret;
}
/* Get volume */
int fm_rx_get_volume(struct fmdev *fmdev, u16 *curr_vol)
{
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (curr_vol == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
*curr_vol = fmdev->rx.volume / FM_RX_VOLUME_GAIN_STEP;
return 0;
}
/* To get current band's bottom and top frequency */
int fm_rx_get_band_freq_range(struct fmdev *fmdev, u32 *bot_freq, u32 *top_freq)
{
if (bot_freq != NULL)
*bot_freq = fmdev->rx.region.bot_freq;
if (top_freq != NULL)
*top_freq = fmdev->rx.region.top_freq;
return 0;
}
/* Returns current band index (0-Europe/US; 1-Japan) */
void fm_rx_get_region(struct fmdev *fmdev, u8 *region)
{
*region = fmdev->rx.region.fm_band;
}
/* Sets band (0-Europe/US; 1-Japan) */
int fm_rx_set_region(struct fmdev *fmdev, u8 region_to_set)
{
u16 payload;
u32 new_frq = 0;
int ret;
if (region_to_set != FM_BAND_EUROPE_US &&
region_to_set != FM_BAND_JAPAN) {
fmerr("Invalid band\n");
return -EINVAL;
}
if (fmdev->rx.region.fm_band == region_to_set) {
fmerr("Requested band is already configured\n");
return 0;
}
/* Send cmd to set the band */
payload = (u16)region_to_set;
ret = fmc_send_cmd(fmdev, BAND_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
fmc_update_region_info(fmdev, region_to_set);
/* Check whether current RX frequency is within band boundary */
if (fmdev->rx.freq < fmdev->rx.region.bot_freq)
new_frq = fmdev->rx.region.bot_freq;
else if (fmdev->rx.freq > fmdev->rx.region.top_freq)
new_frq = fmdev->rx.region.top_freq;
if (new_frq) {
fmdbg("Current freq is not within band limit boundary,switching to %d KHz\n",
new_frq);
/* Current RX frequency is not in range. So, update it */
ret = fm_rx_set_freq(fmdev, new_frq);
}
return ret;
}
/* Reads current mute mode (Mute Off/On/Attenuate)*/
int fm_rx_get_mute_mode(struct fmdev *fmdev, u8 *curr_mute_mode)
{
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (curr_mute_mode == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
*curr_mute_mode = fmdev->rx.mute_mode;
return 0;
}
static int fm_config_rx_mute_reg(struct fmdev *fmdev)
{
u16 payload, muteval;
int ret;
muteval = 0;
switch (fmdev->rx.mute_mode) {
case FM_MUTE_ON:
muteval = FM_RX_AC_MUTE_MODE;
break;
case FM_MUTE_OFF:
muteval = FM_RX_UNMUTE_MODE;
break;
case FM_MUTE_ATTENUATE:
muteval = FM_RX_SOFT_MUTE_FORCE_MODE;
break;
}
if (fmdev->rx.rf_depend_mute == FM_RX_RF_DEPENDENT_MUTE_ON)
muteval |= FM_RX_RF_DEP_MODE;
else
muteval &= ~FM_RX_RF_DEP_MODE;
payload = muteval;
ret = fmc_send_cmd(fmdev, MUTE_STATUS_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
return 0;
}
/* Configures mute mode (Mute Off/On/Attenuate) */
int fm_rx_set_mute_mode(struct fmdev *fmdev, u8 mute_mode_toset)
{
u8 org_state;
int ret;
if (fmdev->rx.mute_mode == mute_mode_toset)
return 0;
org_state = fmdev->rx.mute_mode;
fmdev->rx.mute_mode = mute_mode_toset;
ret = fm_config_rx_mute_reg(fmdev);
if (ret < 0) {
fmdev->rx.mute_mode = org_state;
return ret;
}
return 0;
}
/* Gets RF dependent soft mute mode enable/disable status */
int fm_rx_get_rfdepend_softmute(struct fmdev *fmdev, u8 *curr_mute_mode)
{
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (curr_mute_mode == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
*curr_mute_mode = fmdev->rx.rf_depend_mute;
return 0;
}
/* Sets RF dependent soft mute mode */
int fm_rx_set_rfdepend_softmute(struct fmdev *fmdev, u8 rfdepend_mute)
{
u8 org_state;
int ret;
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (rfdepend_mute != FM_RX_RF_DEPENDENT_MUTE_ON &&
rfdepend_mute != FM_RX_RF_DEPENDENT_MUTE_OFF) {
fmerr("Invalid RF dependent soft mute\n");
return -EINVAL;
}
if (fmdev->rx.rf_depend_mute == rfdepend_mute)
return 0;
org_state = fmdev->rx.rf_depend_mute;
fmdev->rx.rf_depend_mute = rfdepend_mute;
ret = fm_config_rx_mute_reg(fmdev);
if (ret < 0) {
fmdev->rx.rf_depend_mute = org_state;
return ret;
}
return 0;
}
/* Returns the signal strength level of current channel */
int fm_rx_get_rssi_level(struct fmdev *fmdev, u16 *rssilvl)
{
__be16 curr_rssi_lel;
u32 resp_len;
int ret;
if (rssilvl == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
/* Read current RSSI level */
ret = fmc_send_cmd(fmdev, RSSI_LVL_GET, REG_RD, NULL, 2,
&curr_rssi_lel, &resp_len);
if (ret < 0)
return ret;
*rssilvl = be16_to_cpu(curr_rssi_lel);
return 0;
}
/*
* Sets the signal strength level that once reached
* will stop the auto search process
*/
int fm_rx_set_rssi_threshold(struct fmdev *fmdev, short rssi_lvl_toset)
{
u16 payload;
int ret;
if (rssi_lvl_toset < FM_RX_RSSI_THRESHOLD_MIN ||
rssi_lvl_toset > FM_RX_RSSI_THRESHOLD_MAX) {
fmerr("Invalid RSSI threshold level\n");
return -EINVAL;
}
payload = (u16)rssi_lvl_toset;
ret = fmc_send_cmd(fmdev, SEARCH_LVL_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
fmdev->rx.rssi_threshold = rssi_lvl_toset;
return 0;
}
/* Returns current RX RSSI threshold value */
int fm_rx_get_rssi_threshold(struct fmdev *fmdev, short *curr_rssi_lvl)
{
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (curr_rssi_lvl == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
*curr_rssi_lvl = fmdev->rx.rssi_threshold;
return 0;
}
/* Sets RX stereo/mono modes */
int fm_rx_set_stereo_mono(struct fmdev *fmdev, u16 mode)
{
u16 payload;
int ret;
if (mode != FM_STEREO_MODE && mode != FM_MONO_MODE) {
fmerr("Invalid mode\n");
return -EINVAL;
}
/* Set stereo/mono mode */
payload = (u16)mode;
ret = fmc_send_cmd(fmdev, MOST_MODE_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Set stereo blending mode */
payload = FM_STEREO_SOFT_BLEND;
ret = fmc_send_cmd(fmdev, MOST_BLEND_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
return 0;
}
/* Gets current RX stereo/mono mode */
int fm_rx_get_stereo_mono(struct fmdev *fmdev, u16 *mode)
{
__be16 curr_mode;
u32 resp_len;
int ret;
if (mode == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
ret = fmc_send_cmd(fmdev, MOST_MODE_SET, REG_RD, NULL, 2,
&curr_mode, &resp_len);
if (ret < 0)
return ret;
*mode = be16_to_cpu(curr_mode);
return 0;
}
/* Choose RX de-emphasis filter mode (50us/75us) */
int fm_rx_set_deemphasis_mode(struct fmdev *fmdev, u16 mode)
{
u16 payload;
int ret;
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (mode != FM_RX_EMPHASIS_FILTER_50_USEC &&
mode != FM_RX_EMPHASIS_FILTER_75_USEC) {
fmerr("Invalid rx de-emphasis mode (%d)\n", mode);
return -EINVAL;
}
payload = mode;
ret = fmc_send_cmd(fmdev, DEMPH_MODE_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
fmdev->rx.deemphasis_mode = mode;
return 0;
}
/* Gets current RX de-emphasis filter mode */
int fm_rx_get_deemph_mode(struct fmdev *fmdev, u16 *curr_deemphasis_mode)
{
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (curr_deemphasis_mode == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
*curr_deemphasis_mode = fmdev->rx.deemphasis_mode;
return 0;
}
/* Enable/Disable RX RDS */
int fm_rx_set_rds_mode(struct fmdev *fmdev, u8 rds_en_dis)
{
u16 payload;
int ret;
if (rds_en_dis != FM_RDS_ENABLE && rds_en_dis != FM_RDS_DISABLE) {
fmerr("Invalid rds option\n");
return -EINVAL;
}
if (rds_en_dis == FM_RDS_ENABLE
&& fmdev->rx.rds.flag == FM_RDS_DISABLE) {
/* Turn on RX RDS and RDS circuit */
payload = FM_RX_PWR_SET_FM_AND_RDS_BLK_ON;
ret = fmc_send_cmd(fmdev, POWER_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Clear and reset RDS FIFO */
payload = FM_RX_RDS_FLUSH_FIFO;
ret = fmc_send_cmd(fmdev, RDS_CNTRL_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Read flags - just to clear any pending interrupts. */
ret = fmc_send_cmd(fmdev, FLAG_GET, REG_RD, NULL, 2,
NULL, NULL);
if (ret < 0)
return ret;
/* Set RDS FIFO threshold value */
payload = FM_RX_RDS_FIFO_THRESHOLD;
ret = fmc_send_cmd(fmdev, RDS_MEM_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Enable RDS interrupt */
fmdev->irq_info.mask |= FM_RDS_EVENT;
payload = fmdev->irq_info.mask;
ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0) {
fmdev->irq_info.mask &= ~FM_RDS_EVENT;
return ret;
}
/* Update our local flag */
fmdev->rx.rds.flag = FM_RDS_ENABLE;
} else if (rds_en_dis == FM_RDS_DISABLE
&& fmdev->rx.rds.flag == FM_RDS_ENABLE) {
/* Turn off RX RDS */
payload = FM_RX_PWR_SET_FM_ON_RDS_OFF;
ret = fmc_send_cmd(fmdev, POWER_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Reset RDS pointers */
fmdev->rx.rds.last_blk_idx = 0;
fmdev->rx.rds.wr_idx = 0;
fmdev->rx.rds.rd_idx = 0;
fm_rx_reset_station_info(fmdev);
/* Update RDS local cache */
fmdev->irq_info.mask &= ~(FM_RDS_EVENT);
fmdev->rx.rds.flag = FM_RDS_DISABLE;
}
return 0;
}
/* Returns current RX RDS enable/disable status */
int fm_rx_get_rds_mode(struct fmdev *fmdev, u8 *curr_rds_en_dis)
{
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (curr_rds_en_dis == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
*curr_rds_en_dis = fmdev->rx.rds.flag;
return 0;
}
/* Sets RDS operation mode (RDS/RDBS) */
int fm_rx_set_rds_system(struct fmdev *fmdev, u8 rds_mode)
{
u16 payload;
int ret;
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (rds_mode != FM_RDS_SYSTEM_RDS && rds_mode != FM_RDS_SYSTEM_RBDS) {
fmerr("Invalid rds mode\n");
return -EINVAL;
}
/* Set RDS operation mode */
payload = (u16)rds_mode;
ret = fmc_send_cmd(fmdev, RDS_SYSTEM_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
fmdev->rx.rds_mode = rds_mode;
return 0;
}
/* Configures Alternate Frequency switch mode */
int fm_rx_set_af_switch(struct fmdev *fmdev, u8 af_mode)
{
u16 payload;
int ret;
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (af_mode != FM_RX_RDS_AF_SWITCH_MODE_ON &&
af_mode != FM_RX_RDS_AF_SWITCH_MODE_OFF) {
fmerr("Invalid af mode\n");
return -EINVAL;
}
/* Enable/disable low RSSI interrupt based on af_mode */
if (af_mode == FM_RX_RDS_AF_SWITCH_MODE_ON)
fmdev->irq_info.mask |= FM_LEV_EVENT;
else
fmdev->irq_info.mask &= ~FM_LEV_EVENT;
payload = fmdev->irq_info.mask;
ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
fmdev->rx.af_mode = af_mode;
return 0;
}
/* Returns Alternate Frequency switch status */
int fm_rx_get_af_switch(struct fmdev *fmdev, u8 *af_mode)
{
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
if (af_mode == NULL) {
fmerr("Invalid memory\n");
return -ENOMEM;
}
*af_mode = fmdev->rx.af_mode;
return 0;
}

45
drivers/media/radio/wl128x/fmdrv_rx.h
View File

@ -1,45 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* FM Driver for Connectivity chip of Texas Instruments.
* FM RX module header.
*
* Copyright (C) 2011 Texas Instruments
*/
#ifndef _FMDRV_RX_H
#define _FMDRV_RX_H
int fm_rx_set_freq(struct fmdev *, u32);
int fm_rx_set_mute_mode(struct fmdev *, u8);
int fm_rx_set_stereo_mono(struct fmdev *, u16);
int fm_rx_set_rds_mode(struct fmdev *, u8);
int fm_rx_set_rds_system(struct fmdev *, u8);
int fm_rx_set_volume(struct fmdev *, u16);
int fm_rx_set_rssi_threshold(struct fmdev *, short);
int fm_rx_set_region(struct fmdev *, u8);
int fm_rx_set_rfdepend_softmute(struct fmdev *, u8);
int fm_rx_set_deemphasis_mode(struct fmdev *, u16);
int fm_rx_set_af_switch(struct fmdev *, u8);
void fm_rx_reset_rds_cache(struct fmdev *);
void fm_rx_reset_station_info(struct fmdev *);
int fm_rx_seek(struct fmdev *, u32, u32, u32);
int fm_rx_get_rds_mode(struct fmdev *, u8 *);
int fm_rx_get_mute_mode(struct fmdev *, u8 *);
int fm_rx_get_volume(struct fmdev *, u16 *);
int fm_rx_get_band_freq_range(struct fmdev *,
u32 *, u32 *);
int fm_rx_get_stereo_mono(struct fmdev *, u16 *);
int fm_rx_get_rssi_level(struct fmdev *, u16 *);
int fm_rx_get_rssi_threshold(struct fmdev *, short *);
int fm_rx_get_rfdepend_softmute(struct fmdev *, u8 *);
int fm_rx_get_deemph_mode(struct fmdev *, u16 *);
int fm_rx_get_af_switch(struct fmdev *, u8 *);
void fm_rx_get_region(struct fmdev *, u8 *);
int fm_rx_set_chanl_spacing(struct fmdev *, u8);
int fm_rx_get_chanl_spacing(struct fmdev *, u8 *);
#endif

413
drivers/media/radio/wl128x/fmdrv_tx.c
View File

@ -1,413 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* FM Driver for Connectivity chip of Texas Instruments.
* This sub-module of FM driver implements FM TX functionality.
*
* Copyright (C) 2011 Texas Instruments
*/
#include <linux/delay.h>
#include "fmdrv.h"
#include "fmdrv_common.h"
#include "fmdrv_tx.h"
int fm_tx_set_stereo_mono(struct fmdev *fmdev, u16 mode)
{
u16 payload;
int ret;
if (fmdev->tx_data.aud_mode == mode)
return 0;
fmdbg("stereo mode: %d\n", mode);
/* Set Stereo/Mono mode */
payload = (1 - mode);
ret = fmc_send_cmd(fmdev, MONO_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
fmdev->tx_data.aud_mode = mode;
return ret;
}
static int set_rds_text(struct fmdev *fmdev, u8 *rds_text)
{
u16 payload;
int ret;
ret = fmc_send_cmd(fmdev, RDS_DATA_SET, REG_WR, rds_text,
strlen(rds_text), NULL, NULL);
if (ret < 0)
return ret;
/* Scroll mode */
payload = (u16)0x1;
ret = fmc_send_cmd(fmdev, DISPLAY_MODE, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
return 0;
}
static int set_rds_data_mode(struct fmdev *fmdev, u8 mode)
{
u16 payload;
int ret;
/* Setting unique PI TODO: how unique? */
payload = (u16)0xcafe;
ret = fmc_send_cmd(fmdev, PI_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Set decoder id */
payload = (u16)0xa;
ret = fmc_send_cmd(fmdev, DI_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* TODO: RDS_MODE_GET? */
return 0;
}
static int set_rds_len(struct fmdev *fmdev, u8 type, u16 len)
{
u16 payload;
int ret;
len |= type << 8;
payload = len;
ret = fmc_send_cmd(fmdev, RDS_CONFIG_DATA_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* TODO: LENGTH_GET? */
return 0;
}
int fm_tx_set_rds_mode(struct fmdev *fmdev, u8 rds_en_dis)
{
u16 payload;
int ret;
u8 rds_text[] = "Zoom2\n";
fmdbg("rds_en_dis:%d(E:%d, D:%d)\n", rds_en_dis,
FM_RDS_ENABLE, FM_RDS_DISABLE);
if (rds_en_dis == FM_RDS_ENABLE) {
/* Set RDS length */
set_rds_len(fmdev, 0, strlen(rds_text));
/* Set RDS text */
set_rds_text(fmdev, rds_text);
/* Set RDS mode */
set_rds_data_mode(fmdev, 0x0);
}
/* Send command to enable RDS */
if (rds_en_dis == FM_RDS_ENABLE)
payload = 0x01;
else
payload = 0x00;
ret = fmc_send_cmd(fmdev, RDS_DATA_ENB, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
if (rds_en_dis == FM_RDS_ENABLE) {
/* Set RDS length */
set_rds_len(fmdev, 0, strlen(rds_text));
/* Set RDS text */
set_rds_text(fmdev, rds_text);
}
fmdev->tx_data.rds.flag = rds_en_dis;
return 0;
}
int fm_tx_set_radio_text(struct fmdev *fmdev, u8 *rds_text, u8 rds_type)
{
u16 payload;
int ret;
if (fmdev->curr_fmmode != FM_MODE_TX)
return -EPERM;
fm_tx_set_rds_mode(fmdev, 0);
/* Set RDS length */
set_rds_len(fmdev, rds_type, strlen(rds_text));
/* Set RDS text */
set_rds_text(fmdev, rds_text);
/* Set RDS mode */
set_rds_data_mode(fmdev, 0x0);
payload = 1;
ret = fmc_send_cmd(fmdev, RDS_DATA_ENB, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
return 0;
}
int fm_tx_set_af(struct fmdev *fmdev, u32 af)
{
u16 payload;
int ret;
if (fmdev->curr_fmmode != FM_MODE_TX)
return -EPERM;
fmdbg("AF: %d\n", af);
af = (af - 87500) / 100;
payload = (u16)af;
ret = fmc_send_cmd(fmdev, TA_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
return 0;
}
int fm_tx_set_region(struct fmdev *fmdev, u8 region)
{
u16 payload;
int ret;
if (region != FM_BAND_EUROPE_US && region != FM_BAND_JAPAN) {
fmerr("Invalid band\n");
return -EINVAL;
}
/* Send command to set the band */
payload = (u16)region;
ret = fmc_send_cmd(fmdev, TX_BAND_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
return 0;
}
int fm_tx_set_mute_mode(struct fmdev *fmdev, u8 mute_mode_toset)
{
u16 payload;
int ret;
fmdbg("tx: mute mode %d\n", mute_mode_toset);
payload = mute_mode_toset;
ret = fmc_send_cmd(fmdev, MUTE, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
return 0;
}
/* Set TX Audio I/O */
static int set_audio_io(struct fmdev *fmdev)
{
struct fmtx_data *tx = &fmdev->tx_data;
u16 payload;
int ret;
/* Set Audio I/O Enable */
payload = tx->audio_io;
ret = fmc_send_cmd(fmdev, AUDIO_IO_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* TODO: is audio set? */
return 0;
}
/* Start TX Transmission */
static int enable_xmit(struct fmdev *fmdev, u8 new_xmit_state)
{
struct fmtx_data *tx = &fmdev->tx_data;
unsigned long timeleft;
u16 payload;
int ret;
/* Enable POWER_ENB interrupts */
payload = FM_POW_ENB_EVENT;
ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Set Power Enable */
payload = new_xmit_state;
ret = fmc_send_cmd(fmdev, POWER_ENB_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* Wait for Power Enabled */
init_completion(&fmdev->maintask_comp);
timeleft = wait_for_completion_timeout(&fmdev->maintask_comp,
FM_DRV_TX_TIMEOUT);
if (!timeleft) {
fmerr("Timeout(%d sec),didn't get tune ended interrupt\n",
jiffies_to_msecs(FM_DRV_TX_TIMEOUT) / 1000);
return -ETIMEDOUT;
}
set_bit(FM_CORE_TX_XMITING, &fmdev->flag);
tx->xmit_state = new_xmit_state;
return 0;
}
/* Set TX power level */
int fm_tx_set_pwr_lvl(struct fmdev *fmdev, u8 new_pwr_lvl)
{
u16 payload;
struct fmtx_data *tx = &fmdev->tx_data;
int ret;
if (fmdev->curr_fmmode != FM_MODE_TX)
return -EPERM;
fmdbg("tx: pwr_level_to_set %ld\n", (long int)new_pwr_lvl);
/* If the core isn't ready update global variable */
if (!test_bit(FM_CORE_READY, &fmdev->flag)) {
tx->pwr_lvl = new_pwr_lvl;
return 0;
}
/* Set power level: Application will specify power level value in
* units of dB/uV, whereas range and step are specific to FM chip.
* For TI's WL chips, convert application specified power level value
* to chip specific value by subtracting 122 from it. Refer to TI FM
* data sheet for details.
* */
payload = (FM_PWR_LVL_HIGH - new_pwr_lvl);
ret = fmc_send_cmd(fmdev, POWER_LEV_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
/* TODO: is the power level set? */
tx->pwr_lvl = new_pwr_lvl;
return 0;
}
/*
* Sets FM TX pre-emphasis filter value (OFF, 50us, or 75us)
* Convert V4L2 specified filter values to chip specific filter values.
*/
int fm_tx_set_preemph_filter(struct fmdev *fmdev, u32 preemphasis)
{
struct fmtx_data *tx = &fmdev->tx_data;
u16 payload;
int ret;
if (fmdev->curr_fmmode != FM_MODE_TX)
return -EPERM;
switch (preemphasis) {
case V4L2_PREEMPHASIS_DISABLED:
payload = FM_TX_PREEMPH_OFF;
break;
case V4L2_PREEMPHASIS_50_uS:
payload = FM_TX_PREEMPH_50US;
break;
case V4L2_PREEMPHASIS_75_uS:
payload = FM_TX_PREEMPH_75US;
break;
}
ret = fmc_send_cmd(fmdev, PREMPH_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
tx->preemph = payload;
return ret;
}
/* Get the TX tuning capacitor value.*/
int fm_tx_get_tune_cap_val(struct fmdev *fmdev)
{
u16 curr_val;
u32 resp_len;
int ret;
if (fmdev->curr_fmmode != FM_MODE_TX)
return -EPERM;
ret = fmc_send_cmd(fmdev, READ_FMANT_TUNE_VALUE, REG_RD,
NULL, sizeof(curr_val), &curr_val, &resp_len);
if (ret < 0)
return ret;
curr_val = be16_to_cpu((__force __be16)curr_val);
return curr_val;
}
/* Set TX Frequency */
int fm_tx_set_freq(struct fmdev *fmdev, u32 freq_to_set)
{
struct fmtx_data *tx = &fmdev->tx_data;
u16 payload, chanl_index;
int ret;
if (test_bit(FM_CORE_TX_XMITING, &fmdev->flag)) {
enable_xmit(fmdev, 0);
clear_bit(FM_CORE_TX_XMITING, &fmdev->flag);
}
/* Enable FR, BL interrupts */
payload = (FM_FR_EVENT | FM_BL_EVENT);
ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
tx->tx_frq = (unsigned long)freq_to_set;
fmdbg("tx: freq_to_set %ld\n", (long int)tx->tx_frq);
chanl_index = freq_to_set / 10;
/* Set current tuner channel */
payload = chanl_index;
ret = fmc_send_cmd(fmdev, CHANL_SET, REG_WR, &payload,
sizeof(payload), NULL, NULL);
if (ret < 0)
return ret;
fm_tx_set_pwr_lvl(fmdev, tx->pwr_lvl);
fm_tx_set_preemph_filter(fmdev, tx->preemph);
tx->audio_io = 0x01; /* I2S */
set_audio_io(fmdev);
enable_xmit(fmdev, 0x01); /* Enable transmission */
tx->aud_mode = FM_STEREO_MODE;
tx->rds.flag = FM_RDS_DISABLE;
return 0;
}

24
drivers/media/radio/wl128x/fmdrv_tx.h
View File

@ -1,24 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* FM Driver for Connectivity chip of Texas Instruments.
* FM TX module header.
*
* Copyright (C) 2011 Texas Instruments
*/
#ifndef _FMDRV_TX_H
#define _FMDRV_TX_H
int fm_tx_set_freq(struct fmdev *, u32);
int fm_tx_set_pwr_lvl(struct fmdev *, u8);
int fm_tx_set_region(struct fmdev *, u8);
int fm_tx_set_mute_mode(struct fmdev *, u8);
int fm_tx_set_stereo_mono(struct fmdev *, u16);
int fm_tx_set_rds_mode(struct fmdev *, u8);
int fm_tx_set_radio_text(struct fmdev *, u8 *, u8);
int fm_tx_set_af(struct fmdev *, u32);
int fm_tx_set_preemph_filter(struct fmdev *, u32);
int fm_tx_get_tune_cap_val(struct fmdev *);
#endif

604
drivers/media/radio/wl128x/fmdrv_v4l2.c
View File

@ -1,604 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* FM Driver for Connectivity chip of Texas Instruments.
* This file provides interfaces to V4L2 subsystem.
*
* This module registers with V4L2 subsystem as Radio
* data system interface (/dev/radio). During the registration,
* it will expose two set of function pointers.
*
* 1) File operation related API (open, close, read, write, poll...etc).
* 2) Set of V4L2 IOCTL complaint API.
*
* Copyright (C) 2011 Texas Instruments
* Author: Raja Mani <raja_mani@ti.com>
* Author: Manjunatha Halli <manjunatha_halli@ti.com>
*/
#include <linux/export.h>
#include "fmdrv.h"
#include "fmdrv_v4l2.h"
#include "fmdrv_common.h"
#include "fmdrv_rx.h"
#include "fmdrv_tx.h"
static struct video_device gradio_dev;
static u8 radio_disconnected;
/* -- V4L2 RADIO (/dev/radioX) device file operation interfaces --- */
/* Read RX RDS data */
static ssize_t fm_v4l2_fops_read(struct file *file, char __user * buf,
size_t count, loff_t *ppos)
{
u8 rds_mode;
int ret;
struct fmdev *fmdev;
fmdev = video_drvdata(file);
if (!radio_disconnected) {
fmerr("FM device is already disconnected\n");
return -EIO;
}
if (mutex_lock_interruptible(&fmdev->mutex))
return -ERESTARTSYS;
/* Turn on RDS mode if it is disabled */
ret = fm_rx_get_rds_mode(fmdev, &rds_mode);
if (ret < 0) {
fmerr("Unable to read current rds mode\n");
goto read_unlock;
}
if (rds_mode == FM_RDS_DISABLE) {
ret = fmc_set_rds_mode(fmdev, FM_RDS_ENABLE);
if (ret < 0) {
fmerr("Failed to enable rds mode\n");
goto read_unlock;
}
}
/* Copy RDS data from internal buffer to user buffer */
ret = fmc_transfer_rds_from_internal_buff(fmdev, file, buf, count);
read_unlock:
mutex_unlock(&fmdev->mutex);
return ret;
}
/* Write TX RDS data */
static ssize_t fm_v4l2_fops_write(struct file *file, const char __user * buf,
size_t count, loff_t *ppos)
{
struct tx_rds rds;
int ret;
struct fmdev *fmdev;
ret = copy_from_user(&rds, buf, sizeof(rds));
rds.text[sizeof(rds.text) - 1] = '\0';
fmdbg("(%d)type: %d, text %s, af %d\n",
ret, rds.text_type, rds.text, rds.af_freq);
if (ret)
return -EFAULT;
fmdev = video_drvdata(file);
if (mutex_lock_interruptible(&fmdev->mutex))
return -ERESTARTSYS;
fm_tx_set_radio_text(fmdev, rds.text, rds.text_type);
fm_tx_set_af(fmdev, rds.af_freq);
mutex_unlock(&fmdev->mutex);
return sizeof(rds);
}
static __poll_t fm_v4l2_fops_poll(struct file *file, struct poll_table_struct *pts)
{
int ret;
struct fmdev *fmdev;
fmdev = video_drvdata(file);
mutex_lock(&fmdev->mutex);
ret = fmc_is_rds_data_available(fmdev, file, pts);
mutex_unlock(&fmdev->mutex);
if (ret < 0)
return EPOLLIN | EPOLLRDNORM;
return 0;
}
/*
* Handle open request for "/dev/radioX" device.
* Start with FM RX mode as default.
*/
static int fm_v4l2_fops_open(struct file *file)
{
int ret;
struct fmdev *fmdev = NULL;
/* Don't allow multiple open */
if (radio_disconnected) {
fmerr("FM device is already opened\n");
return -EBUSY;
}
fmdev = video_drvdata(file);
if (mutex_lock_interruptible(&fmdev->mutex))
return -ERESTARTSYS;
ret = fmc_prepare(fmdev);
if (ret < 0) {
fmerr("Unable to prepare FM CORE\n");
goto open_unlock;
}
fmdbg("Load FM RX firmware..\n");
ret = fmc_set_mode(fmdev, FM_MODE_RX);
if (ret < 0) {
fmerr("Unable to load FM RX firmware\n");
goto open_unlock;
}
radio_disconnected = 1;
open_unlock:
mutex_unlock(&fmdev->mutex);
return ret;
}
static int fm_v4l2_fops_release(struct file *file)
{
int ret;
struct fmdev *fmdev;
fmdev = video_drvdata(file);
if (!radio_disconnected) {
fmdbg("FM device is already closed\n");
return 0;
}
mutex_lock(&fmdev->mutex);
ret = fmc_set_mode(fmdev, FM_MODE_OFF);
if (ret < 0) {
fmerr("Unable to turn off the chip\n");
goto release_unlock;
}
ret = fmc_release(fmdev);
if (ret < 0) {
fmerr("FM CORE release failed\n");
goto release_unlock;
}
radio_disconnected = 0;
release_unlock:
mutex_unlock(&fmdev->mutex);
return ret;
}
/* V4L2 RADIO (/dev/radioX) device IOCTL interfaces */
static int fm_v4l2_vidioc_querycap(struct file *file, void *priv,
struct v4l2_capability *capability)
{
strscpy(capability->driver, FM_DRV_NAME, sizeof(capability->driver));
strscpy(capability->card, FM_DRV_CARD_SHORT_NAME,
sizeof(capability->card));
sprintf(capability->bus_info, "UART");
return 0;
}
static int fm_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
{
struct fmdev *fmdev = container_of(ctrl->handler,
struct fmdev, ctrl_handler);
switch (ctrl->id) {
case V4L2_CID_TUNE_ANTENNA_CAPACITOR:
ctrl->val = fm_tx_get_tune_cap_val(fmdev);
break;
default:
fmwarn("%s: Unknown IOCTL: %d\n", __func__, ctrl->id);
break;
}
return 0;
}
static int fm_v4l2_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct fmdev *fmdev = container_of(ctrl->handler,
struct fmdev, ctrl_handler);
switch (ctrl->id) {
case V4L2_CID_AUDIO_VOLUME: /* set volume */
return fm_rx_set_volume(fmdev, (u16)ctrl->val);
case V4L2_CID_AUDIO_MUTE: /* set mute */
return fmc_set_mute_mode(fmdev, (u8)ctrl->val);
case V4L2_CID_TUNE_POWER_LEVEL:
/* set TX power level - ext control */
return fm_tx_set_pwr_lvl(fmdev, (u8)ctrl->val);
case V4L2_CID_TUNE_PREEMPHASIS:
return fm_tx_set_preemph_filter(fmdev, (u8) ctrl->val);
default:
return -EINVAL;
}
}
static int fm_v4l2_vidioc_g_audio(struct file *file, void *priv,
struct v4l2_audio *audio)
{
memset(audio, 0, sizeof(*audio));
strscpy(audio->name, "Radio", sizeof(audio->name));
audio->capability = V4L2_AUDCAP_STEREO;
return 0;
}
static int fm_v4l2_vidioc_s_audio(struct file *file, void *priv,
const struct v4l2_audio *audio)
{
if (audio->index != 0)
return -EINVAL;
return 0;
}
/* Get tuner attributes. If current mode is NOT RX, return error */
static int fm_v4l2_vidioc_g_tuner(struct file *file, void *priv,
struct v4l2_tuner *tuner)
{
struct fmdev *fmdev = video_drvdata(file);
u32 bottom_freq;
u32 top_freq;
u16 stereo_mono_mode;
u16 rssilvl;
int ret;
if (tuner->index != 0)
return -EINVAL;
if (fmdev->curr_fmmode != FM_MODE_RX)
return -EPERM;
ret = fm_rx_get_band_freq_range(fmdev, &bottom_freq, &top_freq);
if (ret != 0)
return ret;
ret = fm_rx_get_stereo_mono(fmdev, &stereo_mono_mode);
if (ret != 0)
return ret;
ret = fm_rx_get_rssi_level(fmdev, &rssilvl);
if (ret != 0)
return ret;
strscpy(tuner->name, "FM", sizeof(tuner->name));
tuner->type = V4L2_TUNER_RADIO;
/* Store rangelow and rangehigh freq in unit of 62.5 Hz */
tuner->rangelow = bottom_freq * 16;
tuner->rangehigh = top_freq * 16;
tuner->rxsubchans = V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO |
((fmdev->rx.rds.flag == FM_RDS_ENABLE) ? V4L2_TUNER_SUB_RDS : 0);
tuner->capability = V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_RDS |
V4L2_TUNER_CAP_LOW |
V4L2_TUNER_CAP_HWSEEK_BOUNDED |
V4L2_TUNER_CAP_HWSEEK_WRAP;
tuner->audmode = (stereo_mono_mode ?
V4L2_TUNER_MODE_MONO : V4L2_TUNER_MODE_STEREO);
/*
* Actual rssi value lies in between -128 to +127.
* Convert this range from 0 to 255 by adding +128
*/
rssilvl += 128;
/*
* Return signal strength value should be within 0 to 65535.
* Find out correct signal radio by multiplying (65535/255) = 257
*/
tuner->signal = rssilvl * 257;
tuner->afc = 0;
return ret;
}
/*
* Set tuner attributes. If current mode is NOT RX, set to RX.
* Currently, we set only audio mode (mono/stereo) and RDS state (on/off).
* Should we set other tuner attributes, too?
*/
static int fm_v4l2_vidioc_s_tuner(struct file *file, void *priv,
const struct v4l2_tuner *tuner)
{
struct fmdev *fmdev = video_drvdata(file);
u16 aud_mode;
u8 rds_mode;
int ret;
if (tuner->index != 0)
return -EINVAL;
aud_mode = (tuner->audmode == V4L2_TUNER_MODE_STEREO) ?
FM_STEREO_MODE : FM_MONO_MODE;
rds_mode = (tuner->rxsubchans & V4L2_TUNER_SUB_RDS) ?
FM_RDS_ENABLE : FM_RDS_DISABLE;
if (fmdev->curr_fmmode != FM_MODE_RX) {
ret = fmc_set_mode(fmdev, FM_MODE_RX);
if (ret < 0) {
fmerr("Failed to set RX mode\n");
return ret;
}
}
ret = fmc_set_stereo_mono(fmdev, aud_mode);
if (ret < 0) {
fmerr("Failed to set RX stereo/mono mode\n");
return ret;
}
ret = fmc_set_rds_mode(fmdev, rds_mode);
if (ret < 0)
fmerr("Failed to set RX RDS mode\n");
return ret;
}
/* Get tuner or modulator radio frequency */
static int fm_v4l2_vidioc_g_freq(struct file *file, void *priv,
struct v4l2_frequency *freq)
{
struct fmdev *fmdev = video_drvdata(file);
int ret;
ret = fmc_get_freq(fmdev, &freq->frequency);
if (ret < 0) {
fmerr("Failed to get frequency\n");
return ret;
}
/* Frequency unit of 62.5 Hz*/
freq->frequency = (u32) freq->frequency * 16;
return 0;
}
/* Set tuner or modulator radio frequency */
static int fm_v4l2_vidioc_s_freq(struct file *file, void *priv,
const struct v4l2_frequency *freq)
{
struct fmdev *fmdev = video_drvdata(file);
/*
* As V4L2_TUNER_CAP_LOW is set 1 user sends the frequency
* in units of 62.5 Hz.
*/
return fmc_set_freq(fmdev, freq->frequency / 16);
}
/* Set hardware frequency seek. If current mode is NOT RX, set it RX. */
static int fm_v4l2_vidioc_s_hw_freq_seek(struct file *file, void *priv,
const struct v4l2_hw_freq_seek *seek)
{
struct fmdev *fmdev = video_drvdata(file);
int ret;
if (file->f_flags & O_NONBLOCK)
return -EWOULDBLOCK;
if (fmdev->curr_fmmode != FM_MODE_RX) {
ret = fmc_set_mode(fmdev, FM_MODE_RX);
if (ret != 0) {
fmerr("Failed to set RX mode\n");
return ret;
}
}
ret = fm_rx_seek(fmdev, seek->seek_upward, seek->wrap_around,
seek->spacing);
if (ret < 0)
fmerr("RX seek failed - %d\n", ret);
return ret;
}
/* Get modulator attributes. If mode is not TX, return no attributes. */
static int fm_v4l2_vidioc_g_modulator(struct file *file, void *priv,
struct v4l2_modulator *mod)
{
struct fmdev *fmdev = video_drvdata(file);
if (mod->index != 0)
return -EINVAL;
if (fmdev->curr_fmmode != FM_MODE_TX)
return -EPERM;
mod->txsubchans = ((fmdev->tx_data.aud_mode == FM_STEREO_MODE) ?
V4L2_TUNER_SUB_STEREO : V4L2_TUNER_SUB_MONO) |
((fmdev->tx_data.rds.flag == FM_RDS_ENABLE) ?
V4L2_TUNER_SUB_RDS : 0);
mod->capability = V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_RDS |
V4L2_TUNER_CAP_LOW;
return 0;
}
/* Set modulator attributes. If mode is not TX, set to TX. */
static int fm_v4l2_vidioc_s_modulator(struct file *file, void *priv,
const struct v4l2_modulator *mod)
{
struct fmdev *fmdev = video_drvdata(file);
u8 rds_mode;
u16 aud_mode;
int ret;
if (mod->index != 0)
return -EINVAL;
if (fmdev->curr_fmmode != FM_MODE_TX) {
ret = fmc_set_mode(fmdev, FM_MODE_TX);
if (ret != 0) {
fmerr("Failed to set TX mode\n");
return ret;
}
}
aud_mode = (mod->txsubchans & V4L2_TUNER_SUB_STEREO) ?
FM_STEREO_MODE : FM_MONO_MODE;
rds_mode = (mod->txsubchans & V4L2_TUNER_SUB_RDS) ?
FM_RDS_ENABLE : FM_RDS_DISABLE;
ret = fm_tx_set_stereo_mono(fmdev, aud_mode);
if (ret < 0) {
fmerr("Failed to set mono/stereo mode for TX\n");
return ret;
}
ret = fm_tx_set_rds_mode(fmdev, rds_mode);
if (ret < 0)
fmerr("Failed to set rds mode for TX\n");
return ret;
}
static const struct v4l2_file_operations fm_drv_fops = {
.owner = THIS_MODULE,
.read = fm_v4l2_fops_read,
.write = fm_v4l2_fops_write,
.poll = fm_v4l2_fops_poll,
.unlocked_ioctl = video_ioctl2,
.open = fm_v4l2_fops_open,
.release = fm_v4l2_fops_release,
};
static const struct v4l2_ctrl_ops fm_ctrl_ops = {
.s_ctrl = fm_v4l2_s_ctrl,
.g_volatile_ctrl = fm_g_volatile_ctrl,
};
static const struct v4l2_ioctl_ops fm_drv_ioctl_ops = {
.vidioc_querycap = fm_v4l2_vidioc_querycap,
.vidioc_g_audio = fm_v4l2_vidioc_g_audio,
.vidioc_s_audio = fm_v4l2_vidioc_s_audio,
.vidioc_g_tuner = fm_v4l2_vidioc_g_tuner,
.vidioc_s_tuner = fm_v4l2_vidioc_s_tuner,
.vidioc_g_frequency = fm_v4l2_vidioc_g_freq,
.vidioc_s_frequency = fm_v4l2_vidioc_s_freq,
.vidioc_s_hw_freq_seek = fm_v4l2_vidioc_s_hw_freq_seek,
.vidioc_g_modulator = fm_v4l2_vidioc_g_modulator,
.vidioc_s_modulator = fm_v4l2_vidioc_s_modulator
};
/* V4L2 RADIO device parent structure */
static const struct video_device fm_viddev_template = {
.fops = &fm_drv_fops,
.ioctl_ops = &fm_drv_ioctl_ops,
.name = FM_DRV_NAME,
.release = video_device_release_empty,
/*
* To ensure both the tuner and modulator ioctls are accessible we
* set the vfl_dir to M2M to indicate this.
*
* It is not really a mem2mem device of course, but it can both receive
* and transmit using the same radio device. It's the only radio driver
* that does this and it should really be split in two radio devices,
* but that would affect applications using this driver.
*/
.vfl_dir = VFL_DIR_M2M,
.device_caps = V4L2_CAP_HW_FREQ_SEEK | V4L2_CAP_TUNER | V4L2_CAP_RADIO |
V4L2_CAP_MODULATOR | V4L2_CAP_AUDIO |
V4L2_CAP_READWRITE | V4L2_CAP_RDS_CAPTURE,
};
int fm_v4l2_init_video_device(struct fmdev *fmdev, int radio_nr)
{
struct v4l2_ctrl *ctrl;
int ret;
strscpy(fmdev->v4l2_dev.name, FM_DRV_NAME,
sizeof(fmdev->v4l2_dev.name));
ret = v4l2_device_register(NULL, &fmdev->v4l2_dev);
if (ret < 0)
return ret;
/* Init mutex for core locking */
mutex_init(&fmdev->mutex);
/* Setup FM driver's V4L2 properties */
gradio_dev = fm_viddev_template;
video_set_drvdata(&gradio_dev, fmdev);
gradio_dev.lock = &fmdev->mutex;
gradio_dev.v4l2_dev = &fmdev->v4l2_dev;
/* Register with V4L2 subsystem as RADIO device */
if (video_register_device(&gradio_dev, VFL_TYPE_RADIO, radio_nr)) {
v4l2_device_unregister(&fmdev->v4l2_dev);
fmerr("Could not register video device\n");
return -ENOMEM;
}
fmdev->radio_dev = &gradio_dev;
/* Register to v4l2 ctrl handler framework */
fmdev->radio_dev->ctrl_handler = &fmdev->ctrl_handler;
ret = v4l2_ctrl_handler_init(&fmdev->ctrl_handler, 5);
if (ret < 0) {
fmerr("(fmdev): Can't init ctrl handler\n");
v4l2_ctrl_handler_free(&fmdev->ctrl_handler);
video_unregister_device(fmdev->radio_dev);
v4l2_device_unregister(&fmdev->v4l2_dev);
return -EBUSY;
}
/*
* Following controls are handled by V4L2 control framework.
* Added in ascending ID order.
*/
v4l2_ctrl_new_std(&fmdev->ctrl_handler, &fm_ctrl_ops,
V4L2_CID_AUDIO_VOLUME, FM_RX_VOLUME_MIN,
FM_RX_VOLUME_MAX, 1, FM_RX_VOLUME_MAX);
v4l2_ctrl_new_std(&fmdev->ctrl_handler, &fm_ctrl_ops,
V4L2_CID_AUDIO_MUTE, 0, 1, 1, 1);
v4l2_ctrl_new_std_menu(&fmdev->ctrl_handler, &fm_ctrl_ops,
V4L2_CID_TUNE_PREEMPHASIS, V4L2_PREEMPHASIS_75_uS,
0, V4L2_PREEMPHASIS_75_uS);
v4l2_ctrl_new_std(&fmdev->ctrl_handler, &fm_ctrl_ops,
V4L2_CID_TUNE_POWER_LEVEL, FM_PWR_LVL_LOW,
FM_PWR_LVL_HIGH, 1, FM_PWR_LVL_HIGH);
ctrl = v4l2_ctrl_new_std(&fmdev->ctrl_handler, &fm_ctrl_ops,
V4L2_CID_TUNE_ANTENNA_CAPACITOR, 0,
255, 1, 255);
if (ctrl)
ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
return 0;
}
void *fm_v4l2_deinit_video_device(void)
{
struct fmdev *fmdev;
fmdev = video_get_drvdata(&gradio_dev);
/* Unregister to v4l2 ctrl handler framework*/
v4l2_ctrl_handler_free(&fmdev->ctrl_handler);
/* Unregister RADIO device from V4L2 subsystem */
video_unregister_device(&gradio_dev);
v4l2_device_unregister(&fmdev->v4l2_dev);
return fmdev;
}

20
drivers/media/radio/wl128x/fmdrv_v4l2.h
View File

@ -1,20 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* FM Driver for Connectivity chip of Texas Instruments.
*
* FM V4L2 module header.
*
* Copyright (C) 2011 Texas Instruments
*/
#ifndef _FMDRV_V4L2_H
#define _FMDRV_V4L2_H
#include <media/v4l2-ioctl.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ctrls.h>
int fm_v4l2_init_video_device(struct fmdev *, int);
void *fm_v4l2_deinit_video_device(void);
#endif

4
drivers/media/rc/iguanair.c
View File

@ -194,8 +194,10 @@ static int iguanair_send(struct iguanair *ir, unsigned size)
if (rc)
return rc;
if (wait_for_completion_timeout(&ir->completion, TIMEOUT) == 0)
if (wait_for_completion_timeout(&ir->completion, TIMEOUT) == 0) {
usb_kill_urb(ir->urb_out);
return -ETIMEDOUT;
}
return rc;
}

2
drivers/media/rc/imon_raw.c
View File

@ -37,7 +37,7 @@ static void imon_ir_data(struct imon *imon)
if (packet_no == 0xff)
return;
dev_dbg(imon->dev, "data: %*ph", 8, imon->ir_buf);
dev_dbg(imon->dev, "data: %8ph", imon->ir_buf);
/*
* Only the first 5 bytes contain IR data. Right shift so we move

5
drivers/media/rc/mceusb.c
View File

@ -28,7 +28,6 @@
#include <linux/workqueue.h>
#include <linux/usb.h>
#include <linux/usb/input.h>
#include <linux/pm_wakeup.h>
#include <media/rc-core.h>
#define DRIVER_VERSION "1.95"
@ -658,8 +657,8 @@ static void mceusb_dev_printdata(struct mceusb_dev *ir, u8 *buf, int buf_len,
if (len == 2)
dev_dbg(dev, "Get hw/sw rev?");
else
dev_dbg(dev, "hw/sw rev %*ph",
4, &buf[offset + 2]);
dev_dbg(dev, "hw/sw rev %4ph",
&buf[offset + 2]);
break;
case MCE_CMD_RESUME:
dev_dbg(dev, "Device resume requested");

64
drivers/media/tuners/fc0013.c
View File

@ -112,70 +112,6 @@ static int fc0013_sleep(struct dvb_frontend *fe)
return 0;
}
int fc0013_rc_cal_add(struct dvb_frontend *fe, int rc_val)
{
struct fc0013_priv *priv = fe->tuner_priv;
int ret;
u8 rc_cal;
int val;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
/* push rc_cal value, get rc_cal value */
ret = fc0013_writereg(priv, 0x10, 0x00);
if (ret)
goto error_out;
/* get rc_cal value */
ret = fc0013_readreg(priv, 0x10, &rc_cal);
if (ret)
goto error_out;
rc_cal &= 0x0f;
val = (int)rc_cal + rc_val;
/* forcing rc_cal */
ret = fc0013_writereg(priv, 0x0d, 0x11);
if (ret)
goto error_out;
/* modify rc_cal value */
if (val > 15)
ret = fc0013_writereg(priv, 0x10, 0x0f);
else if (val < 0)
ret = fc0013_writereg(priv, 0x10, 0x00);
else
ret = fc0013_writereg(priv, 0x10, (u8)val);
error_out:
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
return ret;
}
EXPORT_SYMBOL(fc0013_rc_cal_add);
int fc0013_rc_cal_reset(struct dvb_frontend *fe)
{
struct fc0013_priv *priv = fe->tuner_priv;
int ret;
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
ret = fc0013_writereg(priv, 0x0d, 0x01);
if (!ret)
ret = fc0013_writereg(priv, 0x10, 0x00);
if (fe->ops.i2c_gate_ctrl)
fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
return ret;
}
EXPORT_SYMBOL(fc0013_rc_cal_reset);
static int fc0013_set_vhf_track(struct fc0013_priv *priv, u32 freq)
{
int ret;

11
drivers/media/tuners/fc0013.h
View File

@ -16,8 +16,6 @@ extern struct dvb_frontend *fc0013_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
u8 i2c_address, int dual_master,
enum fc001x_xtal_freq xtal_freq);
extern int fc0013_rc_cal_add(struct dvb_frontend *fe, int rc_val);
extern int fc0013_rc_cal_reset(struct dvb_frontend *fe);
#else
static inline struct dvb_frontend *fc0013_attach(struct dvb_frontend *fe,
struct i2c_adapter *i2c,
@ -28,15 +26,6 @@ static inline struct dvb_frontend *fc0013_attach(struct dvb_frontend *fe,
return NULL;
}
static inline int fc0013_rc_cal_add(struct dvb_frontend *fe, int rc_val)
{
return 0;
}
static inline int fc0013_rc_cal_reset(struct dvb_frontend *fe)
{
return 0;
}
#endif
#endif

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