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clk: at91: sckc: Use SCKC_{TD, MD}_SLCK IDs for clk32k clocks

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Use the newly introduced macros instead of raw numbers. With this the code
is a bit easier to understand.

Reviewed-by: Alexander Dahl <ada@thorsis.com>
Link: https://lore.kernel.org/r/20240826173116.3628337-3-claudiu.beznea@tuxon.dev
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
This commit is contained in:
Claudiu Beznea 2024-08-26 20:31:15 +03:00
parent d87daa1853
commit 802244fae1
1 changed files with 13 additions and 11 deletions
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24
drivers/clk/at91/sckc.c
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@ -12,6 +12,8 @@
#include <linux/of_address.h>
#include <linux/io.h>
#include <dt-bindings/clock/at91.h>
#define SLOW_CLOCK_FREQ 32768
#define SLOWCK_SW_CYCLES 5
#define SLOWCK_SW_TIME_USEC ((SLOWCK_SW_CYCLES * USEC_PER_SEC) / \
@ -470,7 +472,7 @@ static void __init of_sam9x60_sckc_setup(struct device_node *np)
{
void __iomem *regbase = of_iomap(np, 0);
struct clk_hw_onecell_data *clk_data;
struct clk_hw *slow_rc, *slow_osc;
struct clk_hw *slow_rc, *slow_osc, *hw;
const char *xtal_name;
const struct clk_hw *parent_hws[2];
static struct clk_parent_data parent_data = {
@ -506,19 +508,19 @@ static void __init of_sam9x60_sckc_setup(struct device_node *np)
/* MD_SLCK and TD_SLCK. */
clk_data->num = 2;
clk_data->hws[0] = clk_hw_register_fixed_rate_parent_hw(NULL, "md_slck",
slow_rc,
0, 32768);
if (IS_ERR(clk_data->hws[0]))
hw = clk_hw_register_fixed_rate_parent_hw(NULL, "md_slck", slow_rc,
0, 32768);
if (IS_ERR(hw))
goto clk_data_free;
clk_data->hws[SCKC_MD_SLCK] = hw;
parent_hws[0] = slow_rc;
parent_hws[1] = slow_osc;
clk_data->hws[1] = at91_clk_register_sam9x5_slow(regbase, "td_slck",
parent_hws, 2,
&at91sam9x60_bits);
if (IS_ERR(clk_data->hws[1]))
hw = at91_clk_register_sam9x5_slow(regbase, "td_slck", parent_hws,
2, &at91sam9x60_bits);
if (IS_ERR(hw))
goto unregister_md_slck;
clk_data->hws[SCKC_TD_SLCK] = hw;
ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
if (WARN_ON(ret))
@ -527,9 +529,9 @@ static void __init of_sam9x60_sckc_setup(struct device_node *np)
return;
unregister_td_slck:
at91_clk_unregister_sam9x5_slow(clk_data->hws[1]);
at91_clk_unregister_sam9x5_slow(clk_data->hws[SCKC_TD_SLCK]);
unregister_md_slck:
clk_hw_unregister(clk_data->hws[0]);
clk_hw_unregister(clk_data->hws[SCKC_MD_SLCK]);
clk_data_free:
kfree(clk_data);
unregister_slow_osc: