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[PATCH] EDAC: drivers for AMD 76x and Intel E750x, E752x
Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Alan Cox
Linus Torvalds
parent
715b49ef2d
commit
806c35f505
356
drivers/edac/amd76x_edac.c
Normal file
356
drivers/edac/amd76x_edac.c
Normal file
@ -0,0 +1,356 @@
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/*
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* AMD 76x Memory Controller kernel module
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* (C) 2003 Linux Networx (http://lnxi.com)
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* This file may be distributed under the terms of the
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* GNU General Public License.
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*
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* Written by Thayne Harbaugh
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* Based on work by Dan Hollis <goemon at anime dot net> and others.
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* http://www.anime.net/~goemon/linux-ecc/
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*
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* $Id: edac_amd76x.c,v 1.4.2.5 2005/10/05 00:43:44 dsp_llnl Exp $
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*
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/slab.h>
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#include "edac_mc.h"
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#define AMD76X_NR_CSROWS 8
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#define AMD76X_NR_CHANS 1
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#define AMD76X_NR_DIMMS 4
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/* AMD 76x register addresses - device 0 function 0 - PCI bridge */
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#define AMD76X_ECC_MODE_STATUS 0x48 /* Mode and status of ECC (32b)
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*
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* 31:16 reserved
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* 15:14 SERR enabled: x1=ue 1x=ce
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* 13 reserved
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* 12 diag: disabled, enabled
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* 11:10 mode: dis, EC, ECC, ECC+scrub
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* 9:8 status: x1=ue 1x=ce
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* 7:4 UE cs row
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* 3:0 CE cs row
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*/
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#define AMD76X_DRAM_MODE_STATUS 0x58 /* DRAM Mode and status (32b)
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*
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* 31:26 clock disable 5 - 0
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* 25 SDRAM init
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* 24 reserved
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* 23 mode register service
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* 22:21 suspend to RAM
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* 20 burst refresh enable
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* 19 refresh disable
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* 18 reserved
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* 17:16 cycles-per-refresh
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* 15:8 reserved
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* 7:0 x4 mode enable 7 - 0
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*/
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#define AMD76X_MEM_BASE_ADDR 0xC0 /* Memory base address (8 x 32b)
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*
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* 31:23 chip-select base
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* 22:16 reserved
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* 15:7 chip-select mask
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* 6:3 reserved
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* 2:1 address mode
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* 0 chip-select enable
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*/
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struct amd76x_error_info {
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u32 ecc_mode_status;
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};
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enum amd76x_chips {
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AMD761 = 0,
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AMD762
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};
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struct amd76x_dev_info {
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const char *ctl_name;
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};
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static const struct amd76x_dev_info amd76x_devs[] = {
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[AMD761] = {.ctl_name = "AMD761"},
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[AMD762] = {.ctl_name = "AMD762"},
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};
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/**
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* amd76x_get_error_info - fetch error information
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* @mci: Memory controller
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* @info: Info to fill in
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*
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* Fetch and store the AMD76x ECC status. Clear pending status
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* on the chip so that further errors will be reported
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*/
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static void amd76x_get_error_info (struct mem_ctl_info *mci,
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struct amd76x_error_info *info)
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{
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pci_read_config_dword(mci->pdev, AMD76X_ECC_MODE_STATUS,
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&info->ecc_mode_status);
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if (info->ecc_mode_status & BIT(8))
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pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS,
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(u32) BIT(8), (u32) BIT(8));
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if (info->ecc_mode_status & BIT(9))
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pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS,
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(u32) BIT(9), (u32) BIT(9));
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}
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/**
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* amd76x_process_error_info - Error check
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* @mci: Memory controller
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* @info: Previously fetched information from chip
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* @handle_errors: 1 if we should do recovery
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*
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* Process the chip state and decide if an error has occurred.
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* A return of 1 indicates an error. Also if handle_errors is true
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* then attempt to handle and clean up after the error
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*/
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static int amd76x_process_error_info (struct mem_ctl_info *mci,
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struct amd76x_error_info *info, int handle_errors)
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{
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int error_found;
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u32 row;
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error_found = 0;
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/*
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* Check for an uncorrectable error
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*/
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if (info->ecc_mode_status & BIT(8)) {
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error_found = 1;
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if (handle_errors) {
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row = (info->ecc_mode_status >> 4) & 0xf;
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edac_mc_handle_ue(mci,
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mci->csrows[row].first_page, 0, row,
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mci->ctl_name);
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}
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}
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/*
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* Check for a correctable error
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*/
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if (info->ecc_mode_status & BIT(9)) {
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error_found = 1;
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if (handle_errors) {
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row = info->ecc_mode_status & 0xf;
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edac_mc_handle_ce(mci,
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mci->csrows[row].first_page, 0, 0, row, 0,
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mci->ctl_name);
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}
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}
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return error_found;
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}
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/**
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* amd76x_check - Poll the controller
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* @mci: Memory controller
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*
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* Called by the poll handlers this function reads the status
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* from the controller and checks for errors.
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*/
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static void amd76x_check(struct mem_ctl_info *mci)
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{
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struct amd76x_error_info info;
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debugf3("MC: " __FILE__ ": %s()\n", __func__);
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amd76x_get_error_info(mci, &info);
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amd76x_process_error_info(mci, &info, 1);
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}
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/**
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* amd76x_probe1 - Perform set up for detected device
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* @pdev; PCI device detected
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* @dev_idx: Device type index
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*
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* We have found an AMD76x and now need to set up the memory
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* controller status reporting. We configure and set up the
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* memory controller reporting and claim the device.
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*/
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static int amd76x_probe1(struct pci_dev *pdev, int dev_idx)
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{
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int rc = -ENODEV;
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int index;
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struct mem_ctl_info *mci = NULL;
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enum edac_type ems_modes[] = {
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EDAC_NONE,
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EDAC_EC,
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EDAC_SECDED,
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EDAC_SECDED
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};
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u32 ems;
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u32 ems_mode;
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debugf0("MC: " __FILE__ ": %s()\n", __func__);
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pci_read_config_dword(pdev, AMD76X_ECC_MODE_STATUS, &ems);
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ems_mode = (ems >> 10) & 0x3;
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mci = edac_mc_alloc(0, AMD76X_NR_CSROWS, AMD76X_NR_CHANS);
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if (mci == NULL) {
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rc = -ENOMEM;
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goto fail;
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}
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debugf0("MC: " __FILE__ ": %s(): mci = %p\n", __func__, mci);
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mci->pdev = pci_dev_get(pdev);
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mci->mtype_cap = MEM_FLAG_RDDR;
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mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
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mci->edac_cap = ems_mode ?
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(EDAC_FLAG_EC | EDAC_FLAG_SECDED) : EDAC_FLAG_NONE;
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mci->mod_name = BS_MOD_STR;
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mci->mod_ver = "$Revision: 1.4.2.5 $";
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mci->ctl_name = amd76x_devs[dev_idx].ctl_name;
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mci->edac_check = amd76x_check;
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mci->ctl_page_to_phys = NULL;
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for (index = 0; index < mci->nr_csrows; index++) {
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struct csrow_info *csrow = &mci->csrows[index];
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u32 mba;
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u32 mba_base;
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u32 mba_mask;
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u32 dms;
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/* find the DRAM Chip Select Base address and mask */
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pci_read_config_dword(mci->pdev,
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AMD76X_MEM_BASE_ADDR + (index * 4),
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&mba);
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if (!(mba & BIT(0)))
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continue;
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mba_base = mba & 0xff800000UL;
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mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
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pci_read_config_dword(mci->pdev, AMD76X_DRAM_MODE_STATUS,
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&dms);
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csrow->first_page = mba_base >> PAGE_SHIFT;
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csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
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csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
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csrow->page_mask = mba_mask >> PAGE_SHIFT;
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csrow->grain = csrow->nr_pages << PAGE_SHIFT;
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csrow->mtype = MEM_RDDR;
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csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
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csrow->edac_mode = ems_modes[ems_mode];
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}
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/* clear counters */
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pci_write_bits32(mci->pdev, AMD76X_ECC_MODE_STATUS, (u32) (0x3 << 8),
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(u32) (0x3 << 8));
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if (edac_mc_add_mc(mci)) {
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debugf3("MC: " __FILE__
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": %s(): failed edac_mc_add_mc()\n", __func__);
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goto fail;
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}
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/* get this far and it's successful */
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debugf3("MC: " __FILE__ ": %s(): success\n", __func__);
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return 0;
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fail:
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if (mci) {
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if(mci->pdev)
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pci_dev_put(mci->pdev);
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edac_mc_free(mci);
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}
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return rc;
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}
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/* returns count (>= 0), or negative on error */
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static int __devinit amd76x_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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debugf0("MC: " __FILE__ ": %s()\n", __func__);
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/* don't need to call pci_device_enable() */
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return amd76x_probe1(pdev, ent->driver_data);
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}
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/**
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* amd76x_remove_one - driver shutdown
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* @pdev: PCI device being handed back
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*
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* Called when the driver is unloaded. Find the matching mci
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* structure for the device then delete the mci and free the
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* resources.
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*/
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static void __devexit amd76x_remove_one(struct pci_dev *pdev)
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{
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struct mem_ctl_info *mci;
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debugf0(__FILE__ ": %s()\n", __func__);
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if ((mci = edac_mc_find_mci_by_pdev(pdev)) == NULL)
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return;
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if (edac_mc_del_mc(mci))
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return;
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pci_dev_put(mci->pdev);
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edac_mc_free(mci);
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}
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static const struct pci_device_id amd76x_pci_tbl[] __devinitdata = {
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{PCI_VEND_DEV(AMD, FE_GATE_700C), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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AMD762},
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{PCI_VEND_DEV(AMD, FE_GATE_700E), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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AMD761},
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{0,} /* 0 terminated list. */
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};
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MODULE_DEVICE_TABLE(pci, amd76x_pci_tbl);
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static struct pci_driver amd76x_driver = {
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.name = BS_MOD_STR,
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.probe = amd76x_init_one,
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.remove = __devexit_p(amd76x_remove_one),
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.id_table = amd76x_pci_tbl,
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};
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int __init amd76x_init(void)
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{
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return pci_register_driver(&amd76x_driver);
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}
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static void __exit amd76x_exit(void)
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{
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pci_unregister_driver(&amd76x_driver);
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}
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module_init(amd76x_init);
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module_exit(amd76x_exit);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
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MODULE_DESCRIPTION("MC support for AMD 76x memory controllers");
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1069
drivers/edac/e752x_edac.c
Normal file
1069
drivers/edac/e752x_edac.c
Normal file
File diff suppressed because it is too large
Load Diff
558
drivers/edac/e7xxx_edac.c
Normal file
558
drivers/edac/e7xxx_edac.c
Normal file
@ -0,0 +1,558 @@
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/*
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* Intel e7xxx Memory Controller kernel module
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* (C) 2003 Linux Networx (http://lnxi.com)
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* This file may be distributed under the terms of the
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* GNU General Public License.
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*
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* See "enum e7xxx_chips" below for supported chipsets
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*
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* Written by Thayne Harbaugh
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* Based on work by Dan Hollis <goemon at anime dot net> and others.
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* http://www.anime.net/~goemon/linux-ecc/
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*
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* Contributors:
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* Eric Biederman (Linux Networx)
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* Tom Zimmerman (Linux Networx)
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* Jim Garlick (Lawrence Livermore National Labs)
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* Dave Peterson (Lawrence Livermore National Labs)
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* That One Guy (Some other place)
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* Wang Zhenyu (intel.com)
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*
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* $Id: edac_e7xxx.c,v 1.5.2.9 2005/10/05 00:43:44 dsp_llnl Exp $
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*
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/slab.h>
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#include "edac_mc.h"
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#ifndef PCI_DEVICE_ID_INTEL_7205_0
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#define PCI_DEVICE_ID_INTEL_7205_0 0x255d
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#endif /* PCI_DEVICE_ID_INTEL_7205_0 */
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#ifndef PCI_DEVICE_ID_INTEL_7205_1_ERR
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#define PCI_DEVICE_ID_INTEL_7205_1_ERR 0x2551
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#endif /* PCI_DEVICE_ID_INTEL_7205_1_ERR */
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#ifndef PCI_DEVICE_ID_INTEL_7500_0
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#define PCI_DEVICE_ID_INTEL_7500_0 0x2540
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#endif /* PCI_DEVICE_ID_INTEL_7500_0 */
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#ifndef PCI_DEVICE_ID_INTEL_7500_1_ERR
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#define PCI_DEVICE_ID_INTEL_7500_1_ERR 0x2541
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#endif /* PCI_DEVICE_ID_INTEL_7500_1_ERR */
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#ifndef PCI_DEVICE_ID_INTEL_7501_0
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#define PCI_DEVICE_ID_INTEL_7501_0 0x254c
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#endif /* PCI_DEVICE_ID_INTEL_7501_0 */
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#ifndef PCI_DEVICE_ID_INTEL_7501_1_ERR
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#define PCI_DEVICE_ID_INTEL_7501_1_ERR 0x2541
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#endif /* PCI_DEVICE_ID_INTEL_7501_1_ERR */
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#ifndef PCI_DEVICE_ID_INTEL_7505_0
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#define PCI_DEVICE_ID_INTEL_7505_0 0x2550
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#endif /* PCI_DEVICE_ID_INTEL_7505_0 */
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#ifndef PCI_DEVICE_ID_INTEL_7505_1_ERR
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#define PCI_DEVICE_ID_INTEL_7505_1_ERR 0x2551
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#endif /* PCI_DEVICE_ID_INTEL_7505_1_ERR */
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#define E7XXX_NR_CSROWS 8 /* number of csrows */
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#define E7XXX_NR_DIMMS 8 /* FIXME - is this correct? */
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/* E7XXX register addresses - device 0 function 0 */
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#define E7XXX_DRB 0x60 /* DRAM row boundary register (8b) */
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#define E7XXX_DRA 0x70 /* DRAM row attribute register (8b) */
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/*
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* 31 Device width row 7 0=x8 1=x4
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* 27 Device width row 6
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* 23 Device width row 5
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* 19 Device width row 4
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* 15 Device width row 3
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* 11 Device width row 2
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* 7 Device width row 1
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* 3 Device width row 0
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*/
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#define E7XXX_DRC 0x7C /* DRAM controller mode reg (32b) */
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/*
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* 22 Number channels 0=1,1=2
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* 19:18 DRB Granularity 32/64MB
|
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*/
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#define E7XXX_TOLM 0xC4 /* DRAM top of low memory reg (16b) */
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#define E7XXX_REMAPBASE 0xC6 /* DRAM remap base address reg (16b) */
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#define E7XXX_REMAPLIMIT 0xC8 /* DRAM remap limit address reg (16b) */
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/* E7XXX register addresses - device 0 function 1 */
|
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#define E7XXX_DRAM_FERR 0x80 /* DRAM first error register (8b) */
|
||||
#define E7XXX_DRAM_NERR 0x82 /* DRAM next error register (8b) */
|
||||
#define E7XXX_DRAM_CELOG_ADD 0xA0 /* DRAM first correctable memory */
|
||||
/* error address register (32b) */
|
||||
/*
|
||||
* 31:28 Reserved
|
||||
* 27:6 CE address (4k block 33:12)
|
||||
* 5:0 Reserved
|
||||
*/
|
||||
#define E7XXX_DRAM_UELOG_ADD 0xB0 /* DRAM first uncorrectable memory */
|
||||
/* error address register (32b) */
|
||||
/*
|
||||
* 31:28 Reserved
|
||||
* 27:6 CE address (4k block 33:12)
|
||||
* 5:0 Reserved
|
||||
*/
|
||||
#define E7XXX_DRAM_CELOG_SYNDROME 0xD0 /* DRAM first correctable memory */
|
||||
/* error syndrome register (16b) */
|
||||
|
||||
enum e7xxx_chips {
|
||||
E7500 = 0,
|
||||
E7501,
|
||||
E7505,
|
||||
E7205,
|
||||
};
|
||||
|
||||
|
||||
struct e7xxx_pvt {
|
||||
struct pci_dev *bridge_ck;
|
||||
u32 tolm;
|
||||
u32 remapbase;
|
||||
u32 remaplimit;
|
||||
const struct e7xxx_dev_info *dev_info;
|
||||
};
|
||||
|
||||
|
||||
struct e7xxx_dev_info {
|
||||
u16 err_dev;
|
||||
const char *ctl_name;
|
||||
};
|
||||
|
||||
|
||||
struct e7xxx_error_info {
|
||||
u8 dram_ferr;
|
||||
u8 dram_nerr;
|
||||
u32 dram_celog_add;
|
||||
u16 dram_celog_syndrome;
|
||||
u32 dram_uelog_add;
|
||||
};
|
||||
|
||||
static const struct e7xxx_dev_info e7xxx_devs[] = {
|
||||
[E7500] = {
|
||||
.err_dev = PCI_DEVICE_ID_INTEL_7500_1_ERR,
|
||||
.ctl_name = "E7500"},
|
||||
[E7501] = {
|
||||
.err_dev = PCI_DEVICE_ID_INTEL_7501_1_ERR,
|
||||
.ctl_name = "E7501"},
|
||||
[E7505] = {
|
||||
.err_dev = PCI_DEVICE_ID_INTEL_7505_1_ERR,
|
||||
.ctl_name = "E7505"},
|
||||
[E7205] = {
|
||||
.err_dev = PCI_DEVICE_ID_INTEL_7205_1_ERR,
|
||||
.ctl_name = "E7205"},
|
||||
};
|
||||
|
||||
|
||||
/* FIXME - is this valid for both SECDED and S4ECD4ED? */
|
||||
static inline int e7xxx_find_channel(u16 syndrome)
|
||||
{
|
||||
debugf3("MC: " __FILE__ ": %s()\n", __func__);
|
||||
|
||||
if ((syndrome & 0xff00) == 0)
|
||||
return 0;
|
||||
if ((syndrome & 0x00ff) == 0)
|
||||
return 1;
|
||||
if ((syndrome & 0xf000) == 0 || (syndrome & 0x0f00) == 0)
|
||||
return 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
static unsigned long
|
||||
ctl_page_to_phys(struct mem_ctl_info *mci, unsigned long page)
|
||||
{
|
||||
u32 remap;
|
||||
struct e7xxx_pvt *pvt = (struct e7xxx_pvt *) mci->pvt_info;
|
||||
|
||||
debugf3("MC: " __FILE__ ": %s()\n", __func__);
|
||||
|
||||
if ((page < pvt->tolm) ||
|
||||
((page >= 0x100000) && (page < pvt->remapbase)))
|
||||
return page;
|
||||
remap = (page - pvt->tolm) + pvt->remapbase;
|
||||
if (remap < pvt->remaplimit)
|
||||
return remap;
|
||||
printk(KERN_ERR "Invalid page %lx - out of range\n", page);
|
||||
return pvt->tolm - 1;
|
||||
}
|
||||
|
||||
|
||||
static void process_ce(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
|
||||
{
|
||||
u32 error_1b, page;
|
||||
u16 syndrome;
|
||||
int row;
|
||||
int channel;
|
||||
|
||||
debugf3("MC: " __FILE__ ": %s()\n", __func__);
|
||||
|
||||
/* read the error address */
|
||||
error_1b = info->dram_celog_add;
|
||||
/* FIXME - should use PAGE_SHIFT */
|
||||
page = error_1b >> 6; /* convert the address to 4k page */
|
||||
/* read the syndrome */
|
||||
syndrome = info->dram_celog_syndrome;
|
||||
/* FIXME - check for -1 */
|
||||
row = edac_mc_find_csrow_by_page(mci, page);
|
||||
/* convert syndrome to channel */
|
||||
channel = e7xxx_find_channel(syndrome);
|
||||
edac_mc_handle_ce(mci, page, 0, syndrome, row, channel,
|
||||
"e7xxx CE");
|
||||
}
|
||||
|
||||
|
||||
static void process_ce_no_info(struct mem_ctl_info *mci)
|
||||
{
|
||||
debugf3("MC: " __FILE__ ": %s()\n", __func__);
|
||||
edac_mc_handle_ce_no_info(mci, "e7xxx CE log register overflow");
|
||||
}
|
||||
|
||||
|
||||
static void process_ue(struct mem_ctl_info *mci, struct e7xxx_error_info *info)
|
||||
{
|
||||
u32 error_2b, block_page;
|
||||
int row;
|
||||
|
||||
debugf3("MC: " __FILE__ ": %s()\n", __func__);
|
||||
|
||||
/* read the error address */
|
||||
error_2b = info->dram_uelog_add;
|
||||
/* FIXME - should use PAGE_SHIFT */
|
||||
block_page = error_2b >> 6; /* convert to 4k address */
|
||||
row = edac_mc_find_csrow_by_page(mci, block_page);
|
||||
edac_mc_handle_ue(mci, block_page, 0, row, "e7xxx UE");
|
||||
}
|
||||
|
||||
|
||||
static void process_ue_no_info(struct mem_ctl_info *mci)
|
||||
{
|
||||
debugf3("MC: " __FILE__ ": %s()\n", __func__);
|
||||
edac_mc_handle_ue_no_info(mci, "e7xxx UE log register overflow");
|
||||
}
|
||||
|
||||
|
||||
static void e7xxx_get_error_info (struct mem_ctl_info *mci,
|
||||
struct e7xxx_error_info *info)
|
||||
{
|
||||
struct e7xxx_pvt *pvt;
|
||||
|
||||
pvt = (struct e7xxx_pvt *) mci->pvt_info;
|
||||
pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR,
|
||||
&info->dram_ferr);
|
||||
pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR,
|
||||
&info->dram_nerr);
|
||||
|
||||
if ((info->dram_ferr & 1) || (info->dram_nerr & 1)) {
|
||||
pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
|
||||
&info->dram_celog_add);
|
||||
pci_read_config_word(pvt->bridge_ck,
|
||||
E7XXX_DRAM_CELOG_SYNDROME, &info->dram_celog_syndrome);
|
||||
}
|
||||
|
||||
if ((info->dram_ferr & 2) || (info->dram_nerr & 2))
|
||||
pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
|
||||
&info->dram_uelog_add);
|
||||
|
||||
if (info->dram_ferr & 3)
|
||||
pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03,
|
||||
0x03);
|
||||
|
||||
if (info->dram_nerr & 3)
|
||||
pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03,
|
||||
0x03);
|
||||
}
|
||||
|
||||
|
||||
static int e7xxx_process_error_info (struct mem_ctl_info *mci,
|
||||
struct e7xxx_error_info *info, int handle_errors)
|
||||
{
|
||||
int error_found;
|
||||
|
||||
error_found = 0;
|
||||
|
||||
/* decode and report errors */
|
||||
if (info->dram_ferr & 1) { /* check first error correctable */
|
||||
error_found = 1;
|
||||
|
||||
if (handle_errors)
|
||||
process_ce(mci, info);
|
||||
}
|
||||
|
||||
if (info->dram_ferr & 2) { /* check first error uncorrectable */
|
||||
error_found = 1;
|
||||
|
||||
if (handle_errors)
|
||||
process_ue(mci, info);
|
||||
}
|
||||
|
||||
if (info->dram_nerr & 1) { /* check next error correctable */
|
||||
error_found = 1;
|
||||
|
||||
if (handle_errors) {
|
||||
if (info->dram_ferr & 1)
|
||||
process_ce_no_info(mci);
|
||||
else
|
||||
process_ce(mci, info);
|
||||
}
|
||||
}
|
||||
|
||||
if (info->dram_nerr & 2) { /* check next error uncorrectable */
|
||||
error_found = 1;
|
||||
|
||||
if (handle_errors) {
|
||||
if (info->dram_ferr & 2)
|
||||
process_ue_no_info(mci);
|
||||
else
|
||||
process_ue(mci, info);
|
||||
}
|
||||
}
|
||||
|
||||
return error_found;
|
||||
}
|
||||
|
||||
|
||||
static void e7xxx_check(struct mem_ctl_info *mci)
|
||||
{
|
||||
struct e7xxx_error_info info;
|
||||
|
||||
debugf3("MC: " __FILE__ ": %s()\n", __func__);
|
||||
e7xxx_get_error_info(mci, &info);
|
||||
e7xxx_process_error_info(mci, &info, 1);
|
||||
}
|
||||
|
||||
|
||||
static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
|
||||
{
|
||||
int rc = -ENODEV;
|
||||
int index;
|
||||
u16 pci_data;
|
||||
struct mem_ctl_info *mci = NULL;
|
||||
struct e7xxx_pvt *pvt = NULL;
|
||||
u32 drc;
|
||||
int drc_chan = 1; /* Number of channels 0=1chan,1=2chan */
|
||||
int drc_drbg = 1; /* DRB granularity 0=32mb,1=64mb */
|
||||
int drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
|
||||
u32 dra;
|
||||
unsigned long last_cumul_size;
|
||||
|
||||
|
||||
debugf0("MC: " __FILE__ ": %s(): mci\n", __func__);
|
||||
|
||||
/* need to find out the number of channels */
|
||||
pci_read_config_dword(pdev, E7XXX_DRC, &drc);
|
||||
/* only e7501 can be single channel */
|
||||
if (dev_idx == E7501) {
|
||||
drc_chan = ((drc >> 22) & 0x1);
|
||||
drc_drbg = (drc >> 18) & 0x3;
|
||||
}
|
||||
drc_ddim = (drc >> 20) & 0x3;
|
||||
|
||||
mci = edac_mc_alloc(sizeof(*pvt), E7XXX_NR_CSROWS, drc_chan + 1);
|
||||
|
||||
if (mci == NULL) {
|
||||
rc = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
debugf3("MC: " __FILE__ ": %s(): init mci\n", __func__);
|
||||
|
||||
mci->mtype_cap = MEM_FLAG_RDDR;
|
||||
mci->edac_ctl_cap =
|
||||
EDAC_FLAG_NONE | EDAC_FLAG_SECDED | EDAC_FLAG_S4ECD4ED;
|
||||
/* FIXME - what if different memory types are in different csrows? */
|
||||
mci->mod_name = BS_MOD_STR;
|
||||
mci->mod_ver = "$Revision: 1.5.2.9 $";
|
||||
mci->pdev = pdev;
|
||||
|
||||
debugf3("MC: " __FILE__ ": %s(): init pvt\n", __func__);
|
||||
pvt = (struct e7xxx_pvt *) mci->pvt_info;
|
||||
pvt->dev_info = &e7xxx_devs[dev_idx];
|
||||
pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
|
||||
pvt->dev_info->err_dev,
|
||||
pvt->bridge_ck);
|
||||
if (!pvt->bridge_ck) {
|
||||
printk(KERN_ERR
|
||||
"MC: error reporting device not found:"
|
||||
"vendor %x device 0x%x (broken BIOS?)\n",
|
||||
PCI_VENDOR_ID_INTEL, e7xxx_devs[dev_idx].err_dev);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
debugf3("MC: " __FILE__ ": %s(): more mci init\n", __func__);
|
||||
mci->ctl_name = pvt->dev_info->ctl_name;
|
||||
|
||||
mci->edac_check = e7xxx_check;
|
||||
mci->ctl_page_to_phys = ctl_page_to_phys;
|
||||
|
||||
/* find out the device types */
|
||||
pci_read_config_dword(pdev, E7XXX_DRA, &dra);
|
||||
|
||||
/*
|
||||
* The dram row boundary (DRB) reg values are boundary address
|
||||
* for each DRAM row with a granularity of 32 or 64MB (single/dual
|
||||
* channel operation). DRB regs are cumulative; therefore DRB7 will
|
||||
* contain the total memory contained in all eight rows.
|
||||
*/
|
||||
for (last_cumul_size = index = 0; index < mci->nr_csrows; index++) {
|
||||
u8 value;
|
||||
u32 cumul_size;
|
||||
/* mem_dev 0=x8, 1=x4 */
|
||||
int mem_dev = (dra >> (index * 4 + 3)) & 0x1;
|
||||
struct csrow_info *csrow = &mci->csrows[index];
|
||||
|
||||
pci_read_config_byte(mci->pdev, E7XXX_DRB + index, &value);
|
||||
/* convert a 64 or 32 MiB DRB to a page size. */
|
||||
cumul_size = value << (25 + drc_drbg - PAGE_SHIFT);
|
||||
debugf3("MC: " __FILE__ ": %s(): (%d) cumul_size 0x%x\n",
|
||||
__func__, index, cumul_size);
|
||||
if (cumul_size == last_cumul_size)
|
||||
continue; /* not populated */
|
||||
|
||||
csrow->first_page = last_cumul_size;
|
||||
csrow->last_page = cumul_size - 1;
|
||||
csrow->nr_pages = cumul_size - last_cumul_size;
|
||||
last_cumul_size = cumul_size;
|
||||
csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
|
||||
csrow->mtype = MEM_RDDR; /* only one type supported */
|
||||
csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
|
||||
|
||||
/*
|
||||
* if single channel or x8 devices then SECDED
|
||||
* if dual channel and x4 then S4ECD4ED
|
||||
*/
|
||||
if (drc_ddim) {
|
||||
if (drc_chan && mem_dev) {
|
||||
csrow->edac_mode = EDAC_S4ECD4ED;
|
||||
mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
|
||||
} else {
|
||||
csrow->edac_mode = EDAC_SECDED;
|
||||
mci->edac_cap |= EDAC_FLAG_SECDED;
|
||||
}
|
||||
} else
|
||||
csrow->edac_mode = EDAC_NONE;
|
||||
}
|
||||
|
||||
mci->edac_cap |= EDAC_FLAG_NONE;
|
||||
|
||||
debugf3("MC: " __FILE__ ": %s(): tolm, remapbase, remaplimit\n",
|
||||
__func__);
|
||||
/* load the top of low memory, remap base, and remap limit vars */
|
||||
pci_read_config_word(mci->pdev, E7XXX_TOLM, &pci_data);
|
||||
pvt->tolm = ((u32) pci_data) << 4;
|
||||
pci_read_config_word(mci->pdev, E7XXX_REMAPBASE, &pci_data);
|
||||
pvt->remapbase = ((u32) pci_data) << 14;
|
||||
pci_read_config_word(mci->pdev, E7XXX_REMAPLIMIT, &pci_data);
|
||||
pvt->remaplimit = ((u32) pci_data) << 14;
|
||||
printk("tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
|
||||
pvt->remapbase, pvt->remaplimit);
|
||||
|
||||
/* clear any pending errors, or initial state bits */
|
||||
pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
|
||||
pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
|
||||
|
||||
if (edac_mc_add_mc(mci) != 0) {
|
||||
debugf3("MC: " __FILE__
|
||||
": %s(): failed edac_mc_add_mc()\n",
|
||||
__func__);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* get this far and it's successful */
|
||||
debugf3("MC: " __FILE__ ": %s(): success\n", __func__);
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
if (mci != NULL) {
|
||||
if(pvt != NULL && pvt->bridge_ck)
|
||||
pci_dev_put(pvt->bridge_ck);
|
||||
edac_mc_free(mci);
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* returns count (>= 0), or negative on error */
|
||||
static int __devinit
|
||||
e7xxx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
debugf0("MC: " __FILE__ ": %s()\n", __func__);
|
||||
|
||||
/* wake up and enable device */
|
||||
return pci_enable_device(pdev) ?
|
||||
-EIO : e7xxx_probe1(pdev, ent->driver_data);
|
||||
}
|
||||
|
||||
|
||||
static void __devexit e7xxx_remove_one(struct pci_dev *pdev)
|
||||
{
|
||||
struct mem_ctl_info *mci;
|
||||
struct e7xxx_pvt *pvt;
|
||||
|
||||
debugf0(__FILE__ ": %s()\n", __func__);
|
||||
|
||||
if (((mci = edac_mc_find_mci_by_pdev(pdev)) != 0) &&
|
||||
edac_mc_del_mc(mci)) {
|
||||
pvt = (struct e7xxx_pvt *) mci->pvt_info;
|
||||
pci_dev_put(pvt->bridge_ck);
|
||||
edac_mc_free(mci);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static const struct pci_device_id e7xxx_pci_tbl[] __devinitdata = {
|
||||
{PCI_VEND_DEV(INTEL, 7205_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
||||
E7205},
|
||||
{PCI_VEND_DEV(INTEL, 7500_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
||||
E7500},
|
||||
{PCI_VEND_DEV(INTEL, 7501_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
||||
E7501},
|
||||
{PCI_VEND_DEV(INTEL, 7505_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
||||
E7505},
|
||||
{0,} /* 0 terminated list. */
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(pci, e7xxx_pci_tbl);
|
||||
|
||||
|
||||
static struct pci_driver e7xxx_driver = {
|
||||
.name = BS_MOD_STR,
|
||||
.probe = e7xxx_init_one,
|
||||
.remove = __devexit_p(e7xxx_remove_one),
|
||||
.id_table = e7xxx_pci_tbl,
|
||||
};
|
||||
|
||||
|
||||
int __init e7xxx_init(void)
|
||||
{
|
||||
return pci_register_driver(&e7xxx_driver);
|
||||
}
|
||||
|
||||
|
||||
static void __exit e7xxx_exit(void)
|
||||
{
|
||||
pci_unregister_driver(&e7xxx_driver);
|
||||
}
|
||||
|
||||
module_init(e7xxx_init);
|
||||
module_exit(e7xxx_exit);
|
||||
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh et al\n"
|
||||
"Based on.work by Dan Hollis et al");
|
||||
MODULE_DESCRIPTION("MC support for Intel e7xxx memory controllers");
|
||||
Loading…
Reference in New Issue
Block a user