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drm/radeon/dpm: fix fallback for empty UVD clocks
Some older 6xx-7xx boards didn't always fill in the UVD clocks properly in the UVD power states. This leads to the driver trying to set a 0 clock which results in slow or broken UVD playback. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=69120 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
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@ -726,14 +726,18 @@ static void rs780_parse_pplib_non_clock_info(struct radeon_device *rdev,
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if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
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rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
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rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
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} else if (r600_is_uvd_state(rps->class, rps->class2)) {
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rps->vclk = RS780_DEFAULT_VCLK_FREQ;
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rps->dclk = RS780_DEFAULT_DCLK_FREQ;
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} else {
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rps->vclk = 0;
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rps->dclk = 0;
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}
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if (r600_is_uvd_state(rps->class, rps->class2)) {
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if ((rps->vclk == 0) || (rps->dclk == 0)) {
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rps->vclk = RS780_DEFAULT_VCLK_FREQ;
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rps->dclk = RS780_DEFAULT_DCLK_FREQ;
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}
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}
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if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
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rdev->pm.dpm.boot_ps = rps;
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if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
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@ -2147,14 +2147,18 @@ static void rv7xx_parse_pplib_non_clock_info(struct radeon_device *rdev,
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if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
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rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
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rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
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} else if (r600_is_uvd_state(rps->class, rps->class2)) {
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rps->vclk = RV770_DEFAULT_VCLK_FREQ;
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rps->dclk = RV770_DEFAULT_DCLK_FREQ;
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} else {
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rps->vclk = 0;
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rps->dclk = 0;
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}
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if (r600_is_uvd_state(rps->class, rps->class2)) {
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if ((rps->vclk == 0) || (rps->dclk == 0)) {
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rps->vclk = RV770_DEFAULT_VCLK_FREQ;
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rps->dclk = RV770_DEFAULT_DCLK_FREQ;
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}
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}
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if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
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rdev->pm.dpm.boot_ps = rps;
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if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
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