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drivers/perf: hisi: update the sccl_id/ccl_id for certain HiSilicon platform
For some HiSilicon platform, the originally designed SCCL_ID and CCL_ID are not satisfied with much rich topology when the MT is set, so we extend the SCCL_ID to MPIDR[aff3] and CCL_ID to MPIDR[aff2]. Let's update this for HiSilicon uncore PMU driver. Cc: John Garry <john.garry@huawei.com> Cc: Hanjun Guo <guohanjun@huawei.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will@kernel.org> Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> Signed-off-by: Will Deacon <will@kernel.org>
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@ -15,6 +15,7 @@
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <asm/cputype.h>
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#include <asm/local64.h>
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#include "hisi_uncore_pmu.h"
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@ -338,8 +339,10 @@ void hisi_uncore_pmu_disable(struct pmu *pmu)
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/*
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* Read Super CPU cluster and CPU cluster ID from MPIDR_EL1.
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* If multi-threading is supported, CCL_ID is the low 3-bits in MPIDR[Aff2]
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* and SCCL_ID is the upper 5-bits of Aff2 field; if not, SCCL_ID
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* If multi-threading is supported, On Huawei Kunpeng 920 SoC whose cpu
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* core is tsv110, CCL_ID is the low 3-bits in MPIDR[Aff2] and SCCL_ID
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* is the upper 5-bits of Aff2 field; while for other cpu types, SCCL_ID
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* is in MPIDR[Aff3] and CCL_ID is in MPIDR[Aff2], if not, SCCL_ID
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* is in MPIDR[Aff2] and CCL_ID is in MPIDR[Aff1].
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*/
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static void hisi_read_sccl_and_ccl_id(int *sccl_id, int *ccl_id)
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@ -347,12 +350,19 @@ static void hisi_read_sccl_and_ccl_id(int *sccl_id, int *ccl_id)
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u64 mpidr = read_cpuid_mpidr();
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if (mpidr & MPIDR_MT_BITMASK) {
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int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
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if (read_cpuid_part_number() == HISI_CPU_PART_TSV110) {
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int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
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if (sccl_id)
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*sccl_id = aff2 >> 3;
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if (ccl_id)
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*ccl_id = aff2 & 0x7;
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if (sccl_id)
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*sccl_id = aff2 >> 3;
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if (ccl_id)
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*ccl_id = aff2 & 0x7;
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} else {
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if (sccl_id)
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*sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 3);
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if (ccl_id)
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*ccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
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}
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} else {
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if (sccl_id)
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*sccl_id = MPIDR_AFFINITY_LEVEL(mpidr, 2);
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