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clk: kirkwood: Add support for MV98DX1135

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The 98DX1135 is a switch chip with an integrated CPU. This is similar to
the 98DX4122 except that the core clock speed is fixed to 166Mhz.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Chris Packham 2019-06-18 09:54:58 +12:00 committed by Stephen Boyd
parent 9a042e718f
commit 88aa7af9c1
1 changed files with 17 additions and 0 deletions
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17
drivers/clk/mvebu/kirkwood.c
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@ -185,6 +185,11 @@ static void __init mv88f6180_get_clk_ratio(
}
}
static u32 __init mv98dx1135_get_tclk_freq(void __iomem *sar)
{
return 166666667;
}
static const struct coreclk_soc_desc kirkwood_coreclks = {
.get_tclk_freq = kirkwood_get_tclk_freq,
.get_cpu_freq = kirkwood_get_cpu_freq,
@ -201,6 +206,14 @@ static const struct coreclk_soc_desc mv88f6180_coreclks = {
.num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
};
static const struct coreclk_soc_desc mv98dx1135_coreclks = {
.get_tclk_freq = mv98dx1135_get_tclk_freq,
.get_cpu_freq = kirkwood_get_cpu_freq,
.get_clk_ratio = kirkwood_get_clk_ratio,
.ratios = kirkwood_coreclk_ratios,
.num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
};
/*
* Clock Gating Control
*/
@ -325,6 +338,8 @@ static void __init kirkwood_clk_init(struct device_node *np)
if (of_device_is_compatible(np, "marvell,mv88f6180-core-clock"))
mvebu_coreclk_setup(np, &mv88f6180_coreclks);
else if (of_device_is_compatible(np, "marvell,mv98dx1135-core-clock"))
mvebu_coreclk_setup(np, &mv98dx1135_coreclks);
else
mvebu_coreclk_setup(np, &kirkwood_coreclks);
@ -339,3 +354,5 @@ CLK_OF_DECLARE(kirkwood_clk, "marvell,kirkwood-core-clock",
kirkwood_clk_init);
CLK_OF_DECLARE(mv88f6180_clk, "marvell,mv88f6180-core-clock",
kirkwood_clk_init);
CLK_OF_DECLARE(98dx1135_clk, "marvell,mv98dx1135-core-clock",
kirkwood_clk_init);