Kernel/linux-next
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git synced 2024-12-29 09:12:07 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

spi: fix typo in the comment

Browse Source 
Correctly spelled comments make it easier for the reader to understand
the code.

Replace 'progrom' with 'program' in the comment &
replace 'Recevie' with 'Receive' in the comment &
replace 'receieved' with 'received' in the comment &
replace 'ajacent' with 'adjacent' in the comment &
replace 'trasaction' with 'transaction' in the comment &
replace 'pecularity' with 'peculiarity' in the comment &
replace 'resiter' with 'register' in the comment &
replace 'tansmition' with 'transmission' in the comment &
replace 'Deufult' with 'Default' in the comment &
replace 'tansfer' with 'transfer' in the comment &
replace 'settign' with 'setting' in the comment.

Signed-off-by: Yan Zhen <yanzhen@vivo.com>
Reviewed-by: Andi Shyti <andi.shyti@kernel.org>
Link: https://patch.msgid.link/20240914095213.298256-1-yanzhen@vivo.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Yan Zhen 2024-09-14 17:52:13 +08:00 committed by Mark Brown
parent 9852d85ec9
commit 89980d3a34
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
10 changed files with 11 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/spi/spi-hisi-sfc-v3xx.c
View File

@ -40,7 +40,7 @@
/* Common definition of interrupt bit masks */ /* Common definition of interrupt bit masks */
#define HISI_SFC_V3XX_INT_MASK_ALL (0x1ff) /* all the masks */ #define HISI_SFC_V3XX_INT_MASK_ALL (0x1ff) /* all the masks */
#define HISI_SFC_V3XX_INT_MASK_CPLT BIT(0) /* command execution complete */ #define HISI_SFC_V3XX_INT_MASK_CPLT BIT(0) /* command execution complete */
#define HISI_SFC_V3XX_INT_MASK_PP_ERR BIT(2) /* page progrom error */ #define HISI_SFC_V3XX_INT_MASK_PP_ERR BIT(2) /* page program error */
#define HISI_SFC_V3XX_INT_MASK_IACCES BIT(5) /* error visiting inaccessible/ #define HISI_SFC_V3XX_INT_MASK_IACCES BIT(5) /* error visiting inaccessible/
* protected address * protected address
*/ */

2
drivers/spi/spi-lantiq-ssc.c
View File

@ -139,7 +139,7 @@
#define LTQ_SPI_FGPO_CLROUTN_S 0 #define LTQ_SPI_FGPO_CLROUTN_S 0
#define LTQ_SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */ #define LTQ_SPI_RXREQ_RXCNT_M 0xFFFF /* Receive count value */
#define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Recevie to-do value */ #define LTQ_SPI_RXCNT_TODO_M 0xFFFF /* Receive to-do value */
#define LTQ_SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */ #define LTQ_SPI_IRNEN_TFI BIT(4) /* TX finished interrupt */
#define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ #define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */

4
drivers/spi/spi-mpc52xx-psc.c
View File

@ -107,7 +107,7 @@ static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
struct mpc52xx_psc_spi *mps = spi_controller_get_devdata(spi->controller); struct mpc52xx_psc_spi *mps = spi_controller_get_devdata(spi->controller);
struct mpc52xx_psc __iomem *psc = mps->psc; struct mpc52xx_psc __iomem *psc = mps->psc;
struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo; struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
unsigned rb = 0; /* number of bytes receieved */ unsigned rb = 0; /* number of bytes received */
unsigned sb = 0; /* number of bytes sent */ unsigned sb = 0; /* number of bytes sent */
unsigned char *rx_buf = (unsigned char *)t->rx_buf; unsigned char *rx_buf = (unsigned char *)t->rx_buf;
unsigned char *tx_buf = (unsigned char *)t->tx_buf; unsigned char *tx_buf = (unsigned char *)t->tx_buf;
@ -325,7 +325,7 @@ static int mpc52xx_psc_spi_of_probe(struct platform_device *pdev)
if (IS_ERR(mps->psc)) if (IS_ERR(mps->psc))
return dev_err_probe(dev, PTR_ERR(mps->psc), "could not ioremap I/O port range\n"); return dev_err_probe(dev, PTR_ERR(mps->psc), "could not ioremap I/O port range\n");
/* On the 5200, fifo regs are immediately ajacent to the psc regs */ /* On the 5200, fifo regs are immediately adjacent to the psc regs */
mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc); mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);
mps->irq = platform_get_irq(pdev, 0); mps->irq = platform_get_irq(pdev, 0);

2
drivers/spi/spi-pic32-sqi.c
View File

@ -226,7 +226,7 @@ static irqreturn_t pic32_sqi_isr(int irq, void *dev_id)
if (status & PESQI_PKTCOMP) { if (status & PESQI_PKTCOMP) {
/* mask all interrupts */ /* mask all interrupts */
enable = 0; enable = 0;
/* complete trasaction */ /* complete transaction */
complete(&sqi->xfer_done); complete(&sqi->xfer_done);
} }

2
drivers/spi/spi-pl022.c
View File

@ -899,7 +899,7 @@ static int configure_dma(struct pl022 *pl022)
break; break;
} }
/* SPI pecularity: we need to read and write the same width */ /* SPI peculiarity: we need to read and write the same width */
if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
rx_conf.src_addr_width = tx_conf.dst_addr_width; rx_conf.src_addr_width = tx_conf.dst_addr_width;
if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)

2
drivers/spi/spi-rockchip-sfc.c
View File

@ -111,7 +111,7 @@
#define SFC_VER_4 0x4 #define SFC_VER_4 0x4
#define SFC_VER_5 0x5 #define SFC_VER_5 0x5
/* Delay line controller resiter */ /* Delay line controller register */
#define SFC_DLL_CTRL0 0x3C #define SFC_DLL_CTRL0 0x3C
#define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15) #define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15)
#define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU #define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU

2
drivers/spi/spi-rockchip.c
View File

@ -192,7 +192,7 @@ struct rockchip_spi {
u8 rsd; u8 rsd;
bool target_abort; bool target_abort;
bool cs_inactive; /* spi target tansmition stop when cs inactive */ bool cs_inactive; /* spi target transmission stop when cs inactive */
bool cs_high_supported; /* native CS supports active-high polarity */ bool cs_high_supported; /* native CS supports active-high polarity */
struct spi_transfer *xfer; /* Store xfer temporarily */ struct spi_transfer *xfer; /* Store xfer temporarily */

2
drivers/spi/spi-s3c64xx.c
View File

@ -1353,7 +1353,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev)
pm_runtime_enable(&pdev->dev); pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev); pm_runtime_get_sync(&pdev->dev);
/* Setup Deufult Mode */ /* Setup Default Mode */
s3c64xx_spi_hwinit(sdd); s3c64xx_spi_hwinit(sdd);
spin_lock_init(&sdd->lock); spin_lock_init(&sdd->lock);

2
drivers/spi/spi-sprd.c
View File

@ -728,7 +728,7 @@ static int sprd_spi_setup_transfer(struct spi_device *sdev,
if (ret) if (ret)
return ret; return ret;
/* Set tansfer speed and valid bits */ /* Set transfer speed and valid bits */
sprd_spi_set_speed(ss, t->speed_hz); sprd_spi_set_speed(ss, t->speed_hz);
sprd_spi_set_transfer_bits(ss, bits_per_word); sprd_spi_set_transfer_bits(ss, bits_per_word);

2
drivers/spi/spi-tegra20-slink.c
View File

@ -542,7 +542,7 @@ static int tegra_slink_start_dma_based_transfer(
if (tspi->is_packed) { if (tspi->is_packed) {
val |= SLINK_PACKED; val |= SLINK_PACKED;
tegra_slink_writel(tspi, val, SLINK_DMA_CTL); tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
/* HW need small delay after settign Packed mode */ /* HW need small delay after setting Packed mode */
udelay(1); udelay(1);
} }
tspi->dma_control_reg = val; tspi->dma_control_reg = val;