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MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits.

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CN38XX pass 1 required icache prefetching to be turned off. This chip never
reached production and is long dead. Other processor specific icache settings
are done by the bootloader. Remove these bits from the kernel.

Signed-off-by: Chad Reese <kreese@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/8944/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Chad Reese 2015-01-15 16:11:16 +03:00 committed by Ralf Baechle
parent 726da2f82a
commit 920cda3870
1 changed files with 0 additions and 20 deletions
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20
arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
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@ -37,26 +37,6 @@
# Needed for octeon specific memcpy
or v0, v0, 0x5001
xor v0, v0, 0x1001
# Read the processor ID register
mfc0 v1, CP0_PRID_REG
# Disable instruction prefetching (Octeon Pass1 errata)
or v0, v0, 0x2000
# Skip reenable of prefetching for Octeon Pass1
beq v1, CP0_PRID_OCTEON_PASS1, skip
nop
# Reenable instruction prefetching, not on Pass1
xor v0, v0, 0x2000
# Strip off pass number off of processor id
srl v1, 8
sll v1, 8
# CN30XX needs some extra stuff turned off for better performance
bne v1, CP0_PRID_OCTEON_CN30XX, skip
nop
# CN30XX Use random Icache replacement
or v0, v0, 0x400
# CN30XX Disable instruction prefetching
or v0, v0, 0x2000
skip:
# First clear off CvmCtl[IPPCI] bit and move the performance
# counters interrupt to IRQ 6
dli v1, ~(7 << 7)