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spi: zynq-qspi: Keep the bitfields naming consistent

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Most of the bits/bitfields #define'd in this driver are composed with:
1/ the driver prefix
2/ the name of the register they apply to

Keep the naming consistent by applying this rule to the CONFIG register
internals. These definitions will be used in a following change set.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/r/20191108140744.1734-4-miquel.raynal@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Miquel Raynal 2019-11-08 15:07:40 +01:00 committed by Mark Brown
parent 087622d094
commit 941be72373
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
1 changed files with 6 additions and 6 deletions
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12
drivers/spi/spi-zynq-qspi.c
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@ -60,9 +60,9 @@
* These are the values used in the calculation of baud rate divisor and * These are the values used in the calculation of baud rate divisor and
* setting the slave select. * setting the slave select.
*/ */
#define ZYNQ_QSPI_BAUD_DIV_MAX GENMASK(2, 0) /* Baud rate maximum */ #define ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX GENMASK(2, 0) /* Baud rate maximum */
#define ZYNQ_QSPI_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift in CR */ #define ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT 3 /* Baud rate divisor shift */
#define ZYNQ_QSPI_SS_SHIFT 10 /* Slave Select field shift in CR */ #define ZYNQ_QSPI_CONFIG_PCS 10 /* Peripheral Chip Select */
/* /*
* QSPI Interrupt Registers bit Masks * QSPI Interrupt Registers bit Masks
@ -292,7 +292,7 @@ static void zynq_qspi_chipselect(struct spi_device *spi, bool assert)
/* Select the slave */ /* Select the slave */
config_reg &= ~ZYNQ_QSPI_CONFIG_SSCTRL_MASK; config_reg &= ~ZYNQ_QSPI_CONFIG_SSCTRL_MASK;
config_reg |= (((~(BIT(spi->chip_select))) << config_reg |= (((~(BIT(spi->chip_select))) <<
ZYNQ_QSPI_SS_SHIFT) & ZYNQ_QSPI_CONFIG_PCS) &
ZYNQ_QSPI_CONFIG_SSCTRL_MASK); ZYNQ_QSPI_CONFIG_SSCTRL_MASK);
} else { } else {
config_reg |= ZYNQ_QSPI_CONFIG_SSCTRL_MASK; config_reg |= ZYNQ_QSPI_CONFIG_SSCTRL_MASK;
@ -331,7 +331,7 @@ static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi)
* ---------------- * ----------------
* 111 - divide by 256 * 111 - divide by 256
*/ */
while ((baud_rate_val < ZYNQ_QSPI_BAUD_DIV_MAX) && while ((baud_rate_val < ZYNQ_QSPI_CONFIG_BAUD_DIV_MAX) &&
(clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) > (clk_get_rate(xqspi->refclk) / (2 << baud_rate_val)) >
spi->max_speed_hz) spi->max_speed_hz)
baud_rate_val++; baud_rate_val++;
@ -347,7 +347,7 @@ static int zynq_qspi_config_op(struct zynq_qspi *xqspi, struct spi_device *spi)
config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK; config_reg |= ZYNQ_QSPI_CONFIG_CPOL_MASK;
config_reg &= ~ZYNQ_QSPI_CONFIG_BDRATE_MASK; config_reg &= ~ZYNQ_QSPI_CONFIG_BDRATE_MASK;
config_reg |= (baud_rate_val << ZYNQ_QSPI_BAUD_DIV_SHIFT); config_reg |= (baud_rate_val << ZYNQ_QSPI_CONFIG_BAUD_DIV_SHIFT);
zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg); zynq_qspi_write(xqspi, ZYNQ_QSPI_CONFIG_OFFSET, config_reg);
return 0; return 0;