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drm/amdkfd: disable IOMMUv2 support for KV/CZ
Use the dGPU path instead. There were a lot of platform issues with IOMMU in general on these chips due to windows not enabling IOMMU at the time. The dGPU path has been used for a long time with newer APUs and works fine. This also paves the way to simplify the driver significantly. v2: use the dGPU queue manager functions Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Tested-by: Mike Lothian <mike@fireburn.co.uk> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -233,10 +233,6 @@ static void kfd_device_info_init(struct kfd_dev *kfd,
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asic_type != CHIP_TONGA)
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kfd->device_info.supports_cwsr = true;
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if (asic_type == CHIP_KAVERI ||
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asic_type == CHIP_CARRIZO)
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kfd->device_info.needs_iommu_device = true;
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if (asic_type != CHIP_HAWAII && !vf)
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kfd->device_info.needs_pci_atomics = true;
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}
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@ -249,7 +245,6 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
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uint32_t gfx_target_version = 0;
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switch (adev->asic_type) {
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#ifdef KFD_SUPPORT_IOMMU_V2
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#ifdef CONFIG_DRM_AMDGPU_CIK
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case CHIP_KAVERI:
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gfx_target_version = 70000;
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@ -262,7 +257,6 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
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if (!vf)
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f2g = &gfx_v8_kfd2kgd;
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break;
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#endif
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#ifdef CONFIG_DRM_AMDGPU_CIK
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case CHIP_HAWAII:
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gfx_target_version = 70001;
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@ -2558,18 +2558,12 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev)
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}
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switch (dev->adev->asic_type) {
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case CHIP_CARRIZO:
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device_queue_manager_init_vi(&dqm->asic_ops);
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break;
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case CHIP_KAVERI:
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device_queue_manager_init_cik(&dqm->asic_ops);
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break;
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case CHIP_HAWAII:
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device_queue_manager_init_cik_hawaii(&dqm->asic_ops);
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break;
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case CHIP_CARRIZO:
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case CHIP_TONGA:
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case CHIP_FIJI:
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case CHIP_POLARIS10:
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