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Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux.git

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This commit is contained in:
Stephen Rothwell 2024-12-20 10:41:19 +11:00
commit a03c7cb185
41 changed files with 3049 additions and 93 deletions
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54
Documentation/devicetree/bindings/arm/mediatek.yaml
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@ -239,6 +239,34 @@ properties:
- enum:
- mediatek,mt8183-pumpkin
- const: mediatek,mt8183
- description: Google Chinchou (Asus Chromebook CZ1104CM2A/CZ1204CM2A)
items:
- const: google,chinchou-sku0
- const: google,chinchou-sku2
- const: google,chinchou-sku4
- const: google,chinchou-sku5
- const: google,chinchou
- const: mediatek,mt8186
- description: Google Chinchou (Asus Chromebook CZ1104FM2A/CZ1204FM2A/CZ1104CM2A/CZ1204CM2A)
items:
- const: google,chinchou-sku1
- const: google,chinchou-sku3
- const: google,chinchou-sku6
- const: google,chinchou-sku7
- const: google,chinchou-sku17
- const: google,chinchou-sku20
- const: google,chinchou-sku22
- const: google,chinchou-sku23
- const: google,chinchou
- const: mediatek,mt8186
- description: Google Chinchou360 (Asus Chromebook CZ1104FM2A/CZ1204FM2A Flip)
items:
- const: google,chinchou-sku16
- const: google,chinchou-sku18
- const: google,chinchou-sku19
- const: google,chinchou-sku21
- const: google,chinchou
- const: mediatek,mt8186
- description: Google Magneton (Lenovo IdeaPad Slim 3 Chromebook (14M868))
items:
- const: google,steelix-sku393219
@ -263,6 +291,19 @@ properties:
- const: google,steelix-sku196608
- const: google,steelix
- const: mediatek,mt8186
- description: Google Starmie (ASUS Chromebook Enterprise CM30 (CM3001))
items:
- const: google,starmie-sku0
- const: google,starmie-sku2
- const: google,starmie-sku3
- const: google,starmie
- const: mediatek,mt8186
- description: Google Starmie (ASUS Chromebook Enterprise CM30 (CM3001))
items:
- const: google,starmie-sku1
- const: google,starmie-sku4
- const: google,starmie
- const: mediatek,mt8186
- description: Google Steelix (Lenovo 300e Yoga Chromebook Gen 4)
items:
- enum:
@ -307,6 +348,19 @@ properties:
- enum:
- mediatek,mt8186-evb
- const: mediatek,mt8186
- description: Google Ciri (Lenovo Chromebook Duet (11", 9))
items:
- enum:
- google,ciri-sku0
- google,ciri-sku1
- google,ciri-sku2
- google,ciri-sku3
- google,ciri-sku4
- google,ciri-sku5
- google,ciri-sku6
- google,ciri-sku7
- const: google,ciri
- const: mediatek,mt8188
- items:
- enum:
- mediatek,mt8188-evb

14
arch/arm64/boot/dts/mediatek/Makefile
View File

@ -17,6 +17,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-mini.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sata.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-sd.dtbo
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986b-rfb.dtb
@ -55,10 +56,15 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-kodama-sku32.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-chinchou-sku16.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393216.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393217.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-magneton-sku393218.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-rusty-sku196608.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-starmie-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131072.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-steelix-sku131073.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327681.dtb
@ -69,6 +75,14 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589824.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589825.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku3.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku4.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku5.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku6.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-geralt-ciri-sku7.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r5-sku2.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb

1
arch/arm64/boot/dts/mediatek/mt6359.dtsi
View File

@ -8,6 +8,7 @@ pmic: pmic {
compatible = "mediatek,mt6359";
interrupt-controller;
#interrupt-cells = <2>;
#sound-dai-cells = <1>;
pmic_adc: adc {
compatible = "mediatek,mt6359-auxadc";

34
arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sata.dtso Normal file
View File

@ -0,0 +1,34 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2021 MediaTek Inc.
* Author: Frank Wunderlich <frank-w@public-files.de>
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
&{/} {
compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
reg_sata12v: regulator-sata12v {
compatible = "regulator-fixed";
regulator-name = "sata12v";
regulator-min-microvolt = <12000000>;
regulator-max-microvolt = <12000000>;
gpio = <&pio 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_sata5v: regulator-sata5v {
compatible = "regulator-fixed";
regulator-name = "sata5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
vin-supply = <&reg_sata12v>;
};
};

29
arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi
View File

@ -931,7 +931,7 @@ pmic: pmic {
interrupt-controller;
#interrupt-cells = <2>;
clock: mt6397clock {
clock: clocks {
compatible = "mediatek,mt6397-clk";
#clock-cells = <1>;
};
@ -942,11 +942,10 @@ pio6397: pinctrl {
#gpio-cells = <2>;
};
regulator: mt6397regulator {
regulators {
compatible = "mediatek,mt6397-regulator";
mt6397_vpca15_reg: buck_vpca15 {
regulator-compatible = "buck_vpca15";
regulator-name = "vpca15";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@ -956,7 +955,6 @@ mt6397_vpca15_reg: buck_vpca15 {
};
mt6397_vpca7_reg: buck_vpca7 {
regulator-compatible = "buck_vpca7";
regulator-name = "vpca7";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@ -966,7 +964,6 @@ mt6397_vpca7_reg: buck_vpca7 {
};
mt6397_vsramca15_reg: buck_vsramca15 {
regulator-compatible = "buck_vsramca15";
regulator-name = "vsramca15";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@ -975,7 +972,6 @@ mt6397_vsramca15_reg: buck_vsramca15 {
};
mt6397_vsramca7_reg: buck_vsramca7 {
regulator-compatible = "buck_vsramca7";
regulator-name = "vsramca7";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@ -984,7 +980,6 @@ mt6397_vsramca7_reg: buck_vsramca7 {
};
mt6397_vcore_reg: buck_vcore {
regulator-compatible = "buck_vcore";
regulator-name = "vcore";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@ -993,7 +988,6 @@ mt6397_vcore_reg: buck_vcore {
};
mt6397_vgpu_reg: buck_vgpu {
regulator-compatible = "buck_vgpu";
regulator-name = "vgpu";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@ -1002,7 +996,6 @@ mt6397_vgpu_reg: buck_vgpu {
};
mt6397_vdrm_reg: buck_vdrm {
regulator-compatible = "buck_vdrm";
regulator-name = "vdrm";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1400000>;
@ -1011,7 +1004,6 @@ mt6397_vdrm_reg: buck_vdrm {
};
mt6397_vio18_reg: buck_vio18 {
regulator-compatible = "buck_vio18";
regulator-name = "vio18";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
@ -1020,18 +1012,15 @@ mt6397_vio18_reg: buck_vio18 {
};
mt6397_vtcxo_reg: ldo_vtcxo {
regulator-compatible = "ldo_vtcxo";
regulator-name = "vtcxo";
regulator-always-on;
};
mt6397_va28_reg: ldo_va28 {
regulator-compatible = "ldo_va28";
regulator-name = "va28";
};
mt6397_vcama_reg: ldo_vcama {
regulator-compatible = "ldo_vcama";
regulator-name = "vcama";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -1039,18 +1028,15 @@ mt6397_vcama_reg: ldo_vcama {
};
mt6397_vio28_reg: ldo_vio28 {
regulator-compatible = "ldo_vio28";
regulator-name = "vio28";
regulator-always-on;
};
mt6397_vusb_reg: ldo_vusb {
regulator-compatible = "ldo_vusb";
regulator-name = "vusb";
};
mt6397_vmc_reg: ldo_vmc {
regulator-compatible = "ldo_vmc";
regulator-name = "vmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
@ -1058,7 +1044,6 @@ mt6397_vmc_reg: ldo_vmc {
};
mt6397_vmch_reg: ldo_vmch {
regulator-compatible = "ldo_vmch";
regulator-name = "vmch";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
@ -1066,7 +1051,6 @@ mt6397_vmch_reg: ldo_vmch {
};
mt6397_vemc_3v3_reg: ldo_vemc3v3 {
regulator-compatible = "ldo_vemc3v3";
regulator-name = "vemc_3v3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
@ -1074,7 +1058,6 @@ mt6397_vemc_3v3_reg: ldo_vemc3v3 {
};
mt6397_vgp1_reg: ldo_vgp1 {
regulator-compatible = "ldo_vgp1";
regulator-name = "vcamd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -1082,7 +1065,6 @@ mt6397_vgp1_reg: ldo_vgp1 {
};
mt6397_vgp2_reg: ldo_vgp2 {
regulator-compatible = "ldo_vgp2";
regulator-name = "vcamio";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@ -1090,7 +1072,6 @@ mt6397_vgp2_reg: ldo_vgp2 {
};
mt6397_vgp3_reg: ldo_vgp3 {
regulator-compatible = "ldo_vgp3";
regulator-name = "vcamaf";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
@ -1098,7 +1079,6 @@ mt6397_vgp3_reg: ldo_vgp3 {
};
mt6397_vgp4_reg: ldo_vgp4 {
regulator-compatible = "ldo_vgp4";
regulator-name = "vgp4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
@ -1106,7 +1086,6 @@ mt6397_vgp4_reg: ldo_vgp4 {
};
mt6397_vgp5_reg: ldo_vgp5 {
regulator-compatible = "ldo_vgp5";
regulator-name = "vgp5";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
@ -1114,7 +1093,6 @@ mt6397_vgp5_reg: ldo_vgp5 {
};
mt6397_vgp6_reg: ldo_vgp6 {
regulator-compatible = "ldo_vgp6";
regulator-name = "vgp6";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
@ -1123,7 +1101,6 @@ mt6397_vgp6_reg: ldo_vgp6 {
};
mt6397_vibr_reg: ldo_vibr {
regulator-compatible = "ldo_vibr";
regulator-name = "vibr";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <3300000>;
@ -1131,7 +1108,7 @@ mt6397_vibr_reg: ldo_vibr {
};
};
rtc: mt6397rtc {
rtc: rtc {
compatible = "mediatek,mt6397-rtc";
};
};

25
arch/arm64/boot/dts/mediatek/mt8173-evb.dts
View File

@ -307,11 +307,10 @@ pmic: pmic {
interrupt-controller;
#interrupt-cells = <2>;
mt6397regulator: mt6397regulator {
regulators {
compatible = "mediatek,mt6397-regulator";
mt6397_vpca15_reg: buck_vpca15 {
regulator-compatible = "buck_vpca15";
regulator-name = "vpca15";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@ -320,7 +319,6 @@ mt6397_vpca15_reg: buck_vpca15 {
};
mt6397_vpca7_reg: buck_vpca7 {
regulator-compatible = "buck_vpca7";
regulator-name = "vpca7";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@ -329,7 +327,6 @@ mt6397_vpca7_reg: buck_vpca7 {
};
mt6397_vsramca15_reg: buck_vsramca15 {
regulator-compatible = "buck_vsramca15";
regulator-name = "vsramca15";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@ -338,7 +335,6 @@ mt6397_vsramca15_reg: buck_vsramca15 {
};
mt6397_vsramca7_reg: buck_vsramca7 {
regulator-compatible = "buck_vsramca7";
regulator-name = "vsramca7";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@ -347,7 +343,6 @@ mt6397_vsramca7_reg: buck_vsramca7 {
};
mt6397_vcore_reg: buck_vcore {
regulator-compatible = "buck_vcore";
regulator-name = "vcore";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@ -356,7 +351,6 @@ mt6397_vcore_reg: buck_vcore {
};
mt6397_vgpu_reg: buck_vgpu {
regulator-compatible = "buck_vgpu";
regulator-name = "vgpu";
regulator-min-microvolt = < 700000>;
regulator-max-microvolt = <1350000>;
@ -365,7 +359,6 @@ mt6397_vgpu_reg: buck_vgpu {
};
mt6397_vdrm_reg: buck_vdrm {
regulator-compatible = "buck_vdrm";
regulator-name = "vdrm";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1400000>;
@ -374,7 +367,6 @@ mt6397_vdrm_reg: buck_vdrm {
};
mt6397_vio18_reg: buck_vio18 {
regulator-compatible = "buck_vio18";
regulator-name = "vio18";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
@ -383,19 +375,16 @@ mt6397_vio18_reg: buck_vio18 {
};
mt6397_vtcxo_reg: ldo_vtcxo {
regulator-compatible = "ldo_vtcxo";
regulator-name = "vtcxo";
regulator-always-on;
};
mt6397_va28_reg: ldo_va28 {
regulator-compatible = "ldo_va28";
regulator-name = "va28";
regulator-always-on;
};
mt6397_vcama_reg: ldo_vcama {
regulator-compatible = "ldo_vcama";
regulator-name = "vcama";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2800000>;
@ -403,18 +392,15 @@ mt6397_vcama_reg: ldo_vcama {
};
mt6397_vio28_reg: ldo_vio28 {
regulator-compatible = "ldo_vio28";
regulator-name = "vio28";
regulator-always-on;
};
mt6397_vusb_reg: ldo_vusb {
regulator-compatible = "ldo_vusb";
regulator-name = "vusb";
};
mt6397_vmc_reg: ldo_vmc {
regulator-compatible = "ldo_vmc";
regulator-name = "vmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
@ -422,7 +408,6 @@ mt6397_vmc_reg: ldo_vmc {
};
mt6397_vmch_reg: ldo_vmch {
regulator-compatible = "ldo_vmch";
regulator-name = "vmch";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
@ -430,7 +415,6 @@ mt6397_vmch_reg: ldo_vmch {
};
mt6397_vemc_3v3_reg: ldo_vemc3v3 {
regulator-compatible = "ldo_vemc3v3";
regulator-name = "vemc_3v3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
@ -438,7 +422,6 @@ mt6397_vemc_3v3_reg: ldo_vemc3v3 {
};
mt6397_vgp1_reg: ldo_vgp1 {
regulator-compatible = "ldo_vgp1";
regulator-name = "vcamd";
regulator-min-microvolt = <1220000>;
regulator-max-microvolt = <3300000>;
@ -446,7 +429,6 @@ mt6397_vgp1_reg: ldo_vgp1 {
};
mt6397_vgp2_reg: ldo_vgp2 {
regulator-compatible = "ldo_vgp2";
regulator-name = "vcamio";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3300000>;
@ -454,7 +436,6 @@ mt6397_vgp2_reg: ldo_vgp2 {
};
mt6397_vgp3_reg: ldo_vgp3 {
regulator-compatible = "ldo_vgp3";
regulator-name = "vcamaf";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
@ -462,7 +443,6 @@ mt6397_vgp3_reg: ldo_vgp3 {
};
mt6397_vgp4_reg: ldo_vgp4 {
regulator-compatible = "ldo_vgp4";
regulator-name = "vgp4";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
@ -470,7 +450,6 @@ mt6397_vgp4_reg: ldo_vgp4 {
};
mt6397_vgp5_reg: ldo_vgp5 {
regulator-compatible = "ldo_vgp5";
regulator-name = "vgp5";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
@ -478,7 +457,6 @@ mt6397_vgp5_reg: ldo_vgp5 {
};
mt6397_vgp6_reg: ldo_vgp6 {
regulator-compatible = "ldo_vgp6";
regulator-name = "vgp6";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3300000>;
@ -486,7 +464,6 @@ mt6397_vgp6_reg: ldo_vgp6 {
};
mt6397_vibr_reg: ldo_vibr {
regulator-compatible = "ldo_vibr";
regulator-name = "vibr";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <3300000>;

4
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-damu.dts
View File

@ -26,6 +26,10 @@ &touchscreen {
hid-descr-addr = <0x0001>;
};
&mt6358codec {
mediatek,dmic-mode = <1>; /* one-wire */
};
&qca_wifi {
qcom,ath10k-calibration-variant = "GO_DAMU";
};

15
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts
View File

@ -12,3 +12,18 @@ / {
chassis-type = "laptop";
compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183";
};
&i2c0 {
touchscreen@40 {
compatible = "hid-over-i2c";
reg = <0x40>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
post-power-on-delay-ms = <70>;
hid-descr-addr = <0x0001>;
};
};

15
arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow.dtsi
View File

@ -6,6 +6,21 @@
/dts-v1/;
#include "mt8183-kukui-jacuzzi.dtsi"
&i2c0 {
touchscreen@40 {
compatible = "hid-over-i2c";
reg = <0x40>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>;
post-power-on-delay-ms = <70>;
hid-descr-addr = <0x0001>;
};
};
&i2c2 {
trackpad@2c {
compatible = "hid-over-i2c";

9
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
View File

@ -269,11 +269,6 @@ dsi_out: endpoint {
};
};
&dpi0 {
/* TODO Re-enable after DP to Type-C port muxing can be described */
status = "disabled";
};
&gic {
mediatek,broken-save-restore-fw;
};
@ -944,13 +939,13 @@ &ssusb {
};
&thermal_zones {
tboard1 {
tboard1-thermal {
polling-delay = <1000>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&tboard_thermistor1>;
};
tboard2 {
tboard2-thermal {
polling-delay = <1000>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&tboard_thermistor2>;

4
arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts
View File

@ -522,10 +522,6 @@ &scp {
status = "okay";
};
&dsi0 {
status = "disabled";
};
&dpi0 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&dpi_func_pins>;

2
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@ -1834,6 +1834,7 @@ dsi0: dsi@14014000 {
resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>;
phys = <&mipi_tx0>;
phy-names = "dphy";
status = "disabled";
};
dpi0: dpi@14015000 {
@ -1845,6 +1846,7 @@ dpi0: dpi@14015000 {
<&mmsys CLK_MM_DPI_MM>,
<&apmixedsys CLK_APMIXED_TVDPLL>;
clock-names = "pixel", "engine", "pll";
status = "disabled";
port {
dpi_out: endpoint { };

18
arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku0.dts Normal file
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@ -0,0 +1,18 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2024 Google LLC
*/
/dts-v1/;
#include "mt8186-corsola-chinchou.dtsi"
/ {
model = "Google chinchou CZ1104CM2A/CZ1204CM2A";
compatible = "google,chinchou-sku0", "google,chinchou-sku2",
"google,chinchou-sku4", "google,chinchou-sku5",
"google,chinchou", "mediatek,mt8186";
};
&gpio_keys {
status = "disabled";
};

35
arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku1.dts Normal file
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@ -0,0 +1,35 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2024 Google LLC
*/
/dts-v1/;
#include "mt8186-corsola-chinchou.dtsi"
/ {
model = "Google chinchou CZ1104FM2A/CZ1204FM2A/CZ1104CM2A/CZ1204CM2A";
compatible = "google,chinchou-sku1", "google,chinchou-sku3",
"google,chinchou-sku6", "google,chinchou-sku7",
"google,chinchou-sku17", "google,chinchou-sku20",
"google,chinchou-sku22", "google,chinchou-sku23",
"google,chinchou", "mediatek,mt8186";
};
&gpio_keys {
status = "disabled";
};
&i2c1 {
i2c-scl-internal-delay-ns = <10000>;
touchscreen: touchscreen@41 {
compatible = "ilitek,ili2901";
reg = <0x41>;
interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>;
vccio-supply = <&pp1800_tchscr_report_disable>;
vcc33-supply = <&pp3300_z2>;
};
};

29
arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou-sku16.dts Normal file
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@ -0,0 +1,29 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2024 Google LLC
*/
/dts-v1/;
#include "mt8186-corsola-chinchou.dtsi"
/ {
model = "Google chinchou CZ1104FM2A/CZ1204FM2A";
compatible = "google,chinchou-sku16", "google,chinchou-sku18",
"google,chinchou-sku19", "google,chinchou-sku21",
"google,chinchou", "mediatek,mt8186";
};
&i2c1 {
i2c-scl-internal-delay-ns = <10000>;
touchscreen: touchscreen@41 {
compatible = "ilitek,ili2901";
reg = <0x41>;
interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>;
vccio-supply = <&pp1800_tchscr_report_disable>;
vcc33-supply = <&pp3300_z2>;
};
};

321
arch/arm64/boot/dts/mediatek/mt8186-corsola-chinchou.dtsi Normal file
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@ -0,0 +1,321 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2024 Google LLC
*/
/dts-v1/;
#include "mt8186-corsola.dtsi"
/ {
/delete-node/ speaker-codec;
pp1000_edpbrdg: regulator-pp1000-edpbrdg {
compatible = "regulator-fixed";
regulator-name = "pp1000_edpbrdg";
pinctrl-names = "default";
pinctrl-0 = <&en_pp1000_edpbrdg>;
enable-active-high;
regulator-boot-on;
gpio = <&pio 29 GPIO_ACTIVE_HIGH>;
vin-supply = <&pp3300_z2>;
};
pp1800_edpbrdg_dx: regulator-pp1800-edpbrdg-dx {
compatible = "regulator-fixed";
regulator-name = "pp1800_edpbrdg_dx";
pinctrl-names = "default";
pinctrl-0 = <&en_pp1800_edpbrdg>;
enable-active-high;
regulator-boot-on;
gpio = <&pio 30 GPIO_ACTIVE_HIGH>;
vin-supply = <&mt6366_vio18_reg>;
};
pp3300_edp_dx: regulator-pp3300-edp-dx {
compatible = "regulator-fixed";
regulator-name = "pp3300_edp_dx";
pinctrl-names = "default";
pinctrl-0 = <&en_pp3300_edpbrdg>;
enable-active-high;
regulator-boot-on;
gpio = <&pio 31 GPIO_ACTIVE_HIGH>;
vin-supply = <&pp3300_z2>;
};
pp1800_tchscr_report_disable: regulator-pp1800-tchscr-report-disable {
compatible = "regulator-fixed";
regulator-name = "pp1800_tchscr_report_disable";
pinctrl-names = "default";
regulator-boot-on;
pinctrl-0 = <&touch_pin_report>;
gpio = <&pio 37 GPIO_ACTIVE_LOW>;
};
};
&dsi_out {
remote-endpoint = <&anx7625_in>;
};
&i2c0 {
clock-frequency = <400000>;
anx_bridge: anx7625@58 {
compatible = "analogix,anx7625";
reg = <0x58>;
pinctrl-names = "default";
pinctrl-0 = <&anx7625_pins>;
enable-gpios = <&pio 96 GPIO_ACTIVE_HIGH>;
reset-gpios = <&pio 98 GPIO_ACTIVE_HIGH>;
vdd10-supply = <&pp1000_edpbrdg>;
vdd18-supply = <&pp1800_edpbrdg_dx>;
vdd33-supply = <&pp3300_edp_dx>;
analogix,lane0-swing = /bits/ 8 <0x70 0x30>;
analogix,lane1-swing = /bits/ 8 <0x70 0x30>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
anx7625_in: endpoint {
remote-endpoint = <&dsi_out>;
data-lanes = <0 1 2 3>;
};
};
port@1 {
reg = <1>;
anx7625_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
aux-bus {
panel: panel {
compatible = "edp-panel";
power-supply = <&pp3300_disp_x>;
backlight = <&backlight_lcd0>;
port {
panel_in: endpoint {
remote-endpoint = <&anx7625_out>;
};
};
};
};
};
};
&i2c2 {
/delete-node/ trackpad@15;
touchpad@15 {
compatible = "hid-over-i2c";
reg = <0x15>;
interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_LOW>;
post-power-on-delay-ms = <10>;
hid-descr-addr = <0x0001>;
vdd-supply = <&pp3300_s3>;
wakeup-source;
};
};
&i2c5 {
clock-frequency = <400000>;
/delete-node/ codec@1a;
rt5650: rt5650@1a {
compatible = "realtek,rt5650";
reg = <0x1a>;
avdd-supply = <&mt6366_vio18_reg>;
cpvdd-supply = <&mt6366_vio18_reg>;
pinctrl-names = "default";
pinctrl-0 = <&speaker_codec_pins_default>;
cbj-sleeve-gpios = <&pio 150 GPIO_ACTIVE_HIGH>;
interrupt-parent = <&pio>;
interrupts = <17 IRQ_TYPE_EDGE_BOTH>;
#sound-dai-cells = <0>;
realtek,dmic1-data-pin = <2>;
realtek,jd-mode = <2>;
};
};
&i2c_tunnel {
/delete-node/ sbs-battery@b;
battery: sbs-battery@f {
compatible = "sbs,sbs-battery";
reg = <0xf>;
sbs,i2c-retry-count = <2>;
sbs,poll-retry-count = <1>;
};
};
&keyboard_controller {
keypad,num-columns = <15>;
function-row-physmap = <
MATRIX_KEY(0x00, 0x02, 0) /* T1 */
MATRIX_KEY(0x03, 0x02, 0) /* T2 */
MATRIX_KEY(0x02, 0x02, 0) /* T3 */
MATRIX_KEY(0x01, 0x02, 0) /* T4 */
MATRIX_KEY(0x03, 0x04, 0) /* T5 */
MATRIX_KEY(0x02, 0x04, 0) /* T6 */
MATRIX_KEY(0x01, 0x04, 0) /* T7 */
MATRIX_KEY(0x02, 0x09, 0) /* T8 */
MATRIX_KEY(0x01, 0x09, 0) /* T9 */
MATRIX_KEY(0x00, 0x04, 0) /* T10 */
MATRIX_KEY(0x00, 0x01, 0) /* T11 */
MATRIX_KEY(0x01, 0x05, 0) /* T12 */
>;
linux,keymap = <
CROS_STD_MAIN_KEYMAP
MATRIX_KEY(0x00, 0x02, KEY_BACK) /* T1 */
MATRIX_KEY(0x03, 0x02, KEY_REFRESH) /* T2 */
MATRIX_KEY(0x02, 0x02, KEY_ZOOM) /* T3 */
MATRIX_KEY(0x01, 0x02, KEY_SCALE) /* T4 */
MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) /* T5 */
MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) /* T6 */
MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) /* T7 */
MATRIX_KEY(0x02, 0x09, KEY_MUTE) /* T8 */
MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) /* T9 */
MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) /* T10 */
MATRIX_KEY(0x00, 0x01, KEY_MICMUTE) /* T11 */
MATRIX_KEY(0x01, 0x05, KEY_CONTROLPANEL) /* T12 */
MATRIX_KEY(0x03, 0x05, KEY_PREVIOUSSONG) /* T13 */
MATRIX_KEY(0x00, 0x09, KEY_PLAYPAUSE) /* T14 */
MATRIX_KEY(0x00, 0x0b, KEY_NEXTSONG) /* T15 */
MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA) /* Search*/
MATRIX_KEY(0x01, 0x0e, KEY_LEFTCTRL) /* Left Control*/
MATRIX_KEY(0x06, 0x0d, KEY_LEFTALT) /* Left ALT*/
MATRIX_KEY(0x03, 0x0e, KEY_RIGHTCTRL) /* Right Control*/
MATRIX_KEY(0x06, 0x0a, KEY_BACKSLASH) /* BACKSLASH*/
>;
};
&mmc1_pins_default {
pins-clk {
drive-strength = <8>;
};
pins-cmd-dat {
drive-strength = <8>;
};
};
&mmc1_pins_uhs {
pins-clk {
drive-strength = <8>;
};
pins-cmd-dat {
drive-strength = <8>;
};
};
&pen_insert {
wakeup-event-action = <EV_ACT_ANY>;
};
&pio {
anx7625_pins: anx7625-pins {
pins-int {
pinmux = <PINMUX_GPIO9__FUNC_GPIO9>;
input-enable;
bias-disable;
};
pins-reset {
pinmux = <PINMUX_GPIO98__FUNC_GPIO98>;
output-low;
};
pins-power-en {
pinmux = <PINMUX_GPIO96__FUNC_GPIO96>;
output-low;
};
};
en_pp1000_edpbrdg: pp1000-edpbrdg-en-pins {
pins-vreg-en {
pinmux = <PINMUX_GPIO29__FUNC_GPIO29>;
output-low;
};
};
en_pp1800_edpbrdg: pp1800-edpbrdg-en-pins {
pins-vreg-en {
pinmux = <PINMUX_GPIO30__FUNC_GPIO30>;
output-low;
};
};
en_pp3300_edpbrdg: pp3300-edpbrdg-en-pins {
pins-vreg-en {
pinmux = <PINMUX_GPIO31__FUNC_GPIO31>;
output-low;
};
};
touch_pin_report: pin-report-pins {
pins-touch-en {
pinmux = <PINMUX_GPIO37__FUNC_GPIO37>;
output-low;
};
};
};
&sound {
compatible = "mediatek,mt8186-mt6366-rt5650-sound";
model = "mt8186_rt5650";
mediatek,adsp = <&adsp>;
audio-routing =
"Headphone", "HPOL",
"Headphone", "HPOR",
"IN1P", "Headset Mic",
"IN1N", "Headset Mic",
"Speakers", "SPOL",
"Speakers", "SPOR",
"HDMI1", "TX";
hs-playback-dai-link {
codec {
sound-dai = <&rt5650>;
};
};
hs-capture-dai-link {
codec {
sound-dai = <&rt5650>;
};
};
spk-share-dai-link {
};
spk-hdmi-playback-dai-link {
codec {
sound-dai = <&it6505dptx>;
};
};
};
&touchscreen_pins {
/delete-node/ pins-report-sw;
};
&wifi_enable_pin {
pins-wifi-enable {
pinmux = <PINMUX_GPIO51__FUNC_GPIO51>;
};
};
&wifi_pwrseq {
reset-gpios = <&pio 51 GPIO_ACTIVE_LOW>;
};

31
arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku0.dts Normal file
View File

@ -0,0 +1,31 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2023 Google LLC
*/
/dts-v1/;
#include "mt8186-corsola-starmie.dtsi"
/ {
model = "Google Starmie sku0 board";
compatible = "google,starmie-sku0", "google,starmie-sku2",
"google,starmie-sku3", "google,starmie",
"mediatek,mt8186";
};
&panel {
compatible = "starry,ili9882t";
};
&i2c1 {
touchscreen: touchscreen@41 {
compatible = "ilitek,ili9882t";
reg = <0x41>;
interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
panel = <&panel>;
reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>;
vccio-supply = <&mt6366_vio18_reg>;
};
};

31
arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie-sku1.dts Normal file
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@ -0,0 +1,31 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2023 Google LLC
*/
/dts-v1/;
#include "mt8186-corsola-starmie.dtsi"
/ {
model = "Google Starmie sku1 board";
compatible = "google,starmie-sku1", "google,starmie-sku4",
"google,starmie", "mediatek,mt8186";
};
&panel {
compatible = "starry,himax83102-j02", "himax,hx83102";
};
&i2c1 {
touchscreen_himax: touchscreen@4f {
compatible = "hid-over-i2c";
reg = <0x4f>;
interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&touchscreen_pins>;
vdd-supply = <&mt6366_vio18_reg>;
panel = <&panel>;
post-power-on-delay-ms = <450>;
hid-descr-addr = <0x0001>;
};
};

472
arch/arm64/boot/dts/mediatek/mt8186-corsola-starmie.dtsi Normal file
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@ -0,0 +1,472 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2023 Google LLC
*/
/dts-v1/;
#include "mt8186-corsola.dtsi"
/ {
en_pp6000_mipi_disp_150ma: en-pp6000-mipi-disp-150ma {
compatible = "regulator-fixed";
regulator-name = "en_pp6000_mipi_disp_150ma";
gpio = <&pio 154 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&en_pp6000_mipi_disp_150ma_fixed_pins>;
};
/*
* Starmie does not have 3.3V display regulator. It is replaced
* with 6V module for enabling panel, re-using eDP GPIOs.
*/
/delete-node/ pp3300_disp_x;
en_pp6000_mipi_disp: en-regulator-pp6000-mipi-disp {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&edp_panel_fixed_pins>;
gpios = <&pio 153 GPIO_ACTIVE_HIGH>;
regulator-name = "en_pp6000_mipi_disp";
enable-active-high;
regulator-enable-ramp-delay = <3000>;
vin-supply = <&pp3300_z2>;
};
tboard_thermistor1: thermal-sensor1 {
compatible = "generic-adc-thermal";
#thermal-sensor-cells = <0>;
io-channels = <&auxadc 0>;
io-channel-names = "sensor-channel";
temperature-lookup-table = < (-5000) 1492
0 1413
5000 1324
10000 1227
15000 1121
20000 1017
25000 900
30000 797
35000 698
40000 606
45000 522
50000 449
55000 383
60000 327
65000 278
70000 236
75000 201
80000 171
85000 145
90000 163
95000 124
100000 91
105000 78
110000 67
115000 58
120000 50
125000 44>;
};
tboard_thermistor2: thermal-sensor2 {
compatible = "generic-adc-thermal";
#thermal-sensor-cells = <0>;
io-channels = <&auxadc 1>;
io-channel-names = "sensor-channel";
temperature-lookup-table = < (-5000) 1492
0 1413
5000 1324
10000 1227
15000 1121
20000 1017
25000 900
30000 797
35000 698
40000 606
45000 522
50000 449
55000 383
60000 327
65000 278
70000 236
75000 201
80000 171
85000 145
90000 163
95000 124
100000 91
105000 78
110000 67
115000 58
120000 50
125000 44>;
};
};
/*
* Starmie does not have EC keyboard. Remove default keyboard controller
* and replace it with the driver for side switches.
*/
/delete-node/ &keyboard_controller;
&cros_ec {
cbas: cbas {
compatible = "google,cros-cbas";
};
keyboard-controller {
compatible = "google,cros-ec-keyb-switches";
};
};
&dsi0 {
#address-cells = <1>;
#size-cells = <0>;
panel: panel@0 {
/* compatible will be set in board dts */
reg = <0>;
enable-gpios = <&pio 98 0>;
pinctrl-names = "default";
pinctrl-0 = <&panel_default_pins>;
avdd-supply = <&en_pp6000_mipi_disp>;
avee-supply = <&en_pp6000_mipi_disp_150ma>;
pp1800-supply = <&mt6366_vio18_reg>;
backlight = <&backlight_lcd0>;
rotation = <270>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
};
};
&dsi_out {
remote-endpoint = <&panel_in>;
};
&i2c0 {
status = "disabled";
};
&i2c2 {
status = "disabled";
};
&i2c4 {
status = "disabled";
};
&i2c5 {
clock-frequency = <400000>;
};
&mmc1_pins_default {
pins-clk {
drive-strength = <8>;
};
pins-cmd-dat {
drive-strength = <8>;
};
};
&mmc1_pins_uhs {
pins-clk {
drive-strength = <8>;
};
pins-cmd-dat {
drive-strength = <8>;
};
};
&pen_insert {
wakeup-event-action = <EV_ACT_ANY>;
};
&pio {
/* 185 lines */
gpio-line-names = "TP",
"TP",
"TP",
"I2S0_HP_DI",
"I2S3_DP_SPKR_DO",
"SAR_INT_ODL",
"BT_WAKE_AP_ODL",
"WIFI_INT_ODL",
"DPBRDG_INT_ODL",
"NC",
"EC_AP_HPD_OD",
"NC",
"TCHSCR_INT_1V8_ODL",
"EC_AP_INT_ODL",
"EC_IN_RW_ODL",
"GSC_AP_INT_ODL",
/*
* AP_FLASH_WP_L is crossystem ABI. Rev1 schematics
* call it AP_WP_ODL.
*/
"AP_FLASH_WP_L",
"HP_INT_ODL",
"PEN_EJECT_OD",
"NC",
"NC",
"UCAM_SEN_EN",
"NC",
"NC",
"NC",
"I2S2_DP_SPK_MCK",
"I2S2_DP_SPKR_BCK",
"I2S2_DP_SPKR_LRCK",
"NC",
"NC",
"NC",
"NC",
"UART_GSC_TX_AP_RX",
"UART_AP_TX_GSC_RX",
"UART_DBGCON_TX_ADSP_RX",
"UART_ADSP_TX_DBGCON_RX",
"NC",
"TCHSCR_REPORT_DISABLE",
"NC",
"EN_PP1800_DPBRDG",
"SPI_AP_CLK_EC",
"SPI_AP_CS_EC_L",
"SPI_AP_DO_EC_DI",
"SPI_AP_DI_EC_DO",
"SPI_AP_CLK_GSC",
"SPI_AP_CS_GSC_L",
"SPI_AP_DO_GSC_DI",
"SPI_AP_DI_GSC_DO",
"UART_DBGCON_TX_SCP_RX",
"UART_SCP_TX_DBGCON_RX",
"EN_PP1200_CAM_X",
"WLAN_MODULE_RST_L",
"NC",
"NC",
"NC",
"NC",
"I2S1_HP_DO",
"I2S1_HP_BCK",
"I2S1_HP_LRCK",
"I2S1_HP_MCK",
"TCHSCR_RST_1V8_L",
"SPI_AP_CLK_ROM",
"SPI_AP_CS_ROM_L",
"SPI_AP_DO_ROM_DI",
"SPI_AP_DI_ROM_DO",
"NC",
"NC",
"EMMC_STRB",
"EMMC_CLK",
"EMMC_CMD",
"EMMC_RST_L",
"EMMC_DATA0",
"EMMC_DATA1",
"EMMC_DATA2",
"EMMC_DATA3",
"EMMC_DATA4",
"EMMC_DATA5",
"EMMC_DATA6",
"EMMC_DATA7",
"AP_KPCOL0",
"NC",
"NC",
"NC",
"TP",
"SDIO_CLK",
"SDIO_CMD",
"SDIO_DATA0",
"SDIO_DATA1",
"SDIO_DATA2",
"SDIO_DATA3",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"MIPI_BL_PWM_1V8",
"DISP_RST_1V8_L",
"MIPI_DPI_CLK",
"MIPI_DPI_VSYNC",
"MIPI_DPI_HSYNC",
"MIPI_DPI_DE",
"MIPI_DPI_D0",
"MIPI_DPI_D1",
"MIPI_DPI_D2",
"MIPI_DPI_D3",
"MIPI_DPI_D4",
"MIPI_DPI_D5",
"MIPI_DPI_D6",
"MIPI_DPI_DA7",
"MIPI_DPI_D8",
"MIPI_DPI_D9",
"MIPI_DPI_D10",
"MIPI_DPI_D11",
"PCM_BT_CLK",
"PCM_BT_SYNC",
"PCM_BT_DI",
"PCM_BT_DO",
"JTAG_TMS_TP",
"JTAG_TCK_TP",
"JTAG_TDI_TP",
"JTAG_TDO_TP",
"JTAG_TRSTN_TP",
"NC",
"NC",
"UCAM_DET_ODL",
"NC",
"NC",
"AP_I2C_TCHSCR_SCL_1V8",
"AP_I2C_TCHSCR_SDA_1V8",
"NC",
"NC",
"AP_I2C_DPBRDG_SCL_1V8",
"AP_I2C_DPBRDG_SDA_1V8",
"NC",
"NC",
"AP_I2C_AUD_SCL_1V8",
"AP_I2C_AUD_SDA_1V8",
"AP_I2C_DISP_SCL_1V8",
"AP_I2C_DISP_SDA_1V8",
"NC",
"NC",
"NC",
"NC",
"SCP_I2C_SENSOR_SCL_1V8",
"SCP_I2C_SENSOR_SDA_1V8",
"AP_EC_WARM_RST_REQ",
"AP_XHCI_INIT_DONE",
"USB3_HUB_RST_L",
"EN_SPKR",
"BEEP_ON",
"AP_DISP_BKLTEN",
"EN_PP6000_MIPI_DISP",
"EN_PP6000_MIPI_DISP_150MA",
"BT_KILL_1V8_L",
"WIFI_KILL_1V8_L",
"PWRAP_SPI0_CSN",
"PWRAP_SPI0_CK",
"PWRAP_SPI0_MO",
"PWRAP_SPI0_MI",
"SRCLKENA0",
"SRCLKENA1",
"SCP_VREQ_VAO",
"AP_RTC_CLK32K",
"AP_PMIC_WDTRST_L",
"AUD_CLK_MOSI",
"AUD_SYNC_MOSI",
"AUD_DAT_MOSI0",
"AUD_DAT_MOSI1",
"AUD_CLK_MISO",
"AUD_SYNC_MISO",
"AUD_DAT_MISO0",
"AUD_DAT_MISO1",
"NC",
"NC",
"NC",
"DPBRDG_RST_L",
"LTE_W_DISABLE_L",
"LTE_SAR_DETECT_L",
"EN_PP3300_LTE_X",
"LTE_PWR_OFF_L",
"LTE_RESET_L",
"TP",
"TP";
dpi_default_pins: dpi-default-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO103__FUNC_GPIO103>,
<PINMUX_GPIO104__FUNC_GPIO104>,
<PINMUX_GPIO105__FUNC_GPIO105>,
<PINMUX_GPIO106__FUNC_GPIO106>,
<PINMUX_GPIO107__FUNC_GPIO107>,
<PINMUX_GPIO108__FUNC_GPIO108>,
<PINMUX_GPIO109__FUNC_GPIO109>,
<PINMUX_GPIO110__FUNC_GPIO110>,
<PINMUX_GPIO111__FUNC_GPIO111>,
<PINMUX_GPIO112__FUNC_GPIO112>,
<PINMUX_GPIO113__FUNC_GPIO113>,
<PINMUX_GPIO114__FUNC_GPIO114>,
<PINMUX_GPIO101__FUNC_GPIO101>,
<PINMUX_GPIO100__FUNC_GPIO100>,
<PINMUX_GPIO102__FUNC_GPIO102>,
<PINMUX_GPIO99__FUNC_GPIO99>;
drive-strength = <10>;
output-low;
};
};
dpi_func_pins: dpi-func-pins {
pins-cmd-dat {
pinmux = <PINMUX_GPIO103__FUNC_DPI_DATA0>,
<PINMUX_GPIO104__FUNC_DPI_DATA1>,
<PINMUX_GPIO105__FUNC_DPI_DATA2>,
<PINMUX_GPIO106__FUNC_DPI_DATA3>,
<PINMUX_GPIO107__FUNC_DPI_DATA4>,
<PINMUX_GPIO108__FUNC_DPI_DATA5>,
<PINMUX_GPIO109__FUNC_DPI_DATA6>,
<PINMUX_GPIO110__FUNC_DPI_DATA7>,
<PINMUX_GPIO111__FUNC_DPI_DATA8>,
<PINMUX_GPIO112__FUNC_DPI_DATA9>,
<PINMUX_GPIO113__FUNC_DPI_DATA10>,
<PINMUX_GPIO114__FUNC_DPI_DATA11>,
<PINMUX_GPIO101__FUNC_DPI_HSYNC>,
<PINMUX_GPIO100__FUNC_DPI_VSYNC>,
<PINMUX_GPIO102__FUNC_DPI_DE>,
<PINMUX_GPIO99__FUNC_DPI_PCLK>;
drive-strength = <10>;
};
};
en_pp6000_mipi_disp_150ma_fixed_pins: en_pp6000-mipi-disp-150ma-fixed-pins {
pins-en {
pinmux = <PINMUX_GPIO154__FUNC_GPIO154>;
output-low;
};
};
panel_default_pins: panel-default-pins {
pins-en {
pinmux = <PINMUX_GPIO98__FUNC_GPIO98>;
output-low;
};
};
};
&usb_c1 {
status = "disabled";
};
&thermal_zones {
tboard1-thermal {
polling-delay = <1000>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&tboard_thermistor1>;
};
tboard2-thermal {
polling-delay = <1000>; /* milliseconds */
polling-delay-passive = <0>; /* milliseconds */
thermal-sensors = <&tboard_thermistor2>;
};
};
&wifi_pwrseq {
reset-gpios = <&pio 51 1>;
};
/*
* Battery on Starmie is using a different address than default.
* Remove old node to reuse "battery" alias.
*/
/delete-node/ &battery;
&i2c_tunnel {
battery: sbs-battery@f {
compatible = "sbs,sbs-battery";
reg = <0xf>;
sbs,i2c-retry-count = <2>;
sbs,poll-retry-count = <1>;
};
};

8
arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi
View File

@ -424,6 +424,7 @@ it6505dptx: dp-bridge@5c {
ovdd-supply = <&mt6366_vsim2_reg>;
pwr18-supply = <&pp1800_dpbrdg_dx>;
reset-gpios = <&pio 177 GPIO_ACTIVE_LOW>;
extcon = <&usbc_extcon>;
ports {
#address-cells = <1>;
@ -1275,7 +1276,7 @@ pmic {
interrupts-extended = <&pio 201 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
mt6366codec: codec {
mt6366codec: audio-codec {
compatible = "mediatek,mt6366-sound", "mediatek,mt6358-sound";
Avdd-supply = <&mt6366_vaud28_reg>;
mediatek,dmic-mode = <1>; /* one-wire */
@ -1656,6 +1657,11 @@ usb_c1: connector@1 {
try-power-role = "source";
};
};
usbc_extcon: extcon0 {
compatible = "google,extcon-usbc-cros-ec";
google,usb-port-id = <0>;
};
};
};

8
arch/arm64/boot/dts/mediatek/mt8186.dtsi
View File

@ -1577,6 +1577,8 @@ ssusb0: usb@11201000 {
#address-cells = <2>;
#size-cells = <2>;
ranges;
wakeup-source;
mediatek,syscon-wakeup = <&pericfg 0x420 2>;
status = "disabled";
usb_host0: usb@11200000 {
@ -1590,8 +1592,6 @@ usb_host0: usb@11200000 {
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
interrupts = <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH 0>;
mediatek,syscon-wakeup = <&pericfg 0x420 2>;
wakeup-source;
status = "disabled";
};
};
@ -1643,6 +1643,8 @@ ssusb1: usb@11281000 {
#address-cells = <2>;
#size-cells = <2>;
ranges;
wakeup-source;
mediatek,syscon-wakeup = <&pericfg 0x424 2>;
status = "disabled";
usb_host1: usb@11280000 {
@ -1656,8 +1658,6 @@ usb_host1: usb@11280000 {
<&infracfg_ao CLK_INFRA_AO_SSUSB_TOP_P1_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
mediatek,syscon-wakeup = <&pericfg 0x424 2>;
wakeup-source;
status = "disabled";
};
};

32
arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku0.dts Normal file
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@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2023 Google LLC
*/
/dts-v1/;
#include "mt8188-geralt-ciri.dtsi"
/ {
model = "Google Ciri sku0 board";
compatible = "google,ciri-sku0", "google,ciri", "mediatek,mt8188";
};
&dsi_panel {
compatible = "boe,nv110wum-l60", "himax,hx83102";
};
&sound {
compatible = "mediatek,mt8188-rt5682s";
model = "mt8188_m98390_5682";
audio-routing =
"ETDM1_OUT", "ETDM_SPK_PIN",
"ETDM2_OUT", "ETDM_HP_PIN",
"ETDM1_IN", "ETDM_SPK_PIN",
"ETDM2_IN", "ETDM_HP_PIN",
"ADDA Capture", "MTKAIF_PIN",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR",
"IN1P", "Headset Mic",
"Left Spk", "Front Left BE_OUT",
"Right Spk", "Front Right BE_OUT";
};

59
arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku1.dts Normal file
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@ -0,0 +1,59 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2023 Google LLC
*/
/dts-v1/;
#include "mt8188-geralt-ciri.dtsi"
/ {
model = "Google Ciri sku1 board";
compatible = "google,ciri-sku1", "google,ciri", "mediatek,mt8188";
};
&dsi_panel {
compatible = "ivo,t109nw41", "himax,hx83102";
};
&i2c0 {
/delete-node/ audio-codec@1a;
es8326: audio-codec@19 {
compatible = "everest,es8326";
reg = <0x19>;
interrupts-extended = <&pio 108 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&audio_codec_pins>;
#sound-dai-cells = <0>;
everest,jack-pol = [0e];
everest,interrupt-clk = [00];
};
};
&sound {
compatible = "mediatek,mt8188-es8326";
model = "mt8188_m98390_8326";
audio-routing =
"ETDM1_OUT", "ETDM_SPK_PIN",
"ETDM2_OUT", "ETDM_HP_PIN",
"ETDM1_IN", "ETDM_SPK_PIN",
"ETDM2_IN", "ETDM_HP_PIN",
"ADDA Capture", "MTKAIF_PIN",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR",
"MIC1", "Headset Mic",
"Left Spk", "Front Left BE_OUT",
"Right Spk", "Front Right BE_OUT";
dai-link-2 {
codec {
sound-dai = <&es8326>;
};
};
dai-link-3 {
codec {
sound-dai = <&es8326>;
};
};
};

59
arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku2.dts Normal file
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@ -0,0 +1,59 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2024 Google LLC
*/
/dts-v1/;
#include "mt8188-geralt-ciri.dtsi"
/ {
model = "Google Ciri sku2 board";
compatible = "google,ciri-sku2", "google,ciri", "mediatek,mt8188";
};
&dsi_panel {
compatible = "boe,nv110wum-l60", "himax,hx83102";
};
&i2c0 {
/delete-node/ audio-codec@1a;
es8326: audio-codec@19 {
compatible = "everest,es8326";
reg = <0x19>;
interrupts-extended = <&pio 108 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&audio_codec_pins>;
#sound-dai-cells = <0>;
everest,jack-pol = [0e];
everest,interrupt-clk = [00];
};
};
&sound {
compatible = "mediatek,mt8188-es8326";
model = "mt8188_m98390_8326";
audio-routing =
"ETDM1_OUT", "ETDM_SPK_PIN",
"ETDM2_OUT", "ETDM_HP_PIN",
"ETDM1_IN", "ETDM_SPK_PIN",
"ETDM2_IN", "ETDM_HP_PIN",
"ADDA Capture", "MTKAIF_PIN",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR",
"MIC1", "Headset Mic",
"Left Spk", "Front Left BE_OUT",
"Right Spk", "Front Right BE_OUT";
dai-link-2 {
codec {
sound-dai = <&es8326>;
};
};
dai-link-3 {
codec {
sound-dai = <&es8326>;
};
};
};

32
arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku3.dts Normal file
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@ -0,0 +1,32 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2024 Google LLC
*/
/dts-v1/;
#include "mt8188-geralt-ciri.dtsi"
/ {
model = "Google Ciri sku3 board";
compatible = "google,ciri-sku3", "google,ciri", "mediatek,mt8188";
};
&dsi_panel {
compatible = "ivo,t109nw41", "himax,hx83102";
};
&sound {
compatible = "mediatek,mt8188-rt5682s";
model = "mt8188_m98390_5682";
audio-routing =
"ETDM1_OUT", "ETDM_SPK_PIN",
"ETDM2_OUT", "ETDM_HP_PIN",
"ETDM1_IN", "ETDM_SPK_PIN",
"ETDM2_IN", "ETDM_HP_PIN",
"ADDA Capture", "MTKAIF_PIN",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR",
"IN1P", "Headset Mic",
"Left Spk", "Front Left BE_OUT",
"Right Spk", "Front Right BE_OUT";
};

48
arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku4.dts Normal file
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@ -0,0 +1,48 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2024 Google LLC
*/
/dts-v1/;
#include "mt8188-geralt-ciri.dtsi"
/ {
model = "Google Ciri sku4 board (rev4)";
compatible = "google,ciri-sku4", "google,ciri", "mediatek,mt8188";
};
&dsi_panel {
compatible = "boe,nv110wum-l60", "himax,hx83102";
};
&i2c0 {
/delete-node/ amplifier@38;
/delete-node/ amplifier@39;
tas2563: amplifier@4f {
compatible = "ti,tas2563", "ti,tas2781";
reg = <0x4f>, <0x4c>; /* left / right channel */
reset-gpios = <&pio 118 GPIO_ACTIVE_HIGH>;
#sound-dai-cells = <0>;
};
};
&sound {
compatible = "mediatek,mt8188-rt5682s";
model = "mt8188_tas2563_5682";
audio-routing =
"ETDM1_OUT", "ETDM_SPK_PIN",
"ETDM2_OUT", "ETDM_HP_PIN",
"ETDM1_IN", "ETDM_SPK_PIN",
"ETDM2_IN", "ETDM_HP_PIN",
"ADDA Capture", "MTKAIF_PIN",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR",
"IN1P", "Headset Mic";
dai-link-1 {
codec {
sound-dai = <&tas2563>;
};
};
};

72
arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku5.dts Normal file
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@ -0,0 +1,72 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2024 Google LLC
*/
/dts-v1/;
#include "mt8188-geralt-ciri.dtsi"
/ {
model = "Google Ciri sku5 board (rev4)";
compatible = "google,ciri-sku5", "google,ciri", "mediatek,mt8188";
};
&dsi_panel {
compatible = "ivo,t109nw41", "himax,hx83102";
};
&i2c0 {
/delete-node/ audio-codec@1a;
/delete-node/ amplifier@38;
/delete-node/ amplifier@39;
es8326: audio-codec@19 {
compatible = "everest,es8326";
reg = <0x19>;
interrupts-extended = <&pio 108 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&audio_codec_pins>;
#sound-dai-cells = <0>;
everest,jack-pol = [0e];
everest,interrupt-clk = [00];
};
tas2563: amplifier@4f {
compatible = "ti,tas2563", "ti,tas2781";
reg = <0x4f>, <0x4c>; /* left / right channel */
reset-gpios = <&pio 118 GPIO_ACTIVE_HIGH>;
#sound-dai-cells = <0>;
};
};
&sound {
compatible = "mediatek,mt8188-es8326";
model = "mt8188_tas2563_8326";
audio-routing =
"ETDM1_OUT", "ETDM_SPK_PIN",
"ETDM2_OUT", "ETDM_HP_PIN",
"ETDM1_IN", "ETDM_SPK_PIN",
"ETDM2_IN", "ETDM_HP_PIN",
"ADDA Capture", "MTKAIF_PIN",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR",
"MIC1", "Headset Mic";
dai-link-1 {
codec {
sound-dai = <&tas2563>;
};
};
dai-link-2 {
codec {
sound-dai = <&es8326>;
};
};
dai-link-3 {
codec {
sound-dai = <&es8326>;
};
};
};

72
arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku6.dts Normal file
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@ -0,0 +1,72 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2024 Google LLC
*/
/dts-v1/;
#include "mt8188-geralt-ciri.dtsi"
/ {
model = "Google Ciri sku6 board (rev4)";
compatible = "google,ciri-sku6", "google,ciri", "mediatek,mt8188";
};
&dsi_panel {
compatible = "boe,nv110wum-l60", "himax,hx83102";
};
&i2c0 {
/delete-node/ audio-codec@1a;
/delete-node/ amplifier@38;
/delete-node/ amplifier@39;
es8326: audio-codec@19 {
compatible = "everest,es8326";
reg = <0x19>;
interrupts-extended = <&pio 108 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&audio_codec_pins>;
#sound-dai-cells = <0>;
everest,jack-pol = [0e];
everest,interrupt-clk = [00];
};
tas2563: amplifier@4f {
compatible = "ti,tas2563", "ti,tas2781";
reg = <0x4f>, <0x4c>; /* left / right channel */
reset-gpios = <&pio 118 GPIO_ACTIVE_HIGH>;
#sound-dai-cells = <0>;
};
};
&sound {
compatible = "mediatek,mt8188-es8326";
model = "mt8188_tas2563_8326";
audio-routing =
"ETDM1_OUT", "ETDM_SPK_PIN",
"ETDM2_OUT", "ETDM_HP_PIN",
"ETDM1_IN", "ETDM_SPK_PIN",
"ETDM2_IN", "ETDM_HP_PIN",
"ADDA Capture", "MTKAIF_PIN",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR",
"MIC1", "Headset Mic";
dai-link-1 {
codec {
sound-dai = <&tas2563>;
};
};
dai-link-2 {
codec {
sound-dai = <&es8326>;
};
};
dai-link-3 {
codec {
sound-dai = <&es8326>;
};
};
};

48
arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri-sku7.dts Normal file
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@ -0,0 +1,48 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2024 Google LLC
*/
/dts-v1/;
#include "mt8188-geralt-ciri.dtsi"
/ {
model = "Google Ciri sku7 board (rev4)";
compatible = "google,ciri-sku7", "google,ciri", "mediatek,mt8188";
};
&dsi_panel {
compatible = "ivo,t109nw41", "himax,hx83102";
};
&i2c0 {
/delete-node/ amplifier@38;
/delete-node/ amplifier@39;
tas2563: amplifier@4f {
compatible = "ti,tas2563", "ti,tas2781";
reg = <0x4f>, <0x4c>; /* left / right channel */
reset-gpios = <&pio 118 GPIO_ACTIVE_HIGH>;
#sound-dai-cells = <0>;
};
};
&sound {
compatible = "mediatek,mt8188-rt5682s";
model = "mt8188_tas2563_5682";
audio-routing =
"ETDM1_OUT", "ETDM_SPK_PIN",
"ETDM2_OUT", "ETDM_HP_PIN",
"ETDM1_IN", "ETDM_SPK_PIN",
"ETDM2_IN", "ETDM_HP_PIN",
"ADDA Capture", "MTKAIF_PIN",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR",
"IN1P", "Headset Mic";
dai-link-1 {
codec {
sound-dai = <&tas2563>;
};
};
};

316
arch/arm64/boot/dts/mediatek/mt8188-geralt-ciri.dtsi Normal file
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@ -0,0 +1,316 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2023 Google LLC
*/
/dts-v1/;
#include "mt8188-geralt.dtsi"
&aud_etdm_hp_on {
pins-mclk {
pinmux = <PINMUX_GPIO114__FUNC_O_I2SO2_MCK>;
};
};
&aud_etdm_hp_off {
pins-mclk {
pinmux = <PINMUX_GPIO114__FUNC_B_GPIO114>;
bias-pull-down;
input-enable;
};
};
&i2c0 {
rt5682s: audio-codec@1a {
compatible = "realtek,rt5682s";
reg = <0x1a>;
interrupts-extended = <&pio 108 IRQ_TYPE_EDGE_BOTH>;
pinctrl-names = "default";
pinctrl-0 = <&audio_codec_pins>;
#sound-dai-cells = <1>;
AVDD-supply = <&mt6359_vio18_ldo_reg>;
DBVDD-supply = <&mt6359_vio18_ldo_reg>;
LDO1-IN-supply = <&mt6359_vio18_ldo_reg>;
MICVDD-supply = <&pp3300_s3>;
realtek,jd-src = <1>;
};
max98390_38: amplifier@38 {
compatible = "maxim,max98390";
reg = <0x38>;
sound-name-prefix = "Front Right";
reset-gpios = <&pio 118 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&speaker_en>;
#sound-dai-cells = <0>;
};
max98390_39: amplifier@39 {
compatible = "maxim,max98390";
reg = <0x39>;
sound-name-prefix = "Front Left";
#sound-dai-cells = <0>;
};
};
&i2c_tunnel {
/*
* The virtual battery I2C addr is 0xf on Ciri, so we describe it
* manually instead of including 'arm/cros-ec-sbs.dtsi'.
**/
battery: sbs-battery@f {
compatible = "sbs,sbs-battery";
reg = <0xf>;
sbs,i2c-retry-count = <2>;
sbs,poll-retry-count = <1>;
};
};
&mipi_tx_config0 {
drive-strength-microamp = <5200>;
};
&mt6359_vm18_ldo_reg {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1900000>;
regulator-microvolt-offset = <100000>;
};
&sound {
dai-link-0 {
link-name = "ETDM1_IN_BE";
dai-format = "i2s";
mediatek,clk-provider = "cpu";
};
dai-link-1 {
link-name = "ETDM1_OUT_BE";
dai-format = "i2s";
mediatek,clk-provider = "cpu";
codec {
sound-dai = <&max98390_38>,
<&max98390_39>;
};
};
dai-link-2 {
link-name = "ETDM2_IN_BE";
mediatek,clk-provider = "cpu";
codec {
sound-dai = <&rt5682s 0>;
};
};
dai-link-3 {
link-name = "ETDM2_OUT_BE";
mediatek,clk-provider = "cpu";
codec {
sound-dai = <&rt5682s 0>;
};
};
dai-link-4 {
link-name = "DPTX_BE";
codec {
sound-dai = <&dp_tx>;
};
};
};
&pio {
gpio-line-names =
"GSC_AP_INT_ODL",
"AP_DISP_BKLTEN",
"",
"EN_PPVAR_MIPI_DISP",
"EN_PPVAR_MIPI_DISP_150MA",
"TCHSCR_RST_1V8_L",
"",
"",
"",
"",
"",
"I2S_SPKR_DATAOUT",
"EN_PP3300_WLAN_X",
"WIFI_KILL_1V8_L",
"BT_KILL_1V8_L",
"AP_FLASH_WP_L", /* ... is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */
"",
"",
"WCAM_PWDN_L",
"WCAM_RST_L",
"UCAM_PWDM_L",
"UCAM_RST_L",
"WCAM_24M_CLK",
"UCAM_24M_CLK",
"MT6319_INT",
"DISP_RST_1V8_L",
"DSIO_DSI_TE",
"",
"TP",
"MIPI_BL_PWM_1V8",
"",
"UART_AP_TX_GSC_RX",
"UART_GSC_TX_AP_RX",
"UART_SSPM_TX_DBGCON_RX",
"UART_DBGCON_TX_SSPM_RX",
"UART_ADSP_TX_DBGCON_RX",
"UART_DBGCON_TX_ADSP_RX",
"JTAG_AP_TMS",
"JTAG_AP_TCK",
"JTAG_AP_TDI",
"JTAG_AP_TDO",
"JTAG_AP_TRST",
"AP_KPCOL0",
"TP",
"",
"TP",
"EC_AP_HPD_OD",
"PCIE_WAKE_1V8_ODL",
"PCIE_RST_1V8_L",
"PCIE_CLKREQ_1V8_ODL",
"",
"",
"",
"",
"",
"AP_I2C_AUD_SCL_1V8",
"AP_I2C_AUD_SDA_1V8",
"AP_I2C_TPM_SCL_1V8",
"AP_I2C_TPM_SDA_1V8",
"AP_I2C_TCHSCR_SCL_1V8",
"AP_I2C_TCHSCR_SDA_1V8",
"AP_I2C_PMIC_SAR_SCL_1V8",
"AP_I2C_PMIC_SAR_SDA_1V8",
"AP_I2C_EC_HID_KB_SCL_1V8",
"AP_I2C_EC_HID_KB_SDA_1V8",
"AP_I2C_UCAM_SCL_1V8",
"AP_I2C_UCAM_SDA_1V8",
"AP_I2C_WCAM_SCL_1V8",
"AP_I2C_WCAM_SDA_1V8",
"SPI_AP_CS_EC_L",
"SPI_AP_CLK_EC",
"SPI_AP_DO_EC_DI",
"SPI_AP_DI_EC_DO",
"TP",
"TP",
"SPI_AP_CS_TCHSCR_L",
"SPI_AP_CLK_TCHSCR",
"SPI_AP_DO_TCHSCR_DI",
"SPI_AP_DI_TCHSCR_DO",
"TP",
"TP",
"TP",
"TP",
"",
"",
"",
"TP",
"",
"",
"",
"",
"",
"PWRAP_SPI_CS_L",
"PWRAP_SPI_CK",
"PWRAP_SPI_MOSI",
"PWRAP_SPI_MISO",
"SRCLKENA0",
"SRCLKENA1",
"SCP_VREQ_VAO",
"AP_RTC_CLK32K",
"AP_PMIC_WDTRST_L",
"AUD_CLK_MOSI",
"AUD_SYNC_MOSI",
"AUD_DAT_MOSI0",
"AUD_DAT_MOSI1",
"AUD_DAT_MISO0",
"AUD_DAT_MISO1",
"",
"HP_INT_ODL",
"SPKR_INT_ODL",
"I2S_HP_DATAIN",
"EN_SPKR",
"I2S_SPKR_MCLK",
"I2S_SPKR_BCLK",
"I2S_HP_MCLK",
"I2S_HP_BCLK",
"I2S_HP_LRCK",
"I2S_HP_DATAOUT",
"RST_SPKR_L",
"I2S_SPKR_LRCK",
"I2S_SPKR_DATAIN",
"",
"",
"",
"",
"SPI_AP_CLK_ROM",
"SPI_AP_CS_ROM_L",
"SPI_AP_DO_ROM_DI",
"SPI_AP_DI_ROM_DO",
"TP",
"TP",
"",
"",
"",
"",
"",
"",
"",
"",
"EN_PP2800A_UCAM_X",
"EN_PP1200_UCAM_X",
"EN_PP2800A_WCAM_X",
"EN_PP1100_WCAM_X",
"TCHSCR_INT_1V8_L",
"",
"MT7921_PMU_EN_1V8",
"",
"AP_EC_WARM_RST_REQ",
"EC_AP_HID_INT_ODL",
"EC_AP_INT_ODL",
"AP_XHCI_INIT_DONE",
"EMMC_DAT7",
"EMMC_DAT6",
"EMMC_DAT5",
"EMMC_DAT4",
"EMMC_RST_L",
"EMMC_CMD",
"EMMC_CLK",
"EMMC_DAT3",
"EMMC_DAT2",
"EMMC_DAT1",
"EMMC_DAT0",
"EMMC_DSL",
"",
"",
"",
"",
"",
"",
"",
"",
"USB3_HUB_RST_L",
"EC_AP_RSVD0_ODL",
"",
"",
"SPMI_SCL",
"SPMI_SDA";
audio_codec_pins: audio-codec-pins {
pins-hp-int-odl {
pinmux = <PINMUX_GPIO108__FUNC_B_GPIO108>;
input-enable;
};
};
speaker_en: speaker-en-pins {
pins-en-spkr {
pinmux = <PINMUX_GPIO111__FUNC_B_GPIO111>;
};
};
};

1156
arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

7
arch/arm64/boot/dts/mediatek/mt8188.dtsi
View File

@ -2125,6 +2125,11 @@ lvts_efuse_data1: lvts1-calib@1ac {
reg = <0x1ac 0x40>;
};
gpu_speedbin: gpu-speedbin@581 {
reg = <0x581 0x1>;
bits = <0 3>;
};
socinfo-data1@7a0 {
reg = <0x7a0 0x4>;
};
@ -2143,6 +2148,8 @@ gpu: gpu@13000000 {
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "job", "mmu", "gpu";
nvmem-cells = <&gpu_speedbin>;
nvmem-cell-names = "speed-bin";
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>,
<&spm MT8188_POWER_DOMAIN_MFG3>,

3
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
View File

@ -1418,7 +1418,6 @@ mt6315_6: pmic@6 {
regulators {
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
@ -1428,7 +1427,6 @@ mt6315_6_vbuck1: vbuck1 {
};
mt6315_6_vbuck3: vbuck3 {
regulator-compatible = "vbuck3";
regulator-name = "Vlcpu";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
@ -1445,7 +1443,6 @@ mt6315_7: pmic@7 {
regulators {
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <800000>;

2
arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
View File

@ -1285,7 +1285,6 @@ mt6315@6 {
regulators {
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;
@ -1303,7 +1302,6 @@ mt6315@7 {
regulators {
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1193750>;

9
arch/arm64/boot/dts/mediatek/mt8195-demo.dts
View File

@ -137,7 +137,6 @@ charger {
richtek,vinovp-microvolt = <14500000>;
otg_vbus_regulator: usb-otg-vbus-regulator {
regulator-compatible = "usb-otg-vbus";
regulator-name = "usb-otg-vbus";
regulator-min-microvolt = <4425000>;
regulator-max-microvolt = <5825000>;
@ -149,7 +148,6 @@ regulator {
LDO_VIN3-supply = <&mt6360_buck2>;
mt6360_buck1: buck1 {
regulator-compatible = "BUCK1";
regulator-name = "mt6360,buck1";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1300000>;
@ -160,7 +158,6 @@ MT6360_OPMODE_LP
};
mt6360_buck2: buck2 {
regulator-compatible = "BUCK2";
regulator-name = "mt6360,buck2";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1300000>;
@ -171,7 +168,6 @@ MT6360_OPMODE_LP
};
mt6360_ldo1: ldo1 {
regulator-compatible = "LDO1";
regulator-name = "mt6360,ldo1";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
@ -180,7 +176,6 @@ mt6360_ldo1: ldo1 {
};
mt6360_ldo2: ldo2 {
regulator-compatible = "LDO2";
regulator-name = "mt6360,ldo2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
@ -189,7 +184,6 @@ mt6360_ldo2: ldo2 {
};
mt6360_ldo3: ldo3 {
regulator-compatible = "LDO3";
regulator-name = "mt6360,ldo3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3600000>;
@ -198,7 +192,6 @@ mt6360_ldo3: ldo3 {
};
mt6360_ldo5: ldo5 {
regulator-compatible = "LDO5";
regulator-name = "mt6360,ldo5";
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3600000>;
@ -207,7 +200,6 @@ mt6360_ldo5: ldo5 {
};
mt6360_ldo6: ldo6 {
regulator-compatible = "LDO6";
regulator-name = "mt6360,ldo6";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2100000>;
@ -216,7 +208,6 @@ mt6360_ldo6: ldo6 {
};
mt6360_ldo7: ldo7 {
regulator-compatible = "LDO7";
regulator-name = "mt6360,ldo7";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2100000>;

3
arch/arm64/boot/dts/mediatek/mt8195.dtsi
View File

@ -1611,9 +1611,6 @@ pcie1: pcie@112f8000 {
phy-names = "pcie-phy";
power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
resets = <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>;
reset-names = "mac";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,

48
arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts
View File

@ -93,6 +93,24 @@ vpu_mem: memory@57000000 {
compatible = "shared-dma-pool";
reg = <0 0x57000000 0 0x1400000>; /* 20 MB */
};
adsp_mem: memory@60000000 {
compatible = "shared-dma-pool";
reg = <0 0x60000000 0 0xf00000>;
no-map;
};
afe_dma_mem: memory@60f00000 {
compatible = "shared-dma-pool";
reg = <0 0x60f00000 0 0x100000>;
no-map;
};
adsp_dma_mem: memory@61000000 {
compatible = "shared-dma-pool";
reg = <0 0x61000000 0 0x100000>;
no-map;
};
};
common_fixed_5v: regulator-0 {
@ -210,6 +228,16 @@ usb_p2_vbus: regulator-9 {
};
};
&adsp {
memory-region = <&adsp_dma_mem>, <&adsp_mem>;
status = "okay";
};
&afe {
memory-region = <&afe_dma_mem>;
status = "okay";
};
&gpu {
mali-supply = <&mt6359_vproc2_buck_reg>;
status = "okay";
@ -932,6 +960,26 @@ &scp {
status = "okay";
};
&sound {
compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb";
model = "mt8390-evk";
pinctrl-names = "default";
pinctrl-0 = <&audio_default_pins>;
audio-routing =
"Headphone", "Headphone L",
"Headphone", "Headphone R";
mediatek,adsp = <&adsp>;
status = "okay";
dai-link-0 {
link-name = "DL_SRC_BE";
codec {
sound-dai = <&pmic 0>;
};
};
};
&spi2 {
pinctrl-0 = <&spi2_pins>;
pinctrl-names = "default";

2
arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts
View File

@ -835,7 +835,6 @@ mt6315_6: pmic@6 {
regulators {
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1193750>;
@ -852,7 +851,6 @@ mt6315_7: pmic@7 {
regulators {
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <546000>;
regulator-max-microvolt = <787000>;

2
arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts
View File

@ -812,7 +812,6 @@ mt6315_6: pmic@6 {
regulators {
mt6315_6_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vbcpu";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1193750>;
@ -829,7 +828,6 @@ mt6315_7: pmic@7 {
regulators {
mt6315_7_vbuck1: vbuck1 {
regulator-compatible = "vbuck1";
regulator-name = "Vgpu";
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1193750>;

11
arch/arm64/boot/dts/mediatek/mt8516.dtsi
View File

@ -144,10 +144,10 @@ reserved-memory {
#size-cells = <2>;
ranges;
/* 128 KiB reserved for ARM Trusted Firmware (BL31) */
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
bl31_secmon_reserved: secmon@43000000 {
no-map;
reg = <0 0x43000000 0 0x20000>;
reg = <0 0x43000000 0 0x30000>;
};
};
@ -206,7 +206,7 @@ watchdog@10007000 {
compatible = "mediatek,mt8516-wdt",
"mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x1000>;
interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_FALLING>;
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
#reset-cells = <1>;
};
@ -268,7 +268,7 @@ gic: interrupt-controller@10310000 {
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x10310000 0 0x1000>,
<0 0x10320000 0 0x1000>,
<0 0x1032f000 0 0x2000>,
<0 0x10340000 0 0x2000>,
<0 0x10360000 0 0x2000>;
interrupts = <GIC_PPI 9
@ -344,6 +344,7 @@ i2c0: i2c@11009000 {
reg = <0 0x11009000 0 0x90>,
<0 0x11000180 0 0x80>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
clock-div = <2>;
clocks = <&topckgen CLK_TOP_I2C0>,
<&topckgen CLK_TOP_APDMA>;
clock-names = "main", "dma";
@ -358,6 +359,7 @@ i2c1: i2c@1100a000 {
reg = <0 0x1100a000 0 0x90>,
<0 0x11000200 0 0x80>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
clock-div = <2>;
clocks = <&topckgen CLK_TOP_I2C1>,
<&topckgen CLK_TOP_APDMA>;
clock-names = "main", "dma";
@ -372,6 +374,7 @@ i2c2: i2c@1100b000 {
reg = <0 0x1100b000 0 0x90>,
<0 0x11000280 0 0x80>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>;
clock-div = <2>;
clocks = <&topckgen CLK_TOP_I2C2>,
<&topckgen CLK_TOP_APDMA>;
clock-names = "main", "dma";

2
arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
View File

@ -47,7 +47,6 @@ key-volume-down {
};
&i2c0 {
clock-div = <2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins_a>;
status = "okay";
@ -156,7 +155,6 @@ cam-pwdn-hog {
};
&i2c2 {
clock-div = <2>;
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins_a>;
status = "okay";