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clk: mmp: pxa168: fix incorrect dividers

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These two clocks had multipliers and dividers that didn't match their
names. A subsequent commit goes through all of the existing peripherals
and ensure the correct clocks are being used everywhere.

Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-3-doug@schmorgal.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Doug Brown 2022-06-12 12:29:27 -07:00 committed by Stephen Boyd
parent a5ff3d8c85
commit a77a1e2f1b
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/mmp/clk-of-pxa168.c
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@ -88,8 +88,8 @@ static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
{PXA168_CLK_PLL1_96, "pll1_96", "pll1_48", 1, 2, 0},
{PXA168_CLK_PLL1_192, "pll1_192", "pll1_96", 1, 2, 0},
{PXA168_CLK_PLL1_13, "pll1_13", "pll1", 1, 13, 0},
{PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 2, 3, 0},
{PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 2, 3, 0},
{PXA168_CLK_PLL1_13_1_5, "pll1_13_1_5", "pll1_13", 1, 5, 0},
{PXA168_CLK_PLL1_2_1_5, "pll1_2_1_5", "pll1_2", 1, 5, 0},
{PXA168_CLK_PLL1_3_16, "pll1_3_16", "pll1", 3, 16, 0},
};