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RISC-V: Don't include Zicsr or Zifencei in I from ACPI

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ACPI ISA strings are based on a specification after Zicsr and Zifencei
were split out of I, so we shouldn't be treating them as part of I.  We
haven't release an ACPI-based kernel yet, so we don't need to worry
about compatibility with the old ISA strings.

Fixes: 07edc32779e3 ("RISC-V: always report presence of extensions formerly part of the base ISA")
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
Link: https://lore.kernel.org/r/20230711224600.10879-1-palmer@rivosinc.com
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Palmer Dabbelt 2023-07-11 15:46:00 -07:00
parent b690e266da
commit ab2dbc7acc
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GPG Key ID: 2E1319F35FBB1889
1 changed files with 2 additions and 7 deletions
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9
arch/riscv/kernel/cpufeature.c
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@ -317,19 +317,14 @@ void __init riscv_fill_hwcap(void)
#undef SET_ISA_EXT_MAP #undef SET_ISA_EXT_MAP
} }
/*
* Linux requires the following extensions, so we may as well
* always set them.
*/
set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
/* /*
* These ones were as they were part of the base ISA when the * These ones were as they were part of the base ISA when the
* port & dt-bindings were upstreamed, and so can be set * port & dt-bindings were upstreamed, and so can be set
* unconditionally where `i` is in riscv,isa on DT systems. * unconditionally where `i` is in riscv,isa on DT systems.
*/ */
if (acpi_disabled) { if (acpi_disabled) {
set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa); set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa);
set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa); set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa);
} }