mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
synced 2025-01-16 13:34:30 +00:00
Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
No conflicts. Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
accc3b4a57
3
.mailmap
3
.mailmap
@ -71,6 +71,9 @@ Ben M Cahill <ben.m.cahill@intel.com>
|
||||
Ben Widawsky <bwidawsk@kernel.org> <ben@bwidawsk.net>
|
||||
Ben Widawsky <bwidawsk@kernel.org> <ben.widawsky@intel.com>
|
||||
Ben Widawsky <bwidawsk@kernel.org> <benjamin.widawsky@intel.com>
|
||||
Bjorn Andersson <andersson@kernel.org> <bjorn@kryo.se>
|
||||
Bjorn Andersson <andersson@kernel.org> <bjorn.andersson@linaro.org>
|
||||
Bjorn Andersson <andersson@kernel.org> <bjorn.andersson@sonymobile.com>
|
||||
Björn Steinbrink <B.Steinbrink@gmx.de>
|
||||
Björn Töpel <bjorn@kernel.org> <bjorn.topel@gmail.com>
|
||||
Björn Töpel <bjorn@kernel.org> <bjorn.topel@intel.com>
|
||||
|
||||
@ -34,8 +34,8 @@ Example:
|
||||
Use specific request line passing from dma
|
||||
For example, MMC request line is 5
|
||||
|
||||
sdhci: sdhci@98e00000 {
|
||||
compatible = "moxa,moxart-sdhci";
|
||||
mmc: mmc@98e00000 {
|
||||
compatible = "moxa,moxart-mmc";
|
||||
reg = <0x98e00000 0x5C>;
|
||||
interrupts = <5 0>;
|
||||
clocks = <&clk_apb>;
|
||||
|
||||
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
title: i.MX8M DDR Controller
|
||||
|
||||
maintainers:
|
||||
- Leonard Crestez <leonard.crestez@nxp.com>
|
||||
- Peng Fan <peng.fan@nxp.com>
|
||||
|
||||
description:
|
||||
The DDRC block is integrated in i.MX8M for interfacing with DDR based
|
||||
|
||||
@ -40,6 +40,7 @@ properties:
|
||||
patternProperties:
|
||||
'^opp-?[0-9]+$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
opp-hz: true
|
||||
|
||||
@ -19,6 +19,7 @@ properties:
|
||||
patternProperties:
|
||||
'^opp-?[0-9]+$':
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
opp-level: true
|
||||
|
||||
@ -148,7 +148,7 @@ You can do plain I2C transactions by using read(2) and write(2) calls.
|
||||
You do not need to pass the address byte; instead, set it through
|
||||
ioctl I2C_SLAVE before you try to access the device.
|
||||
|
||||
You can do SMBus level transactions (see documentation file smbus-protocol
|
||||
You can do SMBus level transactions (see documentation file smbus-protocol.rst
|
||||
for details) through the following functions::
|
||||
|
||||
__s32 i2c_smbus_write_quick(int file, __u8 value);
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||||
|
||||
@ -32,9 +32,9 @@ User manual
|
||||
===========
|
||||
|
||||
I2C slave backends behave like standard I2C clients. So, you can instantiate
|
||||
them as described in the document 'instantiating-devices'. The only difference
|
||||
is that i2c slave backends have their own address space. So, you have to add
|
||||
0x1000 to the address you would originally request. An example for
|
||||
them as described in the document instantiating-devices.rst. The only
|
||||
difference is that i2c slave backends have their own address space. So, you
|
||||
have to add 0x1000 to the address you would originally request. An example for
|
||||
instantiating the slave-eeprom driver from userspace at the 7 bit address 0x64
|
||||
on bus 1::
|
||||
|
||||
|
||||
@ -364,7 +364,7 @@ stop condition is issued between transaction. The i2c_msg structure
|
||||
contains for each message the client address, the number of bytes of the
|
||||
message and the message data itself.
|
||||
|
||||
You can read the file ``i2c-protocol`` for more information about the
|
||||
You can read the file i2c-protocol.rst for more information about the
|
||||
actual I2C protocol.
|
||||
|
||||
|
||||
@ -414,7 +414,7 @@ transactions return 0 on success; the 'read' transactions return the read
|
||||
value, except for block transactions, which return the number of values
|
||||
read. The block buffers need not be longer than 32 bytes.
|
||||
|
||||
You can read the file ``smbus-protocol`` for more information about the
|
||||
You can read the file smbus-protocol.rst for more information about the
|
||||
actual SMBus protocol.
|
||||
|
||||
|
||||
|
||||
23
MAINTAINERS
23
MAINTAINERS
@ -671,7 +671,8 @@ F: fs/afs/
|
||||
F: include/trace/events/afs.h
|
||||
|
||||
AGPGART DRIVER
|
||||
M: David Airlie <airlied@linux.ie>
|
||||
M: David Airlie <airlied@redhat.com>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Maintained
|
||||
T: git git://anongit.freedesktop.org/drm/drm
|
||||
F: drivers/char/agp/
|
||||
@ -1017,7 +1018,6 @@ F: drivers/spi/spi-amd.c
|
||||
|
||||
AMD MP2 I2C DRIVER
|
||||
M: Elie Morisse <syniurge@gmail.com>
|
||||
M: Nehal Shah <nehal-bakulchandra.shah@amd.com>
|
||||
M: Shyam Sundar S K <shyam-sundar.s-k@amd.com>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
S: Maintained
|
||||
@ -2587,7 +2587,7 @@ W: http://www.armlinux.org.uk/
|
||||
|
||||
ARM/QUALCOMM SUPPORT
|
||||
M: Andy Gross <agross@kernel.org>
|
||||
M: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
M: Bjorn Andersson <andersson@kernel.org>
|
||||
R: Konrad Dybcio <konrad.dybcio@somainline.org>
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
S: Maintained
|
||||
@ -5253,6 +5253,7 @@ F: block/blk-throttle.c
|
||||
F: include/linux/blk-cgroup.h
|
||||
|
||||
CONTROL GROUP - CPUSET
|
||||
M: Waiman Long <longman@redhat.com>
|
||||
M: Zefan Li <lizefan.x@bytedance.com>
|
||||
L: cgroups@vger.kernel.org
|
||||
S: Maintained
|
||||
@ -6754,7 +6755,7 @@ F: Documentation/devicetree/bindings/display/panel/samsung,lms380kf01.yaml
|
||||
F: drivers/gpu/drm/panel/panel-widechips-ws2401.c
|
||||
|
||||
DRM DRIVERS
|
||||
M: David Airlie <airlied@linux.ie>
|
||||
M: David Airlie <airlied@gmail.com>
|
||||
M: Daniel Vetter <daniel@ffwll.ch>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
S: Maintained
|
||||
@ -8944,7 +8945,7 @@ F: include/linux/hw_random.h
|
||||
|
||||
HARDWARE SPINLOCK CORE
|
||||
M: Ohad Ben-Cohen <ohad@wizery.com>
|
||||
M: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
M: Bjorn Andersson <andersson@kernel.org>
|
||||
R: Baolin Wang <baolin.wang7@gmail.com>
|
||||
L: linux-remoteproc@vger.kernel.org
|
||||
S: Maintained
|
||||
@ -16133,7 +16134,7 @@ F: drivers/gpio/gpio-sama5d2-piobu.c
|
||||
F: drivers/pinctrl/pinctrl-at91*
|
||||
|
||||
PIN CONTROLLER - QUALCOMM
|
||||
M: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
M: Bjorn Andersson <andersson@kernel.org>
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/pinctrl/qcom,*.txt
|
||||
@ -16826,7 +16827,7 @@ F: Documentation/devicetree/bindings/media/*camss*
|
||||
F: drivers/media/platform/qcom/camss/
|
||||
|
||||
QUALCOMM CLOCK DRIVERS
|
||||
M: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
M: Bjorn Andersson <andersson@kernel.org>
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
S: Supported
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git
|
||||
@ -17316,7 +17317,7 @@ S: Supported
|
||||
F: fs/reiserfs/
|
||||
|
||||
REMOTE PROCESSOR (REMOTEPROC) SUBSYSTEM
|
||||
M: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
M: Bjorn Andersson <andersson@kernel.org>
|
||||
M: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||||
L: linux-remoteproc@vger.kernel.org
|
||||
S: Maintained
|
||||
@ -17329,7 +17330,7 @@ F: include/linux/remoteproc.h
|
||||
F: include/linux/remoteproc/
|
||||
|
||||
REMOTE PROCESSOR MESSAGING (RPMSG) SUBSYSTEM
|
||||
M: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
M: Bjorn Andersson <andersson@kernel.org>
|
||||
M: Mathieu Poirier <mathieu.poirier@linaro.org>
|
||||
L: linux-remoteproc@vger.kernel.org
|
||||
S: Maintained
|
||||
@ -19973,7 +19974,7 @@ S: Supported
|
||||
F: drivers/net/team/
|
||||
F: include/linux/if_team.h
|
||||
F: include/uapi/linux/if_team.h
|
||||
F: tools/testing/selftests/net/team/
|
||||
F: tools/testing/selftests/drivers/net/team/
|
||||
|
||||
TECHNOLOGIC SYSTEMS TS-5500 PLATFORM SUPPORT
|
||||
M: "Savoir-faire Linux Inc." <kernel@savoirfairelinux.com>
|
||||
@ -21580,7 +21581,7 @@ F: drivers/gpio/gpio-virtio.c
|
||||
F: include/uapi/linux/virtio_gpio.h
|
||||
|
||||
VIRTIO GPU DRIVER
|
||||
M: David Airlie <airlied@linux.ie>
|
||||
M: David Airlie <airlied@redhat.com>
|
||||
M: Gerd Hoffmann <kraxel@redhat.com>
|
||||
R: Gurchetan Singh <gurchetansingh@chromium.org>
|
||||
R: Chia-I Wu <olvaffe@gmail.com>
|
||||
|
||||
2
Makefile
2
Makefile
@ -2,7 +2,7 @@
|
||||
VERSION = 6
|
||||
PATCHLEVEL = 0
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc6
|
||||
EXTRAVERSION = -rc7
|
||||
NAME = Hurr durr I'ma ninja sloth
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
||||
@ -1502,8 +1502,7 @@
|
||||
mmc1: mmc@0 {
|
||||
compatible = "ti,am335-sdhci";
|
||||
ti,needs-special-reset;
|
||||
dmas = <&edma_xbar 24 0 0
|
||||
&edma_xbar 25 0 0>;
|
||||
dmas = <&edma 24 0>, <&edma 25 0>;
|
||||
dma-names = "tx", "rx";
|
||||
interrupts = <64>;
|
||||
reg = <0x0 0x1000>;
|
||||
|
||||
@ -25,6 +25,10 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usb4_tm {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&atl_tm {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@ -249,6 +249,7 @@
|
||||
/* 640x480 16bpp @ 25.175MHz is 36827428 bytes/s */
|
||||
max-memory-bandwidth = <40000000>;
|
||||
memory-region = <&impd1_ram>;
|
||||
dma-ranges;
|
||||
|
||||
port@0 {
|
||||
#address-cells = <1>;
|
||||
|
||||
@ -160,6 +160,7 @@
|
||||
|
||||
pci: pciv3@62000000 {
|
||||
compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
@ -261,7 +262,7 @@
|
||||
lm0: bus@c0000000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0xc0000000 0x10000000>;
|
||||
dma-ranges = <0x00000000 0x80000000 0x10000000>;
|
||||
dma-ranges = <0x00000000 0xc0000000 0x10000000>;
|
||||
reg = <0xc0000000 0x10000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@ -269,7 +270,7 @@
|
||||
lm1: bus@d0000000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0xd0000000 0x10000000>;
|
||||
dma-ranges = <0x00000000 0x80000000 0x10000000>;
|
||||
dma-ranges = <0x00000000 0xd0000000 0x10000000>;
|
||||
reg = <0xd0000000 0x10000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@ -277,7 +278,7 @@
|
||||
lm2: bus@e0000000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0xe0000000 0x10000000>;
|
||||
dma-ranges = <0x00000000 0x80000000 0x10000000>;
|
||||
dma-ranges = <0x00000000 0xe0000000 0x10000000>;
|
||||
reg = <0xe0000000 0x10000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@ -285,7 +286,7 @@
|
||||
lm3: bus@f0000000 {
|
||||
compatible = "simple-bus";
|
||||
ranges = <0x00000000 0xf0000000 0x10000000>;
|
||||
dma-ranges = <0x00000000 0x80000000 0x10000000>;
|
||||
dma-ranges = <0x00000000 0xf0000000 0x10000000>;
|
||||
reg = <0xf0000000 0x10000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
@ -541,13 +541,13 @@
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@ -79,7 +79,7 @@
|
||||
clocks = <&ref12>;
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
&mmc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@ -93,8 +93,8 @@
|
||||
clock-names = "PCLK";
|
||||
};
|
||||
|
||||
sdhci: sdhci@98e00000 {
|
||||
compatible = "moxa,moxart-sdhci";
|
||||
mmc: mmc@98e00000 {
|
||||
compatible = "moxa,moxart-mmc";
|
||||
reg = <0x98e00000 0x5C>;
|
||||
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk_apb>;
|
||||
|
||||
@ -18,8 +18,8 @@ config SOC_SP7021
|
||||
select ARM_PSCI
|
||||
select PINCTRL
|
||||
select PINCTRL_SPPCTL
|
||||
select SERIAL_SUNPLUS
|
||||
select SERIAL_SUNPLUS_CONSOLE
|
||||
select SERIAL_SUNPLUS if TTY
|
||||
select SERIAL_SUNPLUS_CONSOLE if TTY
|
||||
help
|
||||
Support for Sunplus SP7021 SoC. It is based on ARM 4-core
|
||||
Cortex-A7 with various peripherals (e.g.: I2C, SPI, SDIO,
|
||||
|
||||
@ -152,11 +152,11 @@
|
||||
* CPLD_reset is RESET_SOFT in schematic
|
||||
*/
|
||||
gpio-line-names =
|
||||
"CPLD_D[1]", "CPLD_int", "CPLD_reset", "",
|
||||
"", "CPLD_D[0]", "", "",
|
||||
"", "", "", "CPLD_D[2]",
|
||||
"CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", "CPLD_D[6]",
|
||||
"CPLD_D[7]", "", "", "",
|
||||
"CPLD_D[6]", "CPLD_int", "CPLD_reset", "",
|
||||
"", "CPLD_D[7]", "", "",
|
||||
"", "", "", "CPLD_D[5]",
|
||||
"CPLD_D[4]", "CPLD_D[3]", "CPLD_D[2]", "CPLD_D[1]",
|
||||
"CPLD_D[0]", "", "", "",
|
||||
"", "", "", "",
|
||||
"", "", "", "KBD_intK",
|
||||
"", "", "", "";
|
||||
|
||||
@ -5,7 +5,6 @@
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/phy/phy-imx8-pcie.h>
|
||||
#include "imx8mm-tqma8mqml.dtsi"
|
||||
#include "mba8mx.dtsi"
|
||||
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
* Copyright 2020-2021 TQ-Systems GmbH
|
||||
*/
|
||||
|
||||
#include <dt-bindings/phy/phy-imx8-pcie.h>
|
||||
#include "imx8mm.dtsi"
|
||||
|
||||
/ {
|
||||
|
||||
@ -367,8 +367,8 @@
|
||||
nxp,dvs-standby-voltage = <850000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-min-microvolt = <805000>;
|
||||
regulator-name = "On-module +VDD_ARM (BUCK2)";
|
||||
regulator-ramp-delay = <3125>;
|
||||
};
|
||||
@ -376,8 +376,8 @@
|
||||
reg_vdd_dram: BUCK3 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <950000>;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-min-microvolt = <805000>;
|
||||
regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)";
|
||||
};
|
||||
|
||||
@ -416,7 +416,7 @@
|
||||
reg_vdd_snvs: LDO2 {
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
regulator-max-microvolt = <900000>;
|
||||
regulator-max-microvolt = <800000>;
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-name = "On-module +V0.8_SNVS (LDO2)";
|
||||
};
|
||||
|
||||
@ -672,7 +672,6 @@
|
||||
<&clk IMX8MN_CLK_GPU_SHADER>,
|
||||
<&clk IMX8MN_CLK_GPU_BUS_ROOT>,
|
||||
<&clk IMX8MN_CLK_GPU_AHB>;
|
||||
resets = <&src IMX8MQ_RESET_GPU_RESET>;
|
||||
};
|
||||
|
||||
pgc_dispmix: power-domain@3 {
|
||||
|
||||
@ -57,13 +57,13 @@
|
||||
switch-1 {
|
||||
label = "S12";
|
||||
linux,code = <BTN_0>;
|
||||
gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
|
||||
gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
switch-2 {
|
||||
label = "S13";
|
||||
linux,code = <BTN_1>;
|
||||
gpios = <&gpio5 27 GPIO_ACTIVE_LOW>;
|
||||
gpios = <&gpio5 26 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -394,6 +394,8 @@
|
||||
|
||||
&pcf85063 {
|
||||
/* RTC_EVENT# is connected on MBa8MPxL */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcf85063>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
@ -630,6 +632,10 @@
|
||||
fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10>; /* Power enable */
|
||||
};
|
||||
|
||||
pinctrl_pcf85063: pcf85063grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x80>;
|
||||
};
|
||||
|
||||
/* LVDS Backlight */
|
||||
pinctrl_pwm2: pwm2grp {
|
||||
fsl,pins = <MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x14>;
|
||||
|
||||
@ -123,8 +123,7 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_reg_can>;
|
||||
regulator-name = "can2_stby";
|
||||
gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
@ -484,35 +483,40 @@
|
||||
lan1: port@0 {
|
||||
reg = <0>;
|
||||
label = "lan1";
|
||||
phy-mode = "internal";
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
};
|
||||
|
||||
lan2: port@1 {
|
||||
reg = <1>;
|
||||
label = "lan2";
|
||||
phy-mode = "internal";
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
};
|
||||
|
||||
lan3: port@2 {
|
||||
reg = <2>;
|
||||
label = "lan3";
|
||||
phy-mode = "internal";
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
};
|
||||
|
||||
lan4: port@3 {
|
||||
reg = <3>;
|
||||
label = "lan4";
|
||||
phy-mode = "internal";
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
};
|
||||
|
||||
lan5: port@4 {
|
||||
reg = <4>;
|
||||
label = "lan5";
|
||||
phy-mode = "internal";
|
||||
local-mac-address = [00 00 00 00 00 00];
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "cpu";
|
||||
ethernet = <&fec>;
|
||||
phy-mode = "rgmii-id";
|
||||
|
||||
@ -172,6 +172,7 @@
|
||||
compatible = "fsl,imx8ulp-pcc3";
|
||||
reg = <0x292d0000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
tpm5: tpm@29340000 {
|
||||
@ -270,6 +271,7 @@
|
||||
compatible = "fsl,imx8ulp-pcc4";
|
||||
reg = <0x29800000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
lpi2c6: i2c@29840000 {
|
||||
@ -414,6 +416,7 @@
|
||||
compatible = "fsl,imx8ulp-pcc5";
|
||||
reg = <0x2da70000 0x10000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -3374,6 +3374,8 @@
|
||||
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
|
||||
interconnect-names = "usb-ddr", "apps-usb";
|
||||
|
||||
wakeup-source;
|
||||
|
||||
usb_1_dwc3: usb@a600000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0 0x0a600000 0 0xe000>;
|
||||
@ -3384,7 +3386,6 @@
|
||||
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
maximum-speed = "super-speed";
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -235,13 +235,13 @@
|
||||
};
|
||||
|
||||
&remoteproc_adsp {
|
||||
firmware-name = "qcom/sc8280xp/qcadsp8280.mbn";
|
||||
firmware-name = "qcom/sc8280xp/LENOVO/21BX/qcadsp8280.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&remoteproc_nsp0 {
|
||||
firmware-name = "qcom/sc8280xp/qccdsp8280.mbn";
|
||||
firmware-name = "qcom/sc8280xp/LENOVO/21BX/qccdsp8280.mbn";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -3394,57 +3394,49 @@
|
||||
compute-cb@1 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <1>;
|
||||
iommus = <&apps_smmu 0x1401 0x2040>,
|
||||
<&apps_smmu 0x1421 0x0>,
|
||||
<&apps_smmu 0x2001 0x420>,
|
||||
<&apps_smmu 0x2041 0x0>;
|
||||
iommus = <&apps_smmu 0x1001 0x0460>;
|
||||
};
|
||||
|
||||
compute-cb@2 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <2>;
|
||||
iommus = <&apps_smmu 0x2 0x3440>,
|
||||
<&apps_smmu 0x22 0x3400>;
|
||||
iommus = <&apps_smmu 0x1002 0x0460>;
|
||||
};
|
||||
|
||||
compute-cb@3 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <3>;
|
||||
iommus = <&apps_smmu 0x3 0x3440>,
|
||||
<&apps_smmu 0x1423 0x0>,
|
||||
<&apps_smmu 0x2023 0x0>;
|
||||
iommus = <&apps_smmu 0x1003 0x0460>;
|
||||
};
|
||||
|
||||
compute-cb@4 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <4>;
|
||||
iommus = <&apps_smmu 0x4 0x3440>,
|
||||
<&apps_smmu 0x24 0x3400>;
|
||||
iommus = <&apps_smmu 0x1004 0x0460>;
|
||||
};
|
||||
|
||||
compute-cb@5 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <5>;
|
||||
iommus = <&apps_smmu 0x5 0x3440>,
|
||||
<&apps_smmu 0x25 0x3400>;
|
||||
iommus = <&apps_smmu 0x1005 0x0460>;
|
||||
};
|
||||
|
||||
compute-cb@6 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <6>;
|
||||
iommus = <&apps_smmu 0x6 0x3460>;
|
||||
iommus = <&apps_smmu 0x1006 0x0460>;
|
||||
};
|
||||
|
||||
compute-cb@7 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <7>;
|
||||
iommus = <&apps_smmu 0x7 0x3460>;
|
||||
iommus = <&apps_smmu 0x1007 0x0460>;
|
||||
};
|
||||
|
||||
compute-cb@8 {
|
||||
compatible = "qcom,fastrpc-compute-cb";
|
||||
reg = <8>;
|
||||
iommus = <&apps_smmu 0x8 0x3460>;
|
||||
iommus = <&apps_smmu 0x1008 0x0460>;
|
||||
};
|
||||
|
||||
/* note: secure cb9 in downstream */
|
||||
|
||||
@ -2128,7 +2128,7 @@
|
||||
|
||||
ufs_mem_phy: phy@1d87000 {
|
||||
compatible = "qcom,sm8350-qmp-ufs-phy";
|
||||
reg = <0 0x01d87000 0 0xe10>;
|
||||
reg = <0 0x01d87000 0 0x1c4>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
@ -2,8 +2,8 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
|
||||
* Copyright (c) 2020 Engicam srl
|
||||
* Copyright (c) 2020 Amarula Solutons
|
||||
* Copyright (c) 2020 Amarula Solutons(India)
|
||||
* Copyright (c) 2020 Amarula Solutions
|
||||
* Copyright (c) 2020 Amarula Solutions(India)
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
@ -88,3 +88,8 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&wlan_host_wake_l {
|
||||
/* Kevin has an external pull up, but Bob does not. */
|
||||
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
@ -244,6 +244,14 @@
|
||||
&edp {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* eDP PHY/clk don't sync reliably at anything other than 24 MHz. Only
|
||||
* set this here, because rk3399-gru.dtsi ensures we can generate this
|
||||
* off GPLL=600MHz, whereas some other RK3399 boards may not.
|
||||
*/
|
||||
assigned-clocks = <&cru PCLK_EDP>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
|
||||
ports {
|
||||
edp_out: port@1 {
|
||||
reg = <1>;
|
||||
@ -578,6 +586,7 @@ ap_i2c_tp: &i2c5 {
|
||||
};
|
||||
|
||||
wlan_host_wake_l: wlan-host-wake-l {
|
||||
/* Kevin has an external pull up, but Bob does not */
|
||||
rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
@ -62,7 +62,6 @@
|
||||
vcc5v0_host: vcc5v0-host-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>;
|
||||
enable-active-low;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
regulator-name = "vcc5v0_host";
|
||||
|
||||
@ -189,7 +189,6 @@
|
||||
|
||||
vcc3v3_sd: vcc3v3_sd {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-low;
|
||||
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc_sd_h>;
|
||||
|
||||
@ -506,7 +506,7 @@
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
|
||||
sd-uhs-sdr104;
|
||||
sd-uhs-sdr50;
|
||||
vmmc-supply = <&vcc3v3_sd>;
|
||||
vqmmc-supply = <&vccio_sd>;
|
||||
status = "okay";
|
||||
|
||||
@ -678,7 +678,7 @@
|
||||
};
|
||||
|
||||
&usb_host0_xhci {
|
||||
extcon = <&usb2phy0>;
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@ -656,7 +656,7 @@
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
vbus-supply = <&vcc5v0_usb_otg>;
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@ -581,7 +581,7 @@
|
||||
};
|
||||
|
||||
&usb2phy0_otg {
|
||||
vbus-supply = <&vcc5v0_usb_otg>;
|
||||
phy-supply = <&vcc5v0_usb_otg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@ -48,6 +48,7 @@ CONFIG_ARCH_KEEMBAY=y
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_ARCH_MESON=y
|
||||
CONFIG_ARCH_MVEBU=y
|
||||
CONFIG_ARCH_NXP=y
|
||||
CONFIG_ARCH_MXC=y
|
||||
CONFIG_ARCH_NPCM=y
|
||||
CONFIG_ARCH_QCOM=y
|
||||
|
||||
@ -237,7 +237,7 @@ static void amu_fie_setup(const struct cpumask *cpus)
|
||||
for_each_cpu(cpu, cpus) {
|
||||
if (!freq_counters_valid(cpu) ||
|
||||
freq_inv_set_max_ratio(cpu,
|
||||
cpufreq_get_hw_max_freq(cpu) * 1000,
|
||||
cpufreq_get_hw_max_freq(cpu) * 1000ULL,
|
||||
arch_timer_get_rate()))
|
||||
return;
|
||||
}
|
||||
|
||||
@ -2114,7 +2114,7 @@ static int finalize_hyp_mode(void)
|
||||
* at, which would end badly once inaccessible.
|
||||
*/
|
||||
kmemleak_free_part(__hyp_bss_start, __hyp_bss_end - __hyp_bss_start);
|
||||
kmemleak_free_part(__va(hyp_mem_base), hyp_mem_size);
|
||||
kmemleak_free_part_phys(hyp_mem_base, hyp_mem_size);
|
||||
return pkvm_drop_host_privileges();
|
||||
}
|
||||
|
||||
|
||||
@ -331,12 +331,6 @@ static void alloc_init_pud(pgd_t *pgdp, unsigned long addr, unsigned long end,
|
||||
}
|
||||
BUG_ON(p4d_bad(p4d));
|
||||
|
||||
/*
|
||||
* No need for locking during early boot. And it doesn't work as
|
||||
* expected with KASLR enabled.
|
||||
*/
|
||||
if (system_state != SYSTEM_BOOTING)
|
||||
mutex_lock(&fixmap_lock);
|
||||
pudp = pud_set_fixmap_offset(p4dp, addr);
|
||||
do {
|
||||
pud_t old_pud = READ_ONCE(*pudp);
|
||||
@ -368,15 +362,13 @@ static void alloc_init_pud(pgd_t *pgdp, unsigned long addr, unsigned long end,
|
||||
} while (pudp++, addr = next, addr != end);
|
||||
|
||||
pud_clear_fixmap();
|
||||
if (system_state != SYSTEM_BOOTING)
|
||||
mutex_unlock(&fixmap_lock);
|
||||
}
|
||||
|
||||
static void __create_pgd_mapping(pgd_t *pgdir, phys_addr_t phys,
|
||||
unsigned long virt, phys_addr_t size,
|
||||
pgprot_t prot,
|
||||
phys_addr_t (*pgtable_alloc)(int),
|
||||
int flags)
|
||||
static void __create_pgd_mapping_locked(pgd_t *pgdir, phys_addr_t phys,
|
||||
unsigned long virt, phys_addr_t size,
|
||||
pgprot_t prot,
|
||||
phys_addr_t (*pgtable_alloc)(int),
|
||||
int flags)
|
||||
{
|
||||
unsigned long addr, end, next;
|
||||
pgd_t *pgdp = pgd_offset_pgd(pgdir, virt);
|
||||
@ -400,8 +392,20 @@ static void __create_pgd_mapping(pgd_t *pgdir, phys_addr_t phys,
|
||||
} while (pgdp++, addr = next, addr != end);
|
||||
}
|
||||
|
||||
static void __create_pgd_mapping(pgd_t *pgdir, phys_addr_t phys,
|
||||
unsigned long virt, phys_addr_t size,
|
||||
pgprot_t prot,
|
||||
phys_addr_t (*pgtable_alloc)(int),
|
||||
int flags)
|
||||
{
|
||||
mutex_lock(&fixmap_lock);
|
||||
__create_pgd_mapping_locked(pgdir, phys, virt, size, prot,
|
||||
pgtable_alloc, flags);
|
||||
mutex_unlock(&fixmap_lock);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
|
||||
extern __alias(__create_pgd_mapping)
|
||||
extern __alias(__create_pgd_mapping_locked)
|
||||
void create_kpti_ng_temp_pgd(pgd_t *pgdir, phys_addr_t phys, unsigned long virt,
|
||||
phys_addr_t size, pgprot_t prot,
|
||||
phys_addr_t (*pgtable_alloc)(int), int flags);
|
||||
|
||||
@ -14,8 +14,6 @@
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
extern const struct plat_smp_ops loongson3_smp_ops;
|
||||
|
||||
#define LOONGSON_REG(x) \
|
||||
(*(volatile u32 *)((char *)TO_UNCACHE(LOONGSON_REG_BASE) + (x)))
|
||||
|
||||
|
||||
@ -14,6 +14,8 @@
|
||||
|
||||
__REF
|
||||
|
||||
.align 12
|
||||
|
||||
SYM_CODE_START(kernel_entry) # kernel entry point
|
||||
|
||||
/* Config direct window and set PG */
|
||||
|
||||
@ -461,11 +461,9 @@ asmlinkage void noinstr do_watch(struct pt_regs *regs)
|
||||
|
||||
asmlinkage void noinstr do_ri(struct pt_regs *regs)
|
||||
{
|
||||
int status = -1;
|
||||
int status = SIGILL;
|
||||
unsigned int opcode = 0;
|
||||
unsigned int __user *era = (unsigned int __user *)exception_era(regs);
|
||||
unsigned long old_era = regs->csr_era;
|
||||
unsigned long old_ra = regs->regs[1];
|
||||
irqentry_state_t state = irqentry_enter(regs);
|
||||
|
||||
local_irq_enable();
|
||||
@ -477,21 +475,12 @@ asmlinkage void noinstr do_ri(struct pt_regs *regs)
|
||||
|
||||
die_if_kernel("Reserved instruction in kernel code", regs);
|
||||
|
||||
compute_return_era(regs);
|
||||
|
||||
if (unlikely(get_user(opcode, era) < 0)) {
|
||||
status = SIGSEGV;
|
||||
current->thread.error_code = 1;
|
||||
}
|
||||
|
||||
if (status < 0)
|
||||
status = SIGILL;
|
||||
|
||||
if (unlikely(status > 0)) {
|
||||
regs->csr_era = old_era; /* Undo skip-over. */
|
||||
regs->regs[1] = old_ra;
|
||||
force_sig(status);
|
||||
}
|
||||
force_sig(status);
|
||||
|
||||
out:
|
||||
local_irq_disable();
|
||||
|
||||
@ -937,15 +937,6 @@ pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long addre
|
||||
pmd = *pmdp;
|
||||
pmd_clear(pmdp);
|
||||
|
||||
/*
|
||||
* pmdp collapse_flush need to ensure that there are no parallel gup
|
||||
* walk after this call. This is needed so that we can have stable
|
||||
* page ref count when collapsing a page. We don't allow a collapse page
|
||||
* if we have gup taken on the page. We can ensure that by sending IPI
|
||||
* because gup walk happens with IRQ disabled.
|
||||
*/
|
||||
serialize_against_pte_lookup(vma->vm_mm);
|
||||
|
||||
radix__flush_tlb_collapsed_pmd(vma->vm_mm, address);
|
||||
|
||||
return pmd;
|
||||
|
||||
@ -386,6 +386,7 @@ config RISCV_ISA_C
|
||||
config RISCV_ISA_SVPBMT
|
||||
bool "SVPBMT extension support"
|
||||
depends on 64BIT && MMU
|
||||
depends on !XIP_KERNEL
|
||||
select RISCV_ALTERNATIVE
|
||||
default y
|
||||
help
|
||||
|
||||
@ -46,7 +46,7 @@ config ERRATA_THEAD
|
||||
|
||||
config ERRATA_THEAD_PBMT
|
||||
bool "Apply T-Head memory type errata"
|
||||
depends on ERRATA_THEAD && 64BIT
|
||||
depends on ERRATA_THEAD && 64BIT && MMU
|
||||
select RISCV_ALTERNATIVE_EARLY
|
||||
default y
|
||||
help
|
||||
@ -57,7 +57,7 @@ config ERRATA_THEAD_PBMT
|
||||
|
||||
config ERRATA_THEAD_CMO
|
||||
bool "Apply T-Head cache management errata"
|
||||
depends on ERRATA_THEAD
|
||||
depends on ERRATA_THEAD && MMU
|
||||
select RISCV_DMA_NONCOHERENT
|
||||
default y
|
||||
help
|
||||
|
||||
@ -37,6 +37,7 @@ static bool errata_probe_cmo(unsigned int stage,
|
||||
if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
|
||||
return false;
|
||||
|
||||
riscv_cbom_block_size = L1_CACHE_BYTES;
|
||||
riscv_noncoherent_supported();
|
||||
return true;
|
||||
#else
|
||||
|
||||
@ -42,6 +42,11 @@ void flush_icache_mm(struct mm_struct *mm, bool local);
|
||||
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
/*
|
||||
* The T-Head CMO errata internally probe the CBOM block size, but otherwise
|
||||
* don't depend on Zicbom.
|
||||
*/
|
||||
extern unsigned int riscv_cbom_block_size;
|
||||
#ifdef CONFIG_RISCV_ISA_ZICBOM
|
||||
void riscv_init_cbom_blocksize(void);
|
||||
#else
|
||||
|
||||
@ -296,8 +296,8 @@ void __init setup_arch(char **cmdline_p)
|
||||
setup_smp();
|
||||
#endif
|
||||
|
||||
riscv_fill_hwcap();
|
||||
riscv_init_cbom_blocksize();
|
||||
riscv_fill_hwcap();
|
||||
apply_boot_alternatives();
|
||||
}
|
||||
|
||||
|
||||
@ -124,6 +124,8 @@ SYSCALL_DEFINE0(rt_sigreturn)
|
||||
if (restore_altstack(&frame->uc.uc_stack))
|
||||
goto badframe;
|
||||
|
||||
regs->cause = -1UL;
|
||||
|
||||
return regs->a0;
|
||||
|
||||
badframe:
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
#include <linux/of_device.h>
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
static unsigned int riscv_cbom_block_size = L1_CACHE_BYTES;
|
||||
unsigned int riscv_cbom_block_size;
|
||||
static bool noncoherent_supported;
|
||||
|
||||
void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
|
||||
@ -79,38 +79,41 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
|
||||
void riscv_init_cbom_blocksize(void)
|
||||
{
|
||||
struct device_node *node;
|
||||
unsigned long cbom_hartid;
|
||||
u32 val, probed_block_size;
|
||||
int ret;
|
||||
u32 val;
|
||||
|
||||
probed_block_size = 0;
|
||||
for_each_of_cpu_node(node) {
|
||||
unsigned long hartid;
|
||||
int cbom_hartid;
|
||||
|
||||
ret = riscv_of_processor_hartid(node, &hartid);
|
||||
if (ret)
|
||||
continue;
|
||||
|
||||
if (hartid < 0)
|
||||
continue;
|
||||
|
||||
/* set block-size for cbom extension if available */
|
||||
ret = of_property_read_u32(node, "riscv,cbom-block-size", &val);
|
||||
if (ret)
|
||||
continue;
|
||||
|
||||
if (!riscv_cbom_block_size) {
|
||||
riscv_cbom_block_size = val;
|
||||
if (!probed_block_size) {
|
||||
probed_block_size = val;
|
||||
cbom_hartid = hartid;
|
||||
} else {
|
||||
if (riscv_cbom_block_size != val)
|
||||
pr_warn("cbom-block-size mismatched between harts %d and %lu\n",
|
||||
if (probed_block_size != val)
|
||||
pr_warn("cbom-block-size mismatched between harts %lu and %lu\n",
|
||||
cbom_hartid, hartid);
|
||||
}
|
||||
}
|
||||
|
||||
if (probed_block_size)
|
||||
riscv_cbom_block_size = probed_block_size;
|
||||
}
|
||||
#endif
|
||||
|
||||
void riscv_noncoherent_supported(void)
|
||||
{
|
||||
WARN(!riscv_cbom_block_size,
|
||||
"Non-coherent DMA support enabled without a block size\n");
|
||||
noncoherent_supported = true;
|
||||
}
|
||||
|
||||
@ -489,6 +489,8 @@ enum prot_type {
|
||||
PROT_TYPE_ALC = 2,
|
||||
PROT_TYPE_DAT = 3,
|
||||
PROT_TYPE_IEP = 4,
|
||||
/* Dummy value for passing an initialized value when code != PGM_PROTECTION */
|
||||
PROT_NONE,
|
||||
};
|
||||
|
||||
static int trans_exc_ending(struct kvm_vcpu *vcpu, int code, unsigned long gva, u8 ar,
|
||||
@ -504,6 +506,10 @@ static int trans_exc_ending(struct kvm_vcpu *vcpu, int code, unsigned long gva,
|
||||
switch (code) {
|
||||
case PGM_PROTECTION:
|
||||
switch (prot) {
|
||||
case PROT_NONE:
|
||||
/* We should never get here, acts like termination */
|
||||
WARN_ON_ONCE(1);
|
||||
break;
|
||||
case PROT_TYPE_IEP:
|
||||
tec->b61 = 1;
|
||||
fallthrough;
|
||||
@ -968,8 +974,10 @@ static int guest_range_to_gpas(struct kvm_vcpu *vcpu, unsigned long ga, u8 ar,
|
||||
return rc;
|
||||
} else {
|
||||
gpa = kvm_s390_real_to_abs(vcpu, ga);
|
||||
if (kvm_is_error_gpa(vcpu->kvm, gpa))
|
||||
if (kvm_is_error_gpa(vcpu->kvm, gpa)) {
|
||||
rc = PGM_ADDRESSING;
|
||||
prot = PROT_NONE;
|
||||
}
|
||||
}
|
||||
if (rc)
|
||||
return trans_exc(vcpu, rc, ga, ar, mode, prot);
|
||||
@ -1112,8 +1120,6 @@ int access_guest_with_key(struct kvm_vcpu *vcpu, unsigned long ga, u8 ar,
|
||||
if (rc == PGM_PROTECTION && try_storage_prot_override)
|
||||
rc = access_guest_page_with_key(vcpu->kvm, mode, gpas[idx],
|
||||
data, fragment_len, PAGE_SPO_ACC);
|
||||
if (rc == PGM_PROTECTION)
|
||||
prot = PROT_TYPE_KEYC;
|
||||
if (rc)
|
||||
break;
|
||||
len -= fragment_len;
|
||||
@ -1123,6 +1129,10 @@ int access_guest_with_key(struct kvm_vcpu *vcpu, unsigned long ga, u8 ar,
|
||||
if (rc > 0) {
|
||||
bool terminate = (mode == GACC_STORE) && (idx > 0);
|
||||
|
||||
if (rc == PGM_PROTECTION)
|
||||
prot = PROT_TYPE_KEYC;
|
||||
else
|
||||
prot = PROT_NONE;
|
||||
rc = trans_exc_ending(vcpu, rc, ga, ar, mode, prot, terminate);
|
||||
}
|
||||
out_unlock:
|
||||
|
||||
@ -3324,7 +3324,7 @@ static void aen_host_forward(unsigned long si)
|
||||
if (gaite->count == 0)
|
||||
return;
|
||||
if (gaite->aisb != 0)
|
||||
set_bit_inv(gaite->aisbo, (unsigned long *)gaite->aisb);
|
||||
set_bit_inv(gaite->aisbo, phys_to_virt(gaite->aisb));
|
||||
|
||||
kvm = kvm_s390_pci_si_to_kvm(aift, si);
|
||||
if (!kvm)
|
||||
|
||||
@ -505,7 +505,7 @@ int kvm_arch_init(void *opaque)
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (kvm_s390_pci_interp_allowed()) {
|
||||
if (IS_ENABLED(CONFIG_VFIO_PCI_ZDEV_KVM)) {
|
||||
rc = kvm_s390_pci_init();
|
||||
if (rc) {
|
||||
pr_err("Unable to allocate AIFT for PCI\n");
|
||||
@ -527,7 +527,7 @@ out:
|
||||
void kvm_arch_exit(void)
|
||||
{
|
||||
kvm_s390_gib_destroy();
|
||||
if (kvm_s390_pci_interp_allowed())
|
||||
if (IS_ENABLED(CONFIG_VFIO_PCI_ZDEV_KVM))
|
||||
kvm_s390_pci_exit();
|
||||
debug_unregister(kvm_s390_dbf);
|
||||
debug_unregister(kvm_s390_dbf_uv);
|
||||
|
||||
@ -58,7 +58,7 @@ static int zpci_setup_aipb(u8 nisc)
|
||||
if (!zpci_aipb)
|
||||
return -ENOMEM;
|
||||
|
||||
aift->sbv = airq_iv_create(ZPCI_NR_DEVICES, AIRQ_IV_ALLOC, 0);
|
||||
aift->sbv = airq_iv_create(ZPCI_NR_DEVICES, AIRQ_IV_ALLOC, NULL);
|
||||
if (!aift->sbv) {
|
||||
rc = -ENOMEM;
|
||||
goto free_aipb;
|
||||
@ -71,7 +71,7 @@ static int zpci_setup_aipb(u8 nisc)
|
||||
rc = -ENOMEM;
|
||||
goto free_sbv;
|
||||
}
|
||||
aift->gait = (struct zpci_gaite *)page_to_phys(page);
|
||||
aift->gait = (struct zpci_gaite *)page_to_virt(page);
|
||||
|
||||
zpci_aipb->aipb.faisb = virt_to_phys(aift->sbv->vector);
|
||||
zpci_aipb->aipb.gait = virt_to_phys(aift->gait);
|
||||
@ -373,7 +373,7 @@ static int kvm_s390_pci_aif_disable(struct zpci_dev *zdev, bool force)
|
||||
gaite->gisc = 0;
|
||||
gaite->aisbo = 0;
|
||||
gaite->gisa = 0;
|
||||
aift->kzdev[zdev->aisb] = 0;
|
||||
aift->kzdev[zdev->aisb] = NULL;
|
||||
/* Clear zdev info */
|
||||
airq_iv_free_bit(aift->sbv, zdev->aisb);
|
||||
airq_iv_release(zdev->aibv);
|
||||
@ -672,23 +672,31 @@ out:
|
||||
|
||||
int kvm_s390_pci_init(void)
|
||||
{
|
||||
zpci_kvm_hook.kvm_register = kvm_s390_pci_register_kvm;
|
||||
zpci_kvm_hook.kvm_unregister = kvm_s390_pci_unregister_kvm;
|
||||
|
||||
if (!kvm_s390_pci_interp_allowed())
|
||||
return 0;
|
||||
|
||||
aift = kzalloc(sizeof(struct zpci_aift), GFP_KERNEL);
|
||||
if (!aift)
|
||||
return -ENOMEM;
|
||||
|
||||
spin_lock_init(&aift->gait_lock);
|
||||
mutex_init(&aift->aift_lock);
|
||||
zpci_kvm_hook.kvm_register = kvm_s390_pci_register_kvm;
|
||||
zpci_kvm_hook.kvm_unregister = kvm_s390_pci_unregister_kvm;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void kvm_s390_pci_exit(void)
|
||||
{
|
||||
mutex_destroy(&aift->aift_lock);
|
||||
zpci_kvm_hook.kvm_register = NULL;
|
||||
zpci_kvm_hook.kvm_unregister = NULL;
|
||||
|
||||
if (!kvm_s390_pci_interp_allowed())
|
||||
return;
|
||||
|
||||
mutex_destroy(&aift->aift_lock);
|
||||
|
||||
kfree(aift);
|
||||
}
|
||||
|
||||
@ -46,9 +46,9 @@ extern struct zpci_aift *aift;
|
||||
static inline struct kvm *kvm_s390_pci_si_to_kvm(struct zpci_aift *aift,
|
||||
unsigned long si)
|
||||
{
|
||||
if (!IS_ENABLED(CONFIG_VFIO_PCI_ZDEV_KVM) || aift->kzdev == 0 ||
|
||||
aift->kzdev[si] == 0)
|
||||
return 0;
|
||||
if (!IS_ENABLED(CONFIG_VFIO_PCI_ZDEV_KVM) || !aift->kzdev ||
|
||||
!aift->kzdev[si])
|
||||
return NULL;
|
||||
return aift->kzdev[si]->kvm;
|
||||
};
|
||||
|
||||
|
||||
@ -115,6 +115,9 @@
|
||||
#define INTEL_FAM6_RAPTORLAKE_P 0xBA
|
||||
#define INTEL_FAM6_RAPTORLAKE_S 0xBF
|
||||
|
||||
#define INTEL_FAM6_METEORLAKE 0xAC
|
||||
#define INTEL_FAM6_METEORLAKE_L 0xAA
|
||||
|
||||
/* "Small Core" Processors (Atom) */
|
||||
|
||||
#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
|
||||
|
||||
@ -729,6 +729,7 @@ struct kvm_vcpu_arch {
|
||||
struct fpu_guest guest_fpu;
|
||||
|
||||
u64 xcr0;
|
||||
u64 guest_supported_xcr0;
|
||||
|
||||
struct kvm_pio_request pio;
|
||||
void *pio_data;
|
||||
|
||||
@ -344,8 +344,11 @@ static vm_fault_t sgx_encl_eaug_page(struct vm_area_struct *vma,
|
||||
}
|
||||
|
||||
va_page = sgx_encl_grow(encl, false);
|
||||
if (IS_ERR(va_page))
|
||||
if (IS_ERR(va_page)) {
|
||||
if (PTR_ERR(va_page) == -EBUSY)
|
||||
vmret = VM_FAULT_NOPAGE;
|
||||
goto err_out_epc;
|
||||
}
|
||||
|
||||
if (va_page)
|
||||
list_add(&va_page->list, &encl->va_pages);
|
||||
|
||||
@ -49,9 +49,13 @@ static LIST_HEAD(sgx_dirty_page_list);
|
||||
* Reset post-kexec EPC pages to the uninitialized state. The pages are removed
|
||||
* from the input list, and made available for the page allocator. SECS pages
|
||||
* prepending their children in the input list are left intact.
|
||||
*
|
||||
* Return 0 when sanitization was successful or kthread was stopped, and the
|
||||
* number of unsanitized pages otherwise.
|
||||
*/
|
||||
static void __sgx_sanitize_pages(struct list_head *dirty_page_list)
|
||||
static unsigned long __sgx_sanitize_pages(struct list_head *dirty_page_list)
|
||||
{
|
||||
unsigned long left_dirty = 0;
|
||||
struct sgx_epc_page *page;
|
||||
LIST_HEAD(dirty);
|
||||
int ret;
|
||||
@ -59,7 +63,7 @@ static void __sgx_sanitize_pages(struct list_head *dirty_page_list)
|
||||
/* dirty_page_list is thread-local, no need for a lock: */
|
||||
while (!list_empty(dirty_page_list)) {
|
||||
if (kthread_should_stop())
|
||||
return;
|
||||
return 0;
|
||||
|
||||
page = list_first_entry(dirty_page_list, struct sgx_epc_page, list);
|
||||
|
||||
@ -92,12 +96,14 @@ static void __sgx_sanitize_pages(struct list_head *dirty_page_list)
|
||||
} else {
|
||||
/* The page is not yet clean - move to the dirty list. */
|
||||
list_move_tail(&page->list, &dirty);
|
||||
left_dirty++;
|
||||
}
|
||||
|
||||
cond_resched();
|
||||
}
|
||||
|
||||
list_splice(&dirty, dirty_page_list);
|
||||
return left_dirty;
|
||||
}
|
||||
|
||||
static bool sgx_reclaimer_age(struct sgx_epc_page *epc_page)
|
||||
@ -395,10 +401,7 @@ static int ksgxd(void *p)
|
||||
* required for SECS pages, whose child pages blocked EREMOVE.
|
||||
*/
|
||||
__sgx_sanitize_pages(&sgx_dirty_page_list);
|
||||
__sgx_sanitize_pages(&sgx_dirty_page_list);
|
||||
|
||||
/* sanity check: */
|
||||
WARN_ON(!list_empty(&sgx_dirty_page_list));
|
||||
WARN_ON(__sgx_sanitize_pages(&sgx_dirty_page_list));
|
||||
|
||||
while (!kthread_should_stop()) {
|
||||
if (try_to_freeze())
|
||||
|
||||
@ -315,7 +315,6 @@ static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct kvm_lapic *apic = vcpu->arch.apic;
|
||||
struct kvm_cpuid_entry2 *best;
|
||||
u64 guest_supported_xcr0;
|
||||
|
||||
best = kvm_find_cpuid_entry(vcpu, 1);
|
||||
if (best && apic) {
|
||||
@ -327,10 +326,16 @@ static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
|
||||
kvm_apic_set_version(vcpu);
|
||||
}
|
||||
|
||||
guest_supported_xcr0 =
|
||||
vcpu->arch.guest_supported_xcr0 =
|
||||
cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent);
|
||||
|
||||
vcpu->arch.guest_fpu.fpstate->user_xfeatures = guest_supported_xcr0;
|
||||
/*
|
||||
* FP+SSE can always be saved/restored via KVM_{G,S}ET_XSAVE, even if
|
||||
* XSAVE/XCRO are not exposed to the guest, and even if XSAVE isn't
|
||||
* supported by the host.
|
||||
*/
|
||||
vcpu->arch.guest_fpu.fpstate->user_xfeatures = vcpu->arch.guest_supported_xcr0 |
|
||||
XFEATURE_MASK_FPSSE;
|
||||
|
||||
kvm_update_pv_runtime(vcpu);
|
||||
|
||||
|
||||
@ -4132,6 +4132,9 @@ static int em_xsetbv(struct x86_emulate_ctxt *ctxt)
|
||||
{
|
||||
u32 eax, ecx, edx;
|
||||
|
||||
if (!(ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSXSAVE))
|
||||
return emulate_ud(ctxt);
|
||||
|
||||
eax = reg_read(ctxt, VCPU_REGS_RAX);
|
||||
edx = reg_read(ctxt, VCPU_REGS_RDX);
|
||||
ecx = reg_read(ctxt, VCPU_REGS_RCX);
|
||||
|
||||
@ -1596,6 +1596,8 @@ static void __rmap_add(struct kvm *kvm,
|
||||
rmap_head = gfn_to_rmap(gfn, sp->role.level, slot);
|
||||
rmap_count = pte_list_add(cache, spte, rmap_head);
|
||||
|
||||
if (rmap_count > kvm->stat.max_mmu_rmap_size)
|
||||
kvm->stat.max_mmu_rmap_size = rmap_count;
|
||||
if (rmap_count > RMAP_RECYCLE_THRESHOLD) {
|
||||
kvm_zap_all_rmap_sptes(kvm, rmap_head);
|
||||
kvm_flush_remote_tlbs_with_address(
|
||||
|
||||
@ -1011,15 +1011,10 @@ void kvm_load_host_xsave_state(struct kvm_vcpu *vcpu)
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(kvm_load_host_xsave_state);
|
||||
|
||||
static inline u64 kvm_guest_supported_xcr0(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return vcpu->arch.guest_fpu.fpstate->user_xfeatures;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_X86_64
|
||||
static inline u64 kvm_guest_supported_xfd(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return kvm_guest_supported_xcr0(vcpu) & XFEATURE_MASK_USER_DYNAMIC;
|
||||
return vcpu->arch.guest_supported_xcr0 & XFEATURE_MASK_USER_DYNAMIC;
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1042,7 +1037,7 @@ static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
|
||||
* saving. However, xcr0 bit 0 is always set, even if the
|
||||
* emulated CPU does not support XSAVE (see kvm_vcpu_reset()).
|
||||
*/
|
||||
valid_bits = kvm_guest_supported_xcr0(vcpu) | XFEATURE_MASK_FP;
|
||||
valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
|
||||
if (xcr0 & ~valid_bits)
|
||||
return 1;
|
||||
|
||||
@ -1070,6 +1065,7 @@ static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
|
||||
|
||||
int kvm_emulate_xsetbv(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
/* Note, #UD due to CR4.OSXSAVE=0 has priority over the intercept. */
|
||||
if (static_call(kvm_x86_get_cpl)(vcpu) != 0 ||
|
||||
__kvm_set_xcr(vcpu, kvm_rcx_read(vcpu), kvm_read_edx_eax(vcpu))) {
|
||||
kvm_inject_gp(vcpu, 0);
|
||||
|
||||
@ -44,7 +44,7 @@ copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
|
||||
* called from other contexts.
|
||||
*/
|
||||
pagefault_disable();
|
||||
ret = __copy_from_user_inatomic(to, from, n);
|
||||
ret = raw_copy_from_user(to, from, n);
|
||||
pagefault_enable();
|
||||
|
||||
return ret;
|
||||
|
||||
@ -4,10 +4,12 @@ KCOV_INSTRUMENT_tlb.o := n
|
||||
KCOV_INSTRUMENT_mem_encrypt.o := n
|
||||
KCOV_INSTRUMENT_mem_encrypt_amd.o := n
|
||||
KCOV_INSTRUMENT_mem_encrypt_identity.o := n
|
||||
KCOV_INSTRUMENT_pgprot.o := n
|
||||
|
||||
KASAN_SANITIZE_mem_encrypt.o := n
|
||||
KASAN_SANITIZE_mem_encrypt_amd.o := n
|
||||
KASAN_SANITIZE_mem_encrypt_identity.o := n
|
||||
KASAN_SANITIZE_pgprot.o := n
|
||||
|
||||
# Disable KCSAN entirely, because otherwise we get warnings that some functions
|
||||
# reference __initdata sections.
|
||||
@ -17,6 +19,7 @@ ifdef CONFIG_FUNCTION_TRACER
|
||||
CFLAGS_REMOVE_mem_encrypt.o = -pg
|
||||
CFLAGS_REMOVE_mem_encrypt_amd.o = -pg
|
||||
CFLAGS_REMOVE_mem_encrypt_identity.o = -pg
|
||||
CFLAGS_REMOVE_pgprot.o = -pg
|
||||
endif
|
||||
|
||||
obj-y := init.o init_$(BITS).o fault.o ioremap.o extable.o mmap.o \
|
||||
|
||||
@ -602,7 +602,6 @@ void del_gendisk(struct gendisk *disk)
|
||||
* Prevent new I/O from crossing bio_queue_enter().
|
||||
*/
|
||||
blk_queue_start_drain(q);
|
||||
blk_mq_freeze_queue_wait(q);
|
||||
|
||||
if (!(disk->flags & GENHD_FL_HIDDEN)) {
|
||||
sysfs_remove_link(&disk_to_dev(disk)->kobj, "bdi");
|
||||
@ -626,6 +625,8 @@ void del_gendisk(struct gendisk *disk)
|
||||
pm_runtime_set_memalloc_noio(disk_to_dev(disk), false);
|
||||
device_del(disk_to_dev(disk));
|
||||
|
||||
blk_mq_freeze_queue_wait(q);
|
||||
|
||||
blk_throtl_cancel_bios(disk->queue);
|
||||
|
||||
blk_sync_queue(q);
|
||||
|
||||
@ -43,7 +43,7 @@ config SYSTEM_TRUSTED_KEYRING
|
||||
bool "Provide system-wide ring of trusted keys"
|
||||
depends on KEYS
|
||||
depends on ASYMMETRIC_KEY_TYPE
|
||||
depends on X509_CERTIFICATE_PARSER
|
||||
depends on X509_CERTIFICATE_PARSER = y
|
||||
help
|
||||
Provide a system keyring to which trusted keys can be added. Keys in
|
||||
the keyring are considered to be trusted. Keys may be added at will
|
||||
|
||||
@ -531,10 +531,27 @@ static void wait_for_freeze(void)
|
||||
/* No delay is needed if we are in guest */
|
||||
if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
|
||||
return;
|
||||
/*
|
||||
* Modern (>=Nehalem) Intel systems use ACPI via intel_idle,
|
||||
* not this code. Assume that any Intel systems using this
|
||||
* are ancient and may need the dummy wait. This also assumes
|
||||
* that the motivating chipset issue was Intel-only.
|
||||
*/
|
||||
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
|
||||
return;
|
||||
#endif
|
||||
/* Dummy wait op - must do something useless after P_LVL2 read
|
||||
because chipsets cannot guarantee that STPCLK# signal
|
||||
gets asserted in time to freeze execution properly. */
|
||||
/*
|
||||
* Dummy wait op - must do something useless after P_LVL2 read
|
||||
* because chipsets cannot guarantee that STPCLK# signal gets
|
||||
* asserted in time to freeze execution properly
|
||||
*
|
||||
* This workaround has been in place since the original ACPI
|
||||
* implementation was merged, circa 2002.
|
||||
*
|
||||
* If a profile is pointing to this instruction, please first
|
||||
* consider moving your system to a more modern idle
|
||||
* mechanism.
|
||||
*/
|
||||
inl(acpi_gbl_FADT.xpm_timer_block.address);
|
||||
}
|
||||
|
||||
|
||||
@ -3988,6 +3988,10 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
|
||||
{ "PIONEER DVD-RW DVR-212D", NULL, ATA_HORKAGE_NOSETXFER },
|
||||
{ "PIONEER DVD-RW DVR-216D", NULL, ATA_HORKAGE_NOSETXFER },
|
||||
|
||||
/* These specific Pioneer models have LPM issues */
|
||||
{ "PIONEER BD-RW BDR-207M", NULL, ATA_HORKAGE_NOLPM },
|
||||
{ "PIONEER BD-RW BDR-205", NULL, ATA_HORKAGE_NOLPM },
|
||||
|
||||
/* Crucial BX100 SSD 500GB has broken LPM support */
|
||||
{ "CT500BX100SSD1", NULL, ATA_HORKAGE_NOLPM },
|
||||
|
||||
|
||||
@ -1018,26 +1018,25 @@ DEVICE_ATTR(sw_activity, S_IWUSR | S_IRUGO, ata_scsi_activity_show,
|
||||
EXPORT_SYMBOL_GPL(dev_attr_sw_activity);
|
||||
|
||||
/**
|
||||
* __ata_change_queue_depth - helper for ata_scsi_change_queue_depth
|
||||
* @ap: ATA port to which the device change the queue depth
|
||||
* ata_change_queue_depth - Set a device maximum queue depth
|
||||
* @ap: ATA port of the target device
|
||||
* @dev: target ATA device
|
||||
* @sdev: SCSI device to configure queue depth for
|
||||
* @queue_depth: new queue depth
|
||||
*
|
||||
* libsas and libata have different approaches for associating a sdev to
|
||||
* its ata_port.
|
||||
* Helper to set a device maximum queue depth, usable with both libsas
|
||||
* and libata.
|
||||
*
|
||||
*/
|
||||
int __ata_change_queue_depth(struct ata_port *ap, struct scsi_device *sdev,
|
||||
int queue_depth)
|
||||
int ata_change_queue_depth(struct ata_port *ap, struct ata_device *dev,
|
||||
struct scsi_device *sdev, int queue_depth)
|
||||
{
|
||||
struct ata_device *dev;
|
||||
unsigned long flags;
|
||||
|
||||
if (queue_depth < 1 || queue_depth == sdev->queue_depth)
|
||||
if (!dev || !ata_dev_enabled(dev))
|
||||
return sdev->queue_depth;
|
||||
|
||||
dev = ata_scsi_find_dev(ap, sdev);
|
||||
if (!dev || !ata_dev_enabled(dev))
|
||||
if (queue_depth < 1 || queue_depth == sdev->queue_depth)
|
||||
return sdev->queue_depth;
|
||||
|
||||
/* NCQ enabled? */
|
||||
@ -1059,7 +1058,7 @@ int __ata_change_queue_depth(struct ata_port *ap, struct scsi_device *sdev,
|
||||
|
||||
return scsi_change_queue_depth(sdev, queue_depth);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(__ata_change_queue_depth);
|
||||
EXPORT_SYMBOL_GPL(ata_change_queue_depth);
|
||||
|
||||
/**
|
||||
* ata_scsi_change_queue_depth - SCSI callback for queue depth config
|
||||
@ -1080,7 +1079,8 @@ int ata_scsi_change_queue_depth(struct scsi_device *sdev, int queue_depth)
|
||||
{
|
||||
struct ata_port *ap = ata_shost_to_port(sdev->host);
|
||||
|
||||
return __ata_change_queue_depth(ap, sdev, queue_depth);
|
||||
return ata_change_queue_depth(ap, ata_scsi_find_dev(ap, sdev),
|
||||
sdev, queue_depth);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ata_scsi_change_queue_depth);
|
||||
|
||||
|
||||
@ -1055,6 +1055,7 @@ EXPORT_SYMBOL_GPL(ata_scsi_dma_need_drain);
|
||||
int ata_scsi_dev_config(struct scsi_device *sdev, struct ata_device *dev)
|
||||
{
|
||||
struct request_queue *q = sdev->request_queue;
|
||||
int depth = 1;
|
||||
|
||||
if (!ata_id_has_unload(dev->id))
|
||||
dev->flags |= ATA_DFLAG_NO_UNLOAD;
|
||||
@ -1100,13 +1101,10 @@ int ata_scsi_dev_config(struct scsi_device *sdev, struct ata_device *dev)
|
||||
if (dev->flags & ATA_DFLAG_AN)
|
||||
set_bit(SDEV_EVT_MEDIA_CHANGE, sdev->supported_events);
|
||||
|
||||
if (dev->flags & ATA_DFLAG_NCQ) {
|
||||
int depth;
|
||||
|
||||
if (dev->flags & ATA_DFLAG_NCQ)
|
||||
depth = min(sdev->host->can_queue, ata_id_queue_depth(dev->id));
|
||||
depth = min(ATA_MAX_QUEUE, depth);
|
||||
scsi_change_queue_depth(sdev, depth);
|
||||
}
|
||||
depth = min(ATA_MAX_QUEUE, depth);
|
||||
scsi_change_queue_depth(sdev, depth);
|
||||
|
||||
if (dev->flags & ATA_DFLAG_TRUSTED)
|
||||
sdev->security_supported = 1;
|
||||
|
||||
@ -1625,7 +1625,7 @@ static int __init fw_devlink_setup(char *arg)
|
||||
}
|
||||
early_param("fw_devlink", fw_devlink_setup);
|
||||
|
||||
static bool fw_devlink_strict = true;
|
||||
static bool fw_devlink_strict;
|
||||
static int __init fw_devlink_strict_setup(char *arg)
|
||||
{
|
||||
return strtobool(arg, &fw_devlink_strict);
|
||||
|
||||
@ -449,6 +449,9 @@ static int quad8_events_configure(struct counter_device *counter)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Enable IRQ line */
|
||||
irq_enabled |= BIT(event_node->channel);
|
||||
|
||||
/* Skip configuration if it is the same as previously set */
|
||||
if (priv->irq_trigger[event_node->channel] == next_irq_trigger)
|
||||
continue;
|
||||
@ -462,9 +465,6 @@ static int quad8_events_configure(struct counter_device *counter)
|
||||
priv->irq_trigger[event_node->channel] << 3;
|
||||
iowrite8(QUAD8_CTR_IOR | ior_cfg,
|
||||
&priv->reg->channel[event_node->channel].control);
|
||||
|
||||
/* Enable IRQ line */
|
||||
irq_enabled |= BIT(event_node->channel);
|
||||
}
|
||||
|
||||
iowrite8(irq_enabled, &priv->reg->index_interrupt);
|
||||
|
||||
@ -15,6 +15,7 @@ void hmem_register_device(int target_nid, struct resource *r)
|
||||
.start = r->start,
|
||||
.end = r->end,
|
||||
.flags = IORESOURCE_MEM,
|
||||
.desc = IORES_DESC_SOFT_RESERVED,
|
||||
};
|
||||
struct platform_device *pdev;
|
||||
struct memregion_info info;
|
||||
|
||||
@ -450,9 +450,13 @@ static int scmi_clock_count_get(const struct scmi_protocol_handle *ph)
|
||||
static const struct scmi_clock_info *
|
||||
scmi_clock_info_get(const struct scmi_protocol_handle *ph, u32 clk_id)
|
||||
{
|
||||
struct scmi_clock_info *clk;
|
||||
struct clock_info *ci = ph->get_priv(ph);
|
||||
struct scmi_clock_info *clk = ci->clk + clk_id;
|
||||
|
||||
if (clk_id >= ci->num_clocks)
|
||||
return NULL;
|
||||
|
||||
clk = ci->clk + clk_id;
|
||||
if (!clk->name[0])
|
||||
return NULL;
|
||||
|
||||
|
||||
@ -106,6 +106,7 @@ enum scmi_optee_pta_cmd {
|
||||
* @channel_id: OP-TEE channel ID used for this transport
|
||||
* @tee_session: TEE session identifier
|
||||
* @caps: OP-TEE SCMI channel capabilities
|
||||
* @rx_len: Response size
|
||||
* @mu: Mutex protection on channel access
|
||||
* @cinfo: SCMI channel information
|
||||
* @shmem: Virtual base address of the shared memory
|
||||
|
||||
@ -166,9 +166,13 @@ static int scmi_domain_reset(const struct scmi_protocol_handle *ph, u32 domain,
|
||||
struct scmi_xfer *t;
|
||||
struct scmi_msg_reset_domain_reset *dom;
|
||||
struct scmi_reset_info *pi = ph->get_priv(ph);
|
||||
struct reset_dom_info *rdom = pi->dom_info + domain;
|
||||
struct reset_dom_info *rdom;
|
||||
|
||||
if (rdom->async_reset)
|
||||
if (domain >= pi->num_domains)
|
||||
return -EINVAL;
|
||||
|
||||
rdom = pi->dom_info + domain;
|
||||
if (rdom->async_reset && flags & AUTONOMOUS_RESET)
|
||||
flags |= ASYNCHRONOUS_RESET;
|
||||
|
||||
ret = ph->xops->xfer_get_init(ph, RESET, sizeof(*dom), 0, &t);
|
||||
@ -180,7 +184,7 @@ static int scmi_domain_reset(const struct scmi_protocol_handle *ph, u32 domain,
|
||||
dom->flags = cpu_to_le32(flags);
|
||||
dom->reset_state = cpu_to_le32(state);
|
||||
|
||||
if (rdom->async_reset)
|
||||
if (flags & ASYNCHRONOUS_RESET)
|
||||
ret = ph->xops->do_xfer_with_response(ph, t);
|
||||
else
|
||||
ret = ph->xops->do_xfer(ph, t);
|
||||
|
||||
@ -8,7 +8,6 @@
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/pm_clock.h>
|
||||
#include <linux/pm_domain.h>
|
||||
#include <linux/scmi_protocol.h>
|
||||
|
||||
@ -53,27 +52,6 @@ static int scmi_pd_power_off(struct generic_pm_domain *domain)
|
||||
return scmi_pd_power(domain, false);
|
||||
}
|
||||
|
||||
static int scmi_pd_attach_dev(struct generic_pm_domain *pd, struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = pm_clk_create(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = of_pm_clk_add_clks(dev);
|
||||
if (ret >= 0)
|
||||
return 0;
|
||||
|
||||
pm_clk_destroy(dev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void scmi_pd_detach_dev(struct generic_pm_domain *pd, struct device *dev)
|
||||
{
|
||||
pm_clk_destroy(dev);
|
||||
}
|
||||
|
||||
static int scmi_pm_domain_probe(struct scmi_device *sdev)
|
||||
{
|
||||
int num_domains, i;
|
||||
@ -124,10 +102,6 @@ static int scmi_pm_domain_probe(struct scmi_device *sdev)
|
||||
scmi_pd->genpd.name = scmi_pd->name;
|
||||
scmi_pd->genpd.power_off = scmi_pd_power_off;
|
||||
scmi_pd->genpd.power_on = scmi_pd_power_on;
|
||||
scmi_pd->genpd.attach_dev = scmi_pd_attach_dev;
|
||||
scmi_pd->genpd.detach_dev = scmi_pd_detach_dev;
|
||||
scmi_pd->genpd.flags = GENPD_FLAG_PM_CLK |
|
||||
GENPD_FLAG_ACTIVE_WAKEUP;
|
||||
|
||||
pm_genpd_init(&scmi_pd->genpd, NULL,
|
||||
state == SCMI_POWER_STATE_GENERIC_OFF);
|
||||
@ -138,9 +112,28 @@ static int scmi_pm_domain_probe(struct scmi_device *sdev)
|
||||
scmi_pd_data->domains = domains;
|
||||
scmi_pd_data->num_domains = num_domains;
|
||||
|
||||
dev_set_drvdata(dev, scmi_pd_data);
|
||||
|
||||
return of_genpd_add_provider_onecell(np, scmi_pd_data);
|
||||
}
|
||||
|
||||
static void scmi_pm_domain_remove(struct scmi_device *sdev)
|
||||
{
|
||||
int i;
|
||||
struct genpd_onecell_data *scmi_pd_data;
|
||||
struct device *dev = &sdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
|
||||
of_genpd_del_provider(np);
|
||||
|
||||
scmi_pd_data = dev_get_drvdata(dev);
|
||||
for (i = 0; i < scmi_pd_data->num_domains; i++) {
|
||||
if (!scmi_pd_data->domains[i])
|
||||
continue;
|
||||
pm_genpd_remove(scmi_pd_data->domains[i]);
|
||||
}
|
||||
}
|
||||
|
||||
static const struct scmi_device_id scmi_id_table[] = {
|
||||
{ SCMI_PROTOCOL_POWER, "genpd" },
|
||||
{ },
|
||||
@ -150,6 +143,7 @@ MODULE_DEVICE_TABLE(scmi, scmi_id_table);
|
||||
static struct scmi_driver scmi_power_domain_driver = {
|
||||
.name = "scmi-power-domain",
|
||||
.probe = scmi_pm_domain_probe,
|
||||
.remove = scmi_pm_domain_remove,
|
||||
.id_table = scmi_id_table,
|
||||
};
|
||||
module_scmi_driver(scmi_power_domain_driver);
|
||||
|
||||
@ -762,6 +762,10 @@ static int scmi_sensor_config_get(const struct scmi_protocol_handle *ph,
|
||||
{
|
||||
int ret;
|
||||
struct scmi_xfer *t;
|
||||
struct sensors_info *si = ph->get_priv(ph);
|
||||
|
||||
if (sensor_id >= si->num_sensors)
|
||||
return -EINVAL;
|
||||
|
||||
ret = ph->xops->xfer_get_init(ph, SENSOR_CONFIG_GET,
|
||||
sizeof(__le32), sizeof(__le32), &t);
|
||||
@ -771,7 +775,6 @@ static int scmi_sensor_config_get(const struct scmi_protocol_handle *ph,
|
||||
put_unaligned_le32(sensor_id, t->tx.buf);
|
||||
ret = ph->xops->do_xfer(ph, t);
|
||||
if (!ret) {
|
||||
struct sensors_info *si = ph->get_priv(ph);
|
||||
struct scmi_sensor_info *s = si->sensors + sensor_id;
|
||||
|
||||
*sensor_config = get_unaligned_le64(t->rx.buf);
|
||||
@ -788,6 +791,10 @@ static int scmi_sensor_config_set(const struct scmi_protocol_handle *ph,
|
||||
int ret;
|
||||
struct scmi_xfer *t;
|
||||
struct scmi_msg_sensor_config_set *msg;
|
||||
struct sensors_info *si = ph->get_priv(ph);
|
||||
|
||||
if (sensor_id >= si->num_sensors)
|
||||
return -EINVAL;
|
||||
|
||||
ret = ph->xops->xfer_get_init(ph, SENSOR_CONFIG_SET,
|
||||
sizeof(*msg), 0, &t);
|
||||
@ -800,7 +807,6 @@ static int scmi_sensor_config_set(const struct scmi_protocol_handle *ph,
|
||||
|
||||
ret = ph->xops->do_xfer(ph, t);
|
||||
if (!ret) {
|
||||
struct sensors_info *si = ph->get_priv(ph);
|
||||
struct scmi_sensor_info *s = si->sensors + sensor_id;
|
||||
|
||||
s->sensor_config = sensor_config;
|
||||
@ -831,8 +837,11 @@ static int scmi_sensor_reading_get(const struct scmi_protocol_handle *ph,
|
||||
int ret;
|
||||
struct scmi_xfer *t;
|
||||
struct scmi_msg_sensor_reading_get *sensor;
|
||||
struct scmi_sensor_info *s;
|
||||
struct sensors_info *si = ph->get_priv(ph);
|
||||
struct scmi_sensor_info *s = si->sensors + sensor_id;
|
||||
|
||||
if (sensor_id >= si->num_sensors)
|
||||
return -EINVAL;
|
||||
|
||||
ret = ph->xops->xfer_get_init(ph, SENSOR_READING_GET,
|
||||
sizeof(*sensor), 0, &t);
|
||||
@ -841,6 +850,7 @@ static int scmi_sensor_reading_get(const struct scmi_protocol_handle *ph,
|
||||
|
||||
sensor = t->tx.buf;
|
||||
sensor->id = cpu_to_le32(sensor_id);
|
||||
s = si->sensors + sensor_id;
|
||||
if (s->async) {
|
||||
sensor->flags = cpu_to_le32(SENSOR_READ_ASYNC);
|
||||
ret = ph->xops->do_xfer_with_response(ph, t);
|
||||
@ -895,9 +905,13 @@ scmi_sensor_reading_get_timestamped(const struct scmi_protocol_handle *ph,
|
||||
int ret;
|
||||
struct scmi_xfer *t;
|
||||
struct scmi_msg_sensor_reading_get *sensor;
|
||||
struct scmi_sensor_info *s;
|
||||
struct sensors_info *si = ph->get_priv(ph);
|
||||
struct scmi_sensor_info *s = si->sensors + sensor_id;
|
||||
|
||||
if (sensor_id >= si->num_sensors)
|
||||
return -EINVAL;
|
||||
|
||||
s = si->sensors + sensor_id;
|
||||
if (!count || !readings ||
|
||||
(!s->num_axis && count > 1) || (s->num_axis && count > s->num_axis))
|
||||
return -EINVAL;
|
||||
@ -948,6 +962,9 @@ scmi_sensor_info_get(const struct scmi_protocol_handle *ph, u32 sensor_id)
|
||||
{
|
||||
struct sensors_info *si = ph->get_priv(ph);
|
||||
|
||||
if (sensor_id >= si->num_sensors)
|
||||
return NULL;
|
||||
|
||||
return si->sensors + sensor_id;
|
||||
}
|
||||
|
||||
|
||||
@ -148,10 +148,6 @@ static ssize_t flash_count_show(struct device *dev,
|
||||
stride = regmap_get_reg_stride(sec->m10bmc->regmap);
|
||||
num_bits = FLASH_COUNT_SIZE * 8;
|
||||
|
||||
flash_buf = kmalloc(FLASH_COUNT_SIZE, GFP_KERNEL);
|
||||
if (!flash_buf)
|
||||
return -ENOMEM;
|
||||
|
||||
if (FLASH_COUNT_SIZE % stride) {
|
||||
dev_err(sec->dev,
|
||||
"FLASH_COUNT_SIZE (0x%x) not aligned to stride (0x%x)\n",
|
||||
@ -160,6 +156,10 @@ static ssize_t flash_count_show(struct device *dev,
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
flash_buf = kmalloc(FLASH_COUNT_SIZE, GFP_KERNEL);
|
||||
if (!flash_buf)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = regmap_bulk_read(sec->m10bmc->regmap, STAGING_FLASH_COUNT,
|
||||
flash_buf, FLASH_COUNT_SIZE / stride);
|
||||
if (ret) {
|
||||
|
||||
@ -39,6 +39,7 @@
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <drm/drm_crtc_helper.h>
|
||||
#include <drm/drm_damage_helper.h>
|
||||
#include <drm/drm_drv.h>
|
||||
#include <drm/drm_edid.h>
|
||||
#include <drm/drm_gem_framebuffer_helper.h>
|
||||
#include <drm/drm_fb_helper.h>
|
||||
@ -497,6 +498,11 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
|
||||
static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
|
||||
.destroy = drm_gem_fb_destroy,
|
||||
.create_handle = drm_gem_fb_create_handle,
|
||||
};
|
||||
|
||||
static const struct drm_framebuffer_funcs amdgpu_fb_funcs_atomic = {
|
||||
.destroy = drm_gem_fb_destroy,
|
||||
.create_handle = drm_gem_fb_create_handle,
|
||||
.dirty = drm_atomic_helper_dirtyfb,
|
||||
};
|
||||
|
||||
@ -1102,7 +1108,10 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev,
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
|
||||
if (drm_drv_uses_atomic_modeset(dev))
|
||||
ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs_atomic);
|
||||
else
|
||||
ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);
|
||||
if (ret)
|
||||
goto err;
|
||||
|
||||
|
||||
@ -181,6 +181,9 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
|
||||
for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) {
|
||||
if (adev->ip_versions[SDMA0_HWIP][0] < IP_VERSION(6, 0, 0))
|
||||
adev->mes.sdma_hqd_mask[i] = i ? 0 : 0x3fc;
|
||||
/* zero sdma_hqd_mask for non-existent engine */
|
||||
else if (adev->sdma.num_instances == 1)
|
||||
adev->mes.sdma_hqd_mask[i] = i ? 0 : 0xfc;
|
||||
else
|
||||
adev->mes.sdma_hqd_mask[i] = 0xfc;
|
||||
}
|
||||
|
||||
@ -2484,8 +2484,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
|
||||
/* Intentionally setting invalid PTE flag
|
||||
* combination to force a no-retry-fault
|
||||
*/
|
||||
flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
|
||||
AMDGPU_PTE_TF;
|
||||
flags = AMDGPU_PTE_SNOOPED | AMDGPU_PTE_PRT;
|
||||
value = 0;
|
||||
} else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
|
||||
/* Redirect the access to the dummy page */
|
||||
|
||||
@ -1103,10 +1103,13 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
|
||||
*flags |= AMDGPU_PDE_BFS(0x9);
|
||||
|
||||
} else if (level == AMDGPU_VM_PDB0) {
|
||||
if (*flags & AMDGPU_PDE_PTE)
|
||||
if (*flags & AMDGPU_PDE_PTE) {
|
||||
*flags &= ~AMDGPU_PDE_PTE;
|
||||
else
|
||||
if (!(*flags & AMDGPU_PTE_VALID))
|
||||
*addr |= 1 << PAGE_SHIFT;
|
||||
} else {
|
||||
*flags |= AMDGPU_PTE_TF;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -4759,7 +4759,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
|
||||
plane_info->visible = true;
|
||||
plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
|
||||
|
||||
plane_info->layer_index = 0;
|
||||
plane_info->layer_index = plane_state->normalized_zpos;
|
||||
|
||||
ret = fill_plane_color_attributes(plane_state, plane_info->format,
|
||||
&plane_info->color_space);
|
||||
@ -4827,7 +4827,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
|
||||
dc_plane_state->global_alpha = plane_info.global_alpha;
|
||||
dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
|
||||
dc_plane_state->dcc = plane_info.dcc;
|
||||
dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
|
||||
dc_plane_state->layer_index = plane_info.layer_index;
|
||||
dc_plane_state->flip_int_enabled = true;
|
||||
|
||||
/*
|
||||
@ -9485,6 +9485,14 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* DC consults the zpos (layer_index in DC terminology) to determine the
|
||||
* hw plane on which to enable the hw cursor (see
|
||||
* `dcn10_can_pipe_disable_cursor`). By now, all modified planes are in
|
||||
* atomic state, so call drm helper to normalize zpos.
|
||||
*/
|
||||
drm_atomic_normalize_zpos(dev, state);
|
||||
|
||||
/* Remove exiting planes if they are modified */
|
||||
for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
|
||||
ret = dm_update_plane_state(dc, state, plane,
|
||||
|
||||
@ -99,7 +99,7 @@ static int dcn31_get_active_display_cnt_wa(
|
||||
return display_count;
|
||||
}
|
||||
|
||||
static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
|
||||
static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
|
||||
{
|
||||
struct dc *dc = clk_mgr_base->ctx->dc;
|
||||
int i;
|
||||
@ -110,9 +110,10 @@ static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
|
||||
if (pipe->top_pipe || pipe->prev_odm_pipe)
|
||||
continue;
|
||||
if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
|
||||
if (disable)
|
||||
if (disable) {
|
||||
pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
|
||||
else
|
||||
reset_sync_context_for_pipe(dc, context, i);
|
||||
} else
|
||||
pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
|
||||
}
|
||||
}
|
||||
@ -211,11 +212,11 @@ void dcn31_update_clocks(struct clk_mgr *clk_mgr_base,
|
||||
}
|
||||
|
||||
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
|
||||
dcn31_disable_otg_wa(clk_mgr_base, true);
|
||||
dcn31_disable_otg_wa(clk_mgr_base, context, true);
|
||||
|
||||
clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
|
||||
dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
|
||||
dcn31_disable_otg_wa(clk_mgr_base, false);
|
||||
dcn31_disable_otg_wa(clk_mgr_base, context, false);
|
||||
|
||||
update_dispclk = true;
|
||||
}
|
||||
|
||||
@ -119,7 +119,7 @@ static int dcn314_get_active_display_cnt_wa(
|
||||
return display_count;
|
||||
}
|
||||
|
||||
static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
|
||||
static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
|
||||
{
|
||||
struct dc *dc = clk_mgr_base->ctx->dc;
|
||||
int i;
|
||||
@ -129,11 +129,11 @@ static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
|
||||
|
||||
if (pipe->top_pipe || pipe->prev_odm_pipe)
|
||||
continue;
|
||||
if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
|
||||
dc_is_virtual_signal(pipe->stream->signal))) {
|
||||
if (disable)
|
||||
if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
|
||||
if (disable) {
|
||||
pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
|
||||
else
|
||||
reset_sync_context_for_pipe(dc, context, i);
|
||||
} else
|
||||
pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
|
||||
}
|
||||
}
|
||||
@ -233,11 +233,11 @@ void dcn314_update_clocks(struct clk_mgr *clk_mgr_base,
|
||||
}
|
||||
|
||||
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
|
||||
dcn314_disable_otg_wa(clk_mgr_base, true);
|
||||
dcn314_disable_otg_wa(clk_mgr_base, context, true);
|
||||
|
||||
clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
|
||||
dcn314_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
|
||||
dcn314_disable_otg_wa(clk_mgr_base, false);
|
||||
dcn314_disable_otg_wa(clk_mgr_base, context, false);
|
||||
|
||||
update_dispclk = true;
|
||||
}
|
||||
|
||||
@ -46,6 +46,9 @@
|
||||
#define TO_CLK_MGR_DCN315(clk_mgr)\
|
||||
container_of(clk_mgr, struct clk_mgr_dcn315, base)
|
||||
|
||||
#define UNSUPPORTED_DCFCLK 10000000
|
||||
#define MIN_DPP_DISP_CLK 100000
|
||||
|
||||
static int dcn315_get_active_display_cnt_wa(
|
||||
struct dc *dc,
|
||||
struct dc_state *context)
|
||||
@ -79,7 +82,7 @@ static int dcn315_get_active_display_cnt_wa(
|
||||
return display_count;
|
||||
}
|
||||
|
||||
static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
|
||||
static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
|
||||
{
|
||||
struct dc *dc = clk_mgr_base->ctx->dc;
|
||||
int i;
|
||||
@ -91,9 +94,10 @@ static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
|
||||
continue;
|
||||
if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
|
||||
dc_is_virtual_signal(pipe->stream->signal))) {
|
||||
if (disable)
|
||||
if (disable) {
|
||||
pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
|
||||
else
|
||||
reset_sync_context_for_pipe(dc, context, i);
|
||||
} else
|
||||
pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
|
||||
}
|
||||
}
|
||||
@ -146,6 +150,9 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
|
||||
}
|
||||
}
|
||||
|
||||
/* Lock pstate by requesting unsupported dcfclk if change is unsupported */
|
||||
if (!new_clocks->p_state_change_support)
|
||||
new_clocks->dcfclk_khz = UNSUPPORTED_DCFCLK;
|
||||
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
|
||||
clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
|
||||
dcn315_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
|
||||
@ -159,10 +166,10 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
|
||||
|
||||
// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
|
||||
if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
|
||||
if (new_clocks->dppclk_khz < 100000)
|
||||
new_clocks->dppclk_khz = 100000;
|
||||
if (new_clocks->dispclk_khz < 100000)
|
||||
new_clocks->dispclk_khz = 100000;
|
||||
if (new_clocks->dppclk_khz < MIN_DPP_DISP_CLK)
|
||||
new_clocks->dppclk_khz = MIN_DPP_DISP_CLK;
|
||||
if (new_clocks->dispclk_khz < MIN_DPP_DISP_CLK)
|
||||
new_clocks->dispclk_khz = MIN_DPP_DISP_CLK;
|
||||
}
|
||||
|
||||
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
|
||||
@ -175,12 +182,12 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
|
||||
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
|
||||
/* No need to apply the w/a if we haven't taken over from bios yet */
|
||||
if (clk_mgr_base->clks.dispclk_khz)
|
||||
dcn315_disable_otg_wa(clk_mgr_base, true);
|
||||
dcn315_disable_otg_wa(clk_mgr_base, context, true);
|
||||
|
||||
clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
|
||||
dcn315_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
|
||||
if (clk_mgr_base->clks.dispclk_khz)
|
||||
dcn315_disable_otg_wa(clk_mgr_base, false);
|
||||
dcn315_disable_otg_wa(clk_mgr_base, context, false);
|
||||
|
||||
update_dispclk = true;
|
||||
}
|
||||
@ -275,7 +282,7 @@ static struct wm_table ddr5_wm_table = {
|
||||
{
|
||||
.wm_inst = WM_A,
|
||||
.wm_type = WM_TYPE_PSTATE_CHG,
|
||||
.pstate_latency_us = 64.0,
|
||||
.pstate_latency_us = 129.0,
|
||||
.sr_exit_time_us = 11.5,
|
||||
.sr_enter_plus_exit_time_us = 14.5,
|
||||
.valid = true,
|
||||
@ -283,7 +290,7 @@ static struct wm_table ddr5_wm_table = {
|
||||
{
|
||||
.wm_inst = WM_B,
|
||||
.wm_type = WM_TYPE_PSTATE_CHG,
|
||||
.pstate_latency_us = 64.0,
|
||||
.pstate_latency_us = 129.0,
|
||||
.sr_exit_time_us = 11.5,
|
||||
.sr_enter_plus_exit_time_us = 14.5,
|
||||
.valid = true,
|
||||
@ -291,7 +298,7 @@ static struct wm_table ddr5_wm_table = {
|
||||
{
|
||||
.wm_inst = WM_C,
|
||||
.wm_type = WM_TYPE_PSTATE_CHG,
|
||||
.pstate_latency_us = 64.0,
|
||||
.pstate_latency_us = 129.0,
|
||||
.sr_exit_time_us = 11.5,
|
||||
.sr_enter_plus_exit_time_us = 14.5,
|
||||
.valid = true,
|
||||
@ -299,7 +306,7 @@ static struct wm_table ddr5_wm_table = {
|
||||
{
|
||||
.wm_inst = WM_D,
|
||||
.wm_type = WM_TYPE_PSTATE_CHG,
|
||||
.pstate_latency_us = 64.0,
|
||||
.pstate_latency_us = 129.0,
|
||||
.sr_exit_time_us = 11.5,
|
||||
.sr_enter_plus_exit_time_us = 14.5,
|
||||
.valid = true,
|
||||
@ -556,8 +563,7 @@ static void dcn315_clk_mgr_helper_populate_bw_params(
|
||||
ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
|
||||
bw_params->vram_type = bios_info->memory_type;
|
||||
bw_params->num_channels = bios_info->ma_channel_number;
|
||||
if (!bw_params->num_channels)
|
||||
bw_params->num_channels = 2;
|
||||
bw_params->dram_channel_width_bytes = bios_info->memory_type == 0x22 ? 8 : 4;
|
||||
|
||||
for (i = 0; i < WM_SET_COUNT; i++) {
|
||||
bw_params->wm_table.entries[i].wm_inst = i;
|
||||
|
||||
@ -112,7 +112,7 @@ static int dcn316_get_active_display_cnt_wa(
|
||||
return display_count;
|
||||
}
|
||||
|
||||
static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
|
||||
static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
|
||||
{
|
||||
struct dc *dc = clk_mgr_base->ctx->dc;
|
||||
int i;
|
||||
@ -124,9 +124,10 @@ static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
|
||||
continue;
|
||||
if (pipe->stream && (pipe->stream->dpms_off || pipe->plane_state == NULL ||
|
||||
dc_is_virtual_signal(pipe->stream->signal))) {
|
||||
if (disable)
|
||||
if (disable) {
|
||||
pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
|
||||
else
|
||||
reset_sync_context_for_pipe(dc, context, i);
|
||||
} else
|
||||
pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
|
||||
}
|
||||
}
|
||||
@ -221,11 +222,11 @@ static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,
|
||||
}
|
||||
|
||||
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
|
||||
dcn316_disable_otg_wa(clk_mgr_base, true);
|
||||
dcn316_disable_otg_wa(clk_mgr_base, context, true);
|
||||
|
||||
clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
|
||||
dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
|
||||
dcn316_disable_otg_wa(clk_mgr_base, false);
|
||||
dcn316_disable_otg_wa(clk_mgr_base, context, false);
|
||||
|
||||
update_dispclk = true;
|
||||
}
|
||||
|
||||
@ -2758,8 +2758,14 @@ bool perform_link_training_with_retries(
|
||||
skip_video_pattern);
|
||||
|
||||
/* Transmit idle pattern once training successful. */
|
||||
if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low)
|
||||
if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low) {
|
||||
dp_set_hw_test_pattern(link, &pipe_ctx->link_res, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
|
||||
/* Update verified link settings to current one
|
||||
* Because DPIA LT might fallback to lower link setting.
|
||||
*/
|
||||
link->verified_link_cap.link_rate = link->cur_link_settings.link_rate;
|
||||
link->verified_link_cap.lane_count = link->cur_link_settings.lane_count;
|
||||
}
|
||||
} else {
|
||||
status = dc_link_dp_perform_link_training(link,
|
||||
&pipe_ctx->link_res,
|
||||
@ -5121,6 +5127,14 @@ bool dp_retrieve_lttpr_cap(struct dc_link *link)
|
||||
lttpr_dpcd_data[DP_PHY_REPEATER_128B132B_RATES -
|
||||
DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
|
||||
|
||||
/* If this chip cap is set, at least one retimer must exist in the chain
|
||||
* Override count to 1 if we receive a known bad count (0 or an invalid value) */
|
||||
if (link->chip_caps & EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN &&
|
||||
(dp_convert_to_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) == 0)) {
|
||||
ASSERT(0);
|
||||
link->dpcd_caps.lttpr_caps.phy_repeater_cnt = 0x80;
|
||||
}
|
||||
|
||||
/* Attempt to train in LTTPR transparent mode if repeater count exceeds 8. */
|
||||
is_lttpr_present = (link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
|
||||
link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
|
||||
|
||||
@ -3584,6 +3584,23 @@ void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,
|
||||
}
|
||||
}
|
||||
|
||||
void reset_sync_context_for_pipe(const struct dc *dc,
|
||||
struct dc_state *context,
|
||||
uint8_t pipe_idx)
|
||||
{
|
||||
int i;
|
||||
struct pipe_ctx *pipe_ctx_reset;
|
||||
|
||||
/* reset the otg sync context for the pipe and its slave pipes if any */
|
||||
for (i = 0; i < dc->res_pool->pipe_count; i++) {
|
||||
pipe_ctx_reset = &context->res_ctx.pipe_ctx[i];
|
||||
|
||||
if (((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_reset) == pipe_idx) &&
|
||||
IS_PIPE_SYNCD_VALID(pipe_ctx_reset)) || (i == pipe_idx))
|
||||
SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_reset, i);
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter)
|
||||
{
|
||||
/* TODO - get transmitter to phy idx mapping from DMUB */
|
||||
|
||||
@ -2164,7 +2164,8 @@ static void dce110_setup_audio_dto(
|
||||
continue;
|
||||
if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
|
||||
continue;
|
||||
if (pipe_ctx->stream_res.audio != NULL) {
|
||||
if (pipe_ctx->stream_res.audio != NULL &&
|
||||
pipe_ctx->stream_res.audio->enabled == false) {
|
||||
struct audio_output audio_output;
|
||||
|
||||
build_audio_output(context, pipe_ctx, &audio_output);
|
||||
@ -2204,7 +2205,8 @@ static void dce110_setup_audio_dto(
|
||||
if (!dc_is_dp_signal(pipe_ctx->stream->signal))
|
||||
continue;
|
||||
|
||||
if (pipe_ctx->stream_res.audio != NULL) {
|
||||
if (pipe_ctx->stream_res.audio != NULL &&
|
||||
pipe_ctx->stream_res.audio->enabled == false) {
|
||||
struct audio_output audio_output;
|
||||
|
||||
build_audio_output(context, pipe_ctx, &audio_output);
|
||||
|
||||
@ -445,226 +445,6 @@
|
||||
type DSCRM_DSC_FORWARD_EN; \
|
||||
type DSCRM_DSC_OPP_PIPE_SOURCE
|
||||
|
||||
#define DSC_REG_LIST_DCN314(id) \
|
||||
SRI(DSC_TOP_CONTROL, DSC_TOP, id),\
|
||||
SRI(DSC_DEBUG_CONTROL, DSC_TOP, id),\
|
||||
SRI(DSCC_CONFIG0, DSCC, id),\
|
||||
SRI(DSCC_CONFIG1, DSCC, id),\
|
||||
SRI(DSCC_STATUS, DSCC, id),\
|
||||
SRI(DSCC_INTERRUPT_CONTROL_STATUS, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG0, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG1, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG2, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG3, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG4, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG5, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG6, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG7, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG8, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG9, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG10, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG11, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG12, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG13, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG14, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG15, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG16, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG17, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG18, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG19, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG20, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG21, DSCC, id),\
|
||||
SRI(DSCC_PPS_CONFIG22, DSCC, id),\
|
||||
SRI(DSCC_MEM_POWER_CONTROL, DSCC, id),\
|
||||
SRI(DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC, id),\
|
||||
SRI(DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC, id),\
|
||||
SRI(DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC, id),\
|
||||
SRI(DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC, id),\
|
||||
SRI(DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC, id),\
|
||||
SRI(DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC, id),\
|
||||
SRI(DSCC_MAX_ABS_ERROR0, DSCC, id),\
|
||||
SRI(DSCC_MAX_ABS_ERROR1, DSCC, id),\
|
||||
SRI(DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id),\
|
||||
SRI(DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\
|
||||
SRI(DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\
|
||||
SRI(DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\
|
||||
SRI(DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC, id),\
|
||||
SRI(DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC, id),\
|
||||
SRI(DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC, id),\
|
||||
SRI(DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC, id),\
|
||||
SRI(DSCCIF_CONFIG0, DSCCIF, id),\
|
||||
SRI(DSCCIF_CONFIG1, DSCCIF, id),\
|
||||
SRI(DSCRM_DSC_FORWARD_CONFIG, DSCRM, id)
|
||||
|
||||
#define DSC_REG_LIST_SH_MASK_DCN314(mask_sh)\
|
||||
DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_CLOCK_EN, mask_sh), \
|
||||
DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DISPCLK_R_GATE_DIS, mask_sh), \
|
||||
DSC_SF(DSC_TOP0_DSC_TOP_CONTROL, DSC_DSCCLK_R_GATE_DIS, mask_sh), \
|
||||
DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_DBG_EN, mask_sh), \
|
||||
DSC_SF(DSC_TOP0_DSC_DEBUG_CONTROL, DSC_TEST_CLOCK_MUX_SEL, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_PER_LINE, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_CONFIG0, ALTERNATE_ICH_ENCODING_EN, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_CONFIG0, NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, mask_sh), \
|
||||
/*DSC_SF(DSCC0_DSCC_CONFIG1, DSCC_DISABLE_ICH, mask_sh),*/ \
|
||||
DSC_SF(DSCC0_DSCC_STATUS, DSCC_DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER0_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER1_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER2_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_BUFFER3_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_INTERRUPT_CONTROL_STATUS, DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MINOR, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG0, DSC_VERSION_MAJOR, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG0, PPS_IDENTIFIER, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG0, LINEBUF_DEPTH, mask_sh), \
|
||||
DSC2_SF(DSCC0, DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BITS_PER_PIXEL, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, VBR_ENABLE, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, SIMPLE_422, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CONVERT_RGB, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, BLOCK_PRED_ENABLE, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_422, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, NATIVE_420, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG1, CHUNK_SIZE, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_WIDTH, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG2, PIC_HEIGHT, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_WIDTH, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG3, SLICE_HEIGHT, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_XMIT_DELAY, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG4, INITIAL_DEC_DELAY, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG5, INITIAL_SCALE_VALUE, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG5, SCALE_INCREMENT_INTERVAL, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SCALE_DECREMENT_INTERVAL, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG6, FIRST_LINE_BPG_OFFSET, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG6, SECOND_LINE_BPG_OFFSET, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG7, NFL_BPG_OFFSET, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG8, NSL_BPG_OFFSET, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG8, SECOND_LINE_OFFSET_ADJ, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG9, INITIAL_OFFSET, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG9, FINAL_OFFSET, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MIN_QP, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG10, FLATNESS_MAX_QP, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG10, RC_MODEL_SIZE, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_EDGE_FACTOR, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT0, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_QUANT_INCR_LIMIT1, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_LO, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG11, RC_TGT_OFFSET_HI, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH0, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH1, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH2, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG12, RC_BUF_THRESH3, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH4, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH5, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH6, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG13, RC_BUF_THRESH7, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH8, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH9, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH10, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG14, RC_BUF_THRESH11, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH12, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RC_BUF_THRESH13, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MIN_QP0, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_MAX_QP0, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG15, RANGE_BPG_OFFSET0, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP1, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP1, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET1, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MIN_QP2, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_MAX_QP2, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG16, RANGE_BPG_OFFSET2, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP3, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP3, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET3, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MIN_QP4, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_MAX_QP4, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG17, RANGE_BPG_OFFSET4, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP5, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP5, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET5, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MIN_QP6, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_MAX_QP6, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG18, RANGE_BPG_OFFSET6, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP7, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP7, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET7, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MIN_QP8, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_MAX_QP8, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG19, RANGE_BPG_OFFSET8, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP9, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP9, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET9, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MIN_QP10, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_MAX_QP10, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG20, RANGE_BPG_OFFSET10, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP11, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP11, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET11, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MIN_QP12, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_MAX_QP12, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG21, RANGE_BPG_OFFSET12, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP13, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP13, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET13, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MIN_QP14, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_MAX_QP14, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_PPS_CONFIG22, RANGE_BPG_OFFSET14, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_DEFAULT_MEM_LOW_POWER_STATE, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_FORCE, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_DIS, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_MEM_PWR_STATE, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_FORCE, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_DIS, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_MEM_POWER_CONTROL, DSCC_NATIVE_422_MEM_PWR_STATE, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_LOWER, DSCC_R_Y_SQUARED_ERROR_LOWER, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_R_Y_SQUARED_ERROR_UPPER, DSCC_R_Y_SQUARED_ERROR_UPPER, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_LOWER, DSCC_G_CB_SQUARED_ERROR_LOWER, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_G_CB_SQUARED_ERROR_UPPER, DSCC_G_CB_SQUARED_ERROR_UPPER, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_LOWER, DSCC_B_CR_SQUARED_ERROR_LOWER, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_B_CR_SQUARED_ERROR_UPPER, DSCC_B_CR_SQUARED_ERROR_UPPER, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_R_Y_MAX_ABS_ERROR, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR0, DSCC_G_CB_MAX_ABS_ERROR, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_MAX_ABS_ERROR1, DSCC_B_CR_MAX_ABS_ERROR, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER0_MAX_FULLNESS_LEVEL, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER0_MAX_FULLNESS_LEVEL, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER1_MAX_FULLNESS_LEVEL, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL, mask_sh), \
|
||||
DSC_SF(DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL, mask_sh), \
|
||||
DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, mask_sh), \
|
||||
DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, mask_sh), \
|
||||
DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, mask_sh), \
|
||||
DSC_SF(DSCCIF0_DSCCIF_CONFIG0, INPUT_PIXEL_FORMAT, mask_sh), \
|
||||
DSC2_SF(DSCCIF0, DSCCIF_CONFIG0__BITS_PER_COMPONENT, mask_sh), \
|
||||
DSC_SF(DSCCIF0_DSCCIF_CONFIG0, DOUBLE_BUFFER_REG_UPDATE_PENDING, mask_sh), \
|
||||
DSC_SF(DSCCIF0_DSCCIF_CONFIG1, PIC_WIDTH, mask_sh), \
|
||||
DSC_SF(DSCCIF0_DSCCIF_CONFIG1, PIC_HEIGHT, mask_sh), \
|
||||
DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, mask_sh), \
|
||||
DSC_SF(DSCRM0_DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_OPP_PIPE_SOURCE, mask_sh)
|
||||
|
||||
|
||||
struct dcn20_dsc_registers {
|
||||
uint32_t DSC_TOP_CONTROL;
|
||||
uint32_t DSC_DEBUG_CONTROL;
|
||||
|
||||
@ -1565,6 +1565,7 @@ static void dcn20_update_dchubp_dpp(
|
||||
/* Any updates are handled in dc interface, just need
|
||||
* to apply existing for plane enable / opp change */
|
||||
if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
|
||||
|| pipe_ctx->update_flags.bits.plane_changed
|
||||
|| pipe_ctx->stream->update_flags.bits.gamut_remap
|
||||
|| pipe_ctx->stream->update_flags.bits.out_csc) {
|
||||
/* dpp/cm gamut remap*/
|
||||
|
||||
@ -343,7 +343,6 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig
|
||||
{
|
||||
struct dc_stream_state *stream = pipe_ctx->stream;
|
||||
unsigned int odm_combine_factor = 0;
|
||||
struct dc *dc = pipe_ctx->stream->ctx->dc;
|
||||
bool two_pix_per_container = false;
|
||||
|
||||
two_pix_per_container = optc2_is_two_pixels_per_containter(&stream->timing);
|
||||
@ -364,7 +363,7 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig
|
||||
} else {
|
||||
*k1_div = PIXEL_RATE_DIV_BY_1;
|
||||
*k2_div = PIXEL_RATE_DIV_BY_4;
|
||||
if ((odm_combine_factor == 2) || dc->debug.enable_dp_dig_pixel_rate_div_policy)
|
||||
if (odm_combine_factor == 2)
|
||||
*k2_div = PIXEL_RATE_DIV_BY_2;
|
||||
}
|
||||
}
|
||||
@ -384,21 +383,10 @@ void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx)
|
||||
return;
|
||||
|
||||
odm_combine_factor = get_odm_config(pipe_ctx, NULL);
|
||||
if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1
|
||||
|| dcn314_is_dp_dig_pixel_rate_div_policy(pipe_ctx))
|
||||
if (optc2_is_two_pixels_per_containter(&pipe_ctx->stream->timing) || odm_combine_factor > 1)
|
||||
pix_per_cycle = 2;
|
||||
|
||||
if (pipe_ctx->stream_res.stream_enc->funcs->set_input_mode)
|
||||
pipe_ctx->stream_res.stream_enc->funcs->set_input_mode(pipe_ctx->stream_res.stream_enc,
|
||||
pix_per_cycle);
|
||||
}
|
||||
|
||||
bool dcn314_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx)
|
||||
{
|
||||
struct dc *dc = pipe_ctx->stream->ctx->dc;
|
||||
|
||||
if (dc_is_dp_signal(pipe_ctx->stream->signal) && !is_dp_128b_132b_signal(pipe_ctx) &&
|
||||
dc->debug.enable_dp_dig_pixel_rate_div_policy)
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
@ -41,6 +41,4 @@ unsigned int dcn314_calculate_dccg_k1_k2_values(struct pipe_ctx *pipe_ctx, unsig
|
||||
|
||||
void dcn314_set_pixels_per_cycle(struct pipe_ctx *pipe_ctx);
|
||||
|
||||
bool dcn314_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);
|
||||
|
||||
#endif /* __DC_HWSS_DCN314_H__ */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue
Block a user