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drm/ssd130x: Add support for the SSD133x OLED controller family
The Solomon SSD133x controllers (such as the SSD1331) are used by RGB dot matrix OLED panels, add a modesetting pipeline to support the chip family. The SSD133x controllers support 256 (8-bit) and 65k (16-bit) color depths but only the 256-color mode (DRM_FORMAT_RGB332) is implemented for now. Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231229112026.2797483-5-javierm@redhat.com
This commit is contained in:
Javier Martinez Canillas
parent
e06b7373cf
commit
b4299c936d
@ -142,6 +142,11 @@ static const struct of_device_id ssd130x_of_match[] = {
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.compatible = "solomon,ssd1327",
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.data = &ssd130x_variants[SSD1327_ID],
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},
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/* ssd133x family */
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{
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.compatible = "solomon,ssd1331",
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.data = &ssd130x_variants[SSD1331_ID],
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},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, ssd130x_of_match);
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@ -166,6 +171,8 @@ static const struct spi_device_id ssd130x_spi_table[] = {
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{ "ssd1322", SSD1322_ID },
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{ "ssd1325", SSD1325_ID },
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{ "ssd1327", SSD1327_ID },
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/* ssd133x family */
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{ "ssd1331", SSD1331_ID },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(spi, ssd130x_spi_table);
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@ -119,6 +119,26 @@
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#define SSD130X_SET_VCOMH_VOLTAGE 0xbe
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#define SSD132X_SET_FUNCTION_SELECT_B 0xd5
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/* ssd133x commands */
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#define SSD133X_SET_COL_RANGE 0x15
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#define SSD133X_SET_ROW_RANGE 0x75
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#define SSD133X_CONTRAST_A 0x81
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#define SSD133X_CONTRAST_B 0x82
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#define SSD133X_CONTRAST_C 0x83
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#define SSD133X_SET_MASTER_CURRENT 0x87
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#define SSD132X_SET_PRECHARGE_A 0x8a
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#define SSD132X_SET_PRECHARGE_B 0x8b
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#define SSD132X_SET_PRECHARGE_C 0x8c
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#define SSD133X_SET_DISPLAY_START 0xa1
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#define SSD133X_SET_DISPLAY_OFFSET 0xa2
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#define SSD133X_SET_DISPLAY_NORMAL 0xa4
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#define SSD133X_SET_MASTER_CONFIG 0xad
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#define SSD133X_POWER_SAVE_MODE 0xb0
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#define SSD133X_PHASES_PERIOD 0xb1
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#define SSD133X_SET_CLOCK_FREQ 0xb3
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#define SSD133X_SET_PRECHARGE_VOLTAGE 0xbb
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#define SSD133X_SET_VCOMH_VOLTAGE 0xbe
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#define MAX_CONTRAST 255
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const struct ssd130x_deviceinfo ssd130x_variants[] = {
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@ -180,6 +200,12 @@ const struct ssd130x_deviceinfo ssd130x_variants[] = {
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.default_width = 128,
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.default_height = 128,
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.family_id = SSD132X_FAMILY,
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},
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/* ssd133x family */
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[SSD1331_ID] = {
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.default_width = 96,
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.default_height = 64,
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.family_id = SSD133X_FAMILY,
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}
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};
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EXPORT_SYMBOL_NS_GPL(ssd130x_variants, DRM_SSD130X);
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@ -589,6 +615,117 @@ static int ssd132x_init(struct ssd130x_device *ssd130x)
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return 0;
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}
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static int ssd133x_init(struct ssd130x_device *ssd130x)
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{
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int ret;
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/* Set color A contrast */
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ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_CONTRAST_A, 0x91);
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if (ret < 0)
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return ret;
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/* Set color B contrast */
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ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_CONTRAST_B, 0x50);
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if (ret < 0)
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return ret;
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/* Set color C contrast */
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ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_CONTRAST_C, 0x7d);
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if (ret < 0)
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return ret;
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/* Set master current */
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ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_MASTER_CURRENT, 0x06);
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if (ret < 0)
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return ret;
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/* Set column start and end */
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ret = ssd130x_write_cmd(ssd130x, 3, SSD133X_SET_COL_RANGE, 0x00, ssd130x->width - 1);
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if (ret < 0)
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return ret;
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/* Set row start and end */
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ret = ssd130x_write_cmd(ssd130x, 3, SSD133X_SET_ROW_RANGE, 0x00, ssd130x->height - 1);
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if (ret < 0)
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return ret;
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/*
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* Horizontal Address Increment
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* Normal order SA,SB,SC (e.g. RGB)
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* COM Split Odd Even
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* 256 color format
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*/
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ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_SET_SEG_REMAP, 0x20);
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if (ret < 0)
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return ret;
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/* Set display start and offset */
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ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_DISPLAY_START, 0x00);
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if (ret < 0)
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return ret;
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ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_DISPLAY_OFFSET, 0x00);
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if (ret < 0)
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return ret;
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/* Set display mode normal */
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ret = ssd130x_write_cmd(ssd130x, 1, SSD133X_SET_DISPLAY_NORMAL);
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if (ret < 0)
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return ret;
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/* Set multiplex ratio value */
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ret = ssd130x_write_cmd(ssd130x, 2, SSD13XX_SET_MULTIPLEX_RATIO, ssd130x->height - 1);
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if (ret < 0)
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return ret;
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/* Set master configuration */
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ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_MASTER_CONFIG, 0x8e);
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if (ret < 0)
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return ret;
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/* Set power mode */
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ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_POWER_SAVE_MODE, 0x0b);
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if (ret < 0)
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return ret;
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/* Set Phase 1 and 2 period */
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ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_PHASES_PERIOD, 0x31);
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if (ret < 0)
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return ret;
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/* Set clock divider */
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ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_CLOCK_FREQ, 0xf0);
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if (ret < 0)
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return ret;
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/* Set pre-charge A */
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ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PRECHARGE_A, 0x64);
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if (ret < 0)
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return ret;
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/* Set pre-charge B */
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ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PRECHARGE_B, 0x78);
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if (ret < 0)
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return ret;
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/* Set pre-charge C */
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ret = ssd130x_write_cmd(ssd130x, 2, SSD132X_SET_PRECHARGE_C, 0x64);
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if (ret < 0)
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return ret;
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/* Set pre-charge level */
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ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_PRECHARGE_VOLTAGE, 0x3a);
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if (ret < 0)
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return ret;
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/* Set VCOMH voltage */
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ret = ssd130x_write_cmd(ssd130x, 2, SSD133X_SET_VCOMH_VOLTAGE, 0x3e);
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if (ret < 0)
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return ret;
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return 0;
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}
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static int ssd130x_update_rect(struct ssd130x_device *ssd130x,
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struct drm_rect *rect, u8 *buf,
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u8 *data_array)
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@ -753,6 +890,47 @@ static int ssd132x_update_rect(struct ssd130x_device *ssd130x,
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return ret;
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}
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static int ssd133x_update_rect(struct ssd130x_device *ssd130x,
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struct drm_rect *rect, u8 *data_array,
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unsigned int pitch)
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{
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unsigned int x = rect->x1;
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unsigned int y = rect->y1;
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unsigned int columns = drm_rect_width(rect);
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unsigned int rows = drm_rect_height(rect);
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int ret;
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/*
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* The screen is divided in Segment and Common outputs, where
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* COM0 to COM[N - 1] are the rows and SEG0 to SEG[M - 1] are
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* the columns.
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*
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* Each Segment has a 8-bit pixel and each Common output has a
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* row of pixels. When using the (default) horizontal address
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* increment mode, each byte of data sent to the controller has
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* a Segment (e.g: SEG0).
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*
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* When using the 256 color depth format, each pixel contains 3
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* sub-pixels for color A, B and C. These have 3 bit, 3 bit and
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* 2 bits respectively.
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*/
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/* Set column start and end */
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ret = ssd130x_write_cmd(ssd130x, 3, SSD133X_SET_COL_RANGE, x, columns - 1);
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if (ret < 0)
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return ret;
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/* Set row start and end */
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ret = ssd130x_write_cmd(ssd130x, 3, SSD133X_SET_ROW_RANGE, y, rows - 1);
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if (ret < 0)
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return ret;
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/* Write out update in one go since horizontal addressing mode is used */
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ret = ssd130x_write_data(ssd130x, data_array, pitch * rows);
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return ret;
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}
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static void ssd130x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array)
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{
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unsigned int pages = DIV_ROUND_UP(ssd130x->height, SSD130X_PAGE_HEIGHT);
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@ -805,6 +983,22 @@ static void ssd132x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array)
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ssd130x_write_data(ssd130x, data_array, columns * height);
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}
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static void ssd133x_clear_screen(struct ssd130x_device *ssd130x, u8 *data_array)
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{
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const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332);
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unsigned int pitch;
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if (!fi)
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return;
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pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width);
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memset(data_array, 0, pitch * ssd130x->height);
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/* Write out update in one go since horizontal addressing mode is used */
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ssd130x_write_data(ssd130x, data_array, pitch * ssd130x->height);
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}
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static int ssd130x_fb_blit_rect(struct drm_framebuffer *fb,
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const struct iosys_map *vmap,
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struct drm_rect *rect,
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@ -866,6 +1060,36 @@ static int ssd132x_fb_blit_rect(struct drm_framebuffer *fb,
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return ret;
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}
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static int ssd133x_fb_blit_rect(struct drm_framebuffer *fb,
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const struct iosys_map *vmap,
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struct drm_rect *rect, u8 *data_array,
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struct drm_format_conv_state *fmtcnv_state)
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{
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struct ssd130x_device *ssd130x = drm_to_ssd130x(fb->dev);
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const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332);
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unsigned int dst_pitch;
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struct iosys_map dst;
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int ret = 0;
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if (!fi)
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return -EINVAL;
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dst_pitch = drm_format_info_min_pitch(fi, 0, drm_rect_width(rect));
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ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
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if (ret)
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return ret;
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iosys_map_set_vaddr(&dst, data_array);
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drm_fb_xrgb8888_to_rgb332(&dst, &dst_pitch, vmap, fb, rect, fmtcnv_state);
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drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
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ssd133x_update_rect(ssd130x, rect, data_array, dst_pitch);
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return ret;
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}
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static int ssd130x_primary_plane_atomic_check(struct drm_plane *plane,
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struct drm_atomic_state *state)
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{
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@ -964,6 +1188,29 @@ static int ssd132x_primary_plane_atomic_check(struct drm_plane *plane,
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return 0;
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}
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static int ssd133x_primary_plane_atomic_check(struct drm_plane *plane,
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struct drm_atomic_state *state)
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{
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struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
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struct drm_crtc *crtc = plane_state->crtc;
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struct drm_crtc_state *crtc_state = NULL;
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int ret;
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if (crtc)
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crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
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ret = drm_atomic_helper_check_plane_state(plane_state, crtc_state,
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DRM_PLANE_NO_SCALING,
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DRM_PLANE_NO_SCALING,
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false, false);
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if (ret)
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return ret;
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else if (!plane_state->visible)
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return 0;
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return 0;
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}
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static void ssd130x_primary_plane_atomic_update(struct drm_plane *plane,
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struct drm_atomic_state *state)
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{
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@ -1034,6 +1281,39 @@ static void ssd132x_primary_plane_atomic_update(struct drm_plane *plane,
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drm_dev_exit(idx);
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}
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static void ssd133x_primary_plane_atomic_update(struct drm_plane *plane,
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struct drm_atomic_state *state)
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{
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struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
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struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);
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struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
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struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
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struct ssd130x_crtc_state *ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state);
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struct drm_framebuffer *fb = plane_state->fb;
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struct drm_atomic_helper_damage_iter iter;
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struct drm_device *drm = plane->dev;
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struct drm_rect dst_clip;
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struct drm_rect damage;
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int idx;
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if (!drm_dev_enter(drm, &idx))
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return;
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drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);
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drm_atomic_for_each_plane_damage(&iter, &damage) {
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dst_clip = plane_state->dst;
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if (!drm_rect_intersect(&dst_clip, &damage))
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continue;
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ssd133x_fb_blit_rect(fb, &shadow_plane_state->data[0], &dst_clip,
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ssd130x_crtc_state->data_array,
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&shadow_plane_state->fmtcnv_state);
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}
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drm_dev_exit(idx);
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}
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static void ssd130x_primary_plane_atomic_disable(struct drm_plane *plane,
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struct drm_atomic_state *state)
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{
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@ -1082,6 +1362,30 @@ static void ssd132x_primary_plane_atomic_disable(struct drm_plane *plane,
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drm_dev_exit(idx);
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}
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static void ssd133x_primary_plane_atomic_disable(struct drm_plane *plane,
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struct drm_atomic_state *state)
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{
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struct drm_device *drm = plane->dev;
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struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
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struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
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struct drm_crtc_state *crtc_state;
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struct ssd130x_crtc_state *ssd130x_crtc_state;
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int idx;
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if (!plane_state->crtc)
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return;
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crtc_state = drm_atomic_get_new_crtc_state(state, plane_state->crtc);
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ssd130x_crtc_state = to_ssd130x_crtc_state(crtc_state);
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if (!drm_dev_enter(drm, &idx))
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return;
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ssd133x_clear_screen(ssd130x, ssd130x_crtc_state->data_array);
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drm_dev_exit(idx);
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}
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/* Called during init to allocate the plane's atomic state. */
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static void ssd130x_primary_plane_reset(struct drm_plane *plane)
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{
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@ -1144,6 +1448,12 @@ static const struct drm_plane_helper_funcs ssd130x_primary_plane_helper_funcs[]
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.atomic_check = ssd132x_primary_plane_atomic_check,
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.atomic_update = ssd132x_primary_plane_atomic_update,
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.atomic_disable = ssd132x_primary_plane_atomic_disable,
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},
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[SSD133X_FAMILY] = {
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DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
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.atomic_check = ssd133x_primary_plane_atomic_check,
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.atomic_update = ssd133x_primary_plane_atomic_update,
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.atomic_disable = ssd133x_primary_plane_atomic_disable,
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}
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};
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@ -1214,6 +1524,33 @@ static int ssd132x_crtc_atomic_check(struct drm_crtc *crtc,
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return 0;
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}
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static int ssd133x_crtc_atomic_check(struct drm_crtc *crtc,
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struct drm_atomic_state *state)
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{
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struct drm_device *drm = crtc->dev;
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struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
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struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
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struct ssd130x_crtc_state *ssd130x_state = to_ssd130x_crtc_state(crtc_state);
|
||||
const struct drm_format_info *fi = drm_format_info(DRM_FORMAT_RGB332);
|
||||
unsigned int pitch;
|
||||
int ret;
|
||||
|
||||
if (!fi)
|
||||
return -EINVAL;
|
||||
|
||||
ret = drm_crtc_helper_atomic_check(crtc, state);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
pitch = drm_format_info_min_pitch(fi, 0, ssd130x->width);
|
||||
|
||||
ssd130x_state->data_array = kmalloc(pitch * ssd130x->height, GFP_KERNEL);
|
||||
if (!ssd130x_state->data_array)
|
||||
return -ENOMEM;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Called during init to allocate the CRTC's atomic state. */
|
||||
static void ssd130x_crtc_reset(struct drm_crtc *crtc)
|
||||
{
|
||||
@ -1275,6 +1612,10 @@ static const struct drm_crtc_helper_funcs ssd130x_crtc_helper_funcs[] = {
|
||||
.mode_valid = ssd130x_crtc_mode_valid,
|
||||
.atomic_check = ssd132x_crtc_atomic_check,
|
||||
},
|
||||
[SSD133X_FAMILY] = {
|
||||
.mode_valid = ssd130x_crtc_mode_valid,
|
||||
.atomic_check = ssd133x_crtc_atomic_check,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct drm_crtc_funcs ssd130x_crtc_funcs = {
|
||||
@ -1337,6 +1678,31 @@ static void ssd132x_encoder_atomic_enable(struct drm_encoder *encoder,
|
||||
ssd130x_power_off(ssd130x);
|
||||
}
|
||||
|
||||
static void ssd133x_encoder_atomic_enable(struct drm_encoder *encoder,
|
||||
struct drm_atomic_state *state)
|
||||
{
|
||||
struct drm_device *drm = encoder->dev;
|
||||
struct ssd130x_device *ssd130x = drm_to_ssd130x(drm);
|
||||
int ret;
|
||||
|
||||
ret = ssd130x_power_on(ssd130x);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
ret = ssd133x_init(ssd130x);
|
||||
if (ret)
|
||||
goto power_off;
|
||||
|
||||
ssd130x_write_cmd(ssd130x, 1, SSD13XX_DISPLAY_ON);
|
||||
|
||||
backlight_enable(ssd130x->bl_dev);
|
||||
|
||||
return;
|
||||
|
||||
power_off:
|
||||
ssd130x_power_off(ssd130x);
|
||||
}
|
||||
|
||||
static void ssd130x_encoder_atomic_disable(struct drm_encoder *encoder,
|
||||
struct drm_atomic_state *state)
|
||||
{
|
||||
@ -1358,6 +1724,10 @@ static const struct drm_encoder_helper_funcs ssd130x_encoder_helper_funcs[] = {
|
||||
[SSD132X_FAMILY] = {
|
||||
.atomic_enable = ssd132x_encoder_atomic_enable,
|
||||
.atomic_disable = ssd130x_encoder_atomic_disable,
|
||||
},
|
||||
[SSD133X_FAMILY] = {
|
||||
.atomic_enable = ssd133x_encoder_atomic_enable,
|
||||
.atomic_disable = ssd130x_encoder_atomic_disable,
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
@ -25,7 +25,8 @@
|
||||
|
||||
enum ssd130x_family_ids {
|
||||
SSD130X_FAMILY,
|
||||
SSD132X_FAMILY
|
||||
SSD132X_FAMILY,
|
||||
SSD133X_FAMILY
|
||||
};
|
||||
|
||||
enum ssd130x_variants {
|
||||
@ -39,6 +40,8 @@ enum ssd130x_variants {
|
||||
SSD1322_ID,
|
||||
SSD1325_ID,
|
||||
SSD1327_ID,
|
||||
/* ssd133x family */
|
||||
SSD1331_ID,
|
||||
NR_SSD130X_VARIANTS
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user