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ARC: mm: compute TLB size as needed from ways * sets
This frees up some bits to hold more high level info such as PAE being present, w/o increasing the size of already bloated cpuinfo struct Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
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@ -327,8 +327,8 @@ struct bcr_generic {
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*/
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struct cpuinfo_arc_mmu {
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unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, u_dtlb:6, u_itlb:6;
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unsigned int num_tlb:16, sets:12, ways:4;
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unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:12;
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unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
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};
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struct cpuinfo_arc_cache {
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@ -240,9 +240,10 @@ static void tlb_entry_insert(unsigned int pd0, unsigned int pd1)
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noinline void local_flush_tlb_all(void)
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{
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struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
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unsigned long flags;
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unsigned int entry;
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struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
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int num_tlb = mmu->sets * mmu->ways;
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local_irq_save(flags);
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@ -250,7 +251,7 @@ noinline void local_flush_tlb_all(void)
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write_aux_reg(ARC_REG_TLBPD1, 0);
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write_aux_reg(ARC_REG_TLBPD0, 0);
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for (entry = 0; entry < mmu->num_tlb; entry++) {
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for (entry = 0; entry < num_tlb; entry++) {
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/* write this entry to the TLB */
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write_aux_reg(ARC_REG_TLBINDEX, entry);
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write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
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@ -767,8 +768,6 @@ void read_decode_mmu_bcr(void)
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mmu->u_dtlb = mmu4->u_dtlb * 4;
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mmu->u_itlb = mmu4->u_itlb * 4;
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}
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mmu->num_tlb = mmu->sets * mmu->ways;
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}
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char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
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@ -785,7 +784,7 @@ char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
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n += scnprintf(buf + n, len - n,
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"MMU [v%x]\t: %dk PAGE, %sJTLB %d (%dx%d), uDTLB %d, uITLB %d %s\n",
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p_mmu->ver, p_mmu->pg_sz_k, super_pg,
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p_mmu->num_tlb, p_mmu->sets, p_mmu->ways,
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p_mmu->sets * p_mmu->ways, p_mmu->sets, p_mmu->ways,
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p_mmu->u_dtlb, p_mmu->u_itlb,
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IS_ENABLED(CONFIG_ARC_MMU_SASID) ? ",SASID" : "");
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