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drm/nouveau/imem: convert to new-style nvkm_subdev

Browse Source 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2015-08-20 14:54:20 +10:00
parent 8de65bd090
commit b7a2bc1886
21 changed files with 293 additions and 399 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h
View File

@ -4,14 +4,11 @@
struct nvkm_memory;
struct nvkm_instmem {
struct nvkm_subdev subdev;
struct list_head list;
u32 reserved;
int (*alloc)(struct nvkm_instmem *, u32 size, u32 align, bool zero,
struct nvkm_memory **);
const struct nvkm_instmem_func *func;
struct nvkm_subdev subdev;
struct list_head list;
u32 reserved;
struct nvkm_memory *vbios;
struct nvkm_ramht *ramht;
@ -19,26 +16,14 @@ struct nvkm_instmem {
struct nvkm_memory *ramfc;
};
struct nvkm_instmem_func {
u32 (*rd32)(struct nvkm_instmem *, u32 addr);
void (*wr32)(struct nvkm_instmem *, u32 addr, u32 data);
};
u32 nvkm_instmem_rd32(struct nvkm_instmem *, u32 addr);
void nvkm_instmem_wr32(struct nvkm_instmem *, u32 addr, u32 data);
int nvkm_instobj_new(struct nvkm_instmem *, u32 size, u32 align, bool zero,
struct nvkm_memory **);
static inline struct nvkm_instmem *
nvkm_instmem(void *obj)
{
/* nv04/nv40 impls need to create objects in their constructor,
* which is before the subdev pointer is valid
*/
if (nv_iclass(obj, NV_SUBDEV_CLASS) &&
nv_subidx(obj) == NVDEV_SUBDEV_INSTMEM)
return obj;
return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_INSTMEM);
}
extern struct nvkm_oclass *nv04_instmem_oclass;
extern struct nvkm_oclass *nv40_instmem_oclass;
extern struct nvkm_oclass *nv50_instmem_oclass;
extern struct nvkm_oclass *gk20a_instmem_oclass;
int nv04_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **);
int nv40_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **);
int nv50_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **);
int gk20a_instmem_new(struct nvkm_device *, int, struct nvkm_instmem **);
#endif

2
drivers/gpu/drm/nouveau/nvkm/core/memory.c
View File

@ -55,7 +55,7 @@ nvkm_memory_new(struct nvkm_device *device, enum nvkm_memory_target target,
if (unlikely(target != NVKM_MEM_TARGET_INST || !imem))
return -ENOSYS;
ret = imem->alloc(imem, size, align, zero, &memory);
ret = nvkm_instobj_new(imem, size, align, zero, &memory);
if (ret)
return ret;

138
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@ -82,7 +82,7 @@ nv4_chipset = {
.devinit = nv04_devinit_new,
.fb = nv04_fb_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -102,7 +102,7 @@ nv5_chipset = {
.devinit = nv05_devinit_new,
.fb = nv04_fb_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -123,7 +123,7 @@ nv10_chipset = {
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -142,7 +142,7 @@ nv11_chipset = {
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -163,7 +163,7 @@ nv15_chipset = {
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -184,7 +184,7 @@ nv17_chipset = {
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -205,7 +205,7 @@ nv18_chipset = {
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -226,7 +226,7 @@ nv1a_chipset = {
.fb = nv1a_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -247,7 +247,7 @@ nv1f_chipset = {
.fb = nv1a_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -268,7 +268,7 @@ nv20_chipset = {
.fb = nv20_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -289,7 +289,7 @@ nv25_chipset = {
.fb = nv25_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -310,7 +310,7 @@ nv28_chipset = {
.fb = nv25_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -331,7 +331,7 @@ nv2a_chipset = {
.fb = nv25_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -352,7 +352,7 @@ nv30_chipset = {
.fb = nv30_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -373,7 +373,7 @@ nv31_chipset = {
.fb = nv30_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -395,7 +395,7 @@ nv34_chipset = {
.fb = nv10_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -417,7 +417,7 @@ nv35_chipset = {
.fb = nv35_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -438,7 +438,7 @@ nv36_chipset = {
.fb = nv36_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv04_instmem_new,
.imem = nv04_instmem_new,
// .mc = nv04_mc_new,
// .mmu = nv04_mmu_new,
// .timer = nv04_timer_new,
@ -460,7 +460,7 @@ nv40_chipset = {
.fb = nv40_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
.imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv04_mmu_new,
// .therm = nv40_therm_new,
@ -485,7 +485,7 @@ nv41_chipset = {
.fb = nv41_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
.imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
@ -510,7 +510,7 @@ nv42_chipset = {
.fb = nv41_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
.imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
@ -535,7 +535,7 @@ nv43_chipset = {
.fb = nv41_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
.imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
@ -560,7 +560,7 @@ nv44_chipset = {
.fb = nv44_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
.imem = nv40_instmem_new,
// .mc = nv44_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
@ -585,7 +585,7 @@ nv45_chipset = {
.fb = nv40_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
.imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv04_mmu_new,
// .therm = nv40_therm_new,
@ -610,7 +610,7 @@ nv46_chipset = {
.fb = nv46_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
.imem = nv40_instmem_new,
// .mc = nv44_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
@ -635,7 +635,7 @@ nv47_chipset = {
.fb = nv47_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
.imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
@ -660,7 +660,7 @@ nv49_chipset = {
.fb = nv49_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
.imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
@ -685,7 +685,7 @@ nv4a_chipset = {
.fb = nv44_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
.imem = nv40_instmem_new,
// .mc = nv44_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
@ -710,7 +710,7 @@ nv4b_chipset = {
.fb = nv49_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
.imem = nv40_instmem_new,
// .mc = nv40_mc_new,
// .mmu = nv41_mmu_new,
// .therm = nv40_therm_new,
@ -735,7 +735,7 @@ nv4c_chipset = {
.fb = nv46_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
.imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
@ -760,7 +760,7 @@ nv4e_chipset = {
.fb = nv4e_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv4e_i2c_new,
// .imem = nv40_instmem_new,
.imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
@ -787,7 +787,7 @@ nv50_chipset = {
.fuse = nv50_fuse_new,
.gpio = nv50_gpio_new,
.i2c = nv50_i2c_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
@ -813,7 +813,7 @@ nv63_chipset = {
.fb = nv46_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
.imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
@ -838,7 +838,7 @@ nv67_chipset = {
.fb = nv46_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
.imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
@ -863,7 +863,7 @@ nv68_chipset = {
.fb = nv46_fb_new,
.gpio = nv10_gpio_new,
.i2c = nv04_i2c_new,
// .imem = nv40_instmem_new,
.imem = nv40_instmem_new,
// .mc = nv4c_mc_new,
// .mmu = nv44_mmu_new,
// .therm = nv40_therm_new,
@ -890,7 +890,7 @@ nv84_chipset = {
.fuse = nv50_fuse_new,
.gpio = nv50_gpio_new,
.i2c = nv50_i2c_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
@ -921,7 +921,7 @@ nv86_chipset = {
.fuse = nv50_fuse_new,
.gpio = nv50_gpio_new,
.i2c = nv50_i2c_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
@ -952,7 +952,7 @@ nv92_chipset = {
.fuse = nv50_fuse_new,
.gpio = nv50_gpio_new,
.i2c = nv50_i2c_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .mc = nv50_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
@ -983,7 +983,7 @@ nv94_chipset = {
.fuse = nv50_fuse_new,
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .mc = g94_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
@ -1017,7 +1017,7 @@ nv96_chipset = {
.bus = g94_bus_new,
// .timer = nv04_timer_new,
.fb = g84_fb_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .mmu = nv50_mmu_new,
.bar = g84_bar_new,
// .volt = nv40_volt_new,
@ -1048,7 +1048,7 @@ nv98_chipset = {
.bus = g94_bus_new,
// .timer = nv04_timer_new,
.fb = g84_fb_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .mmu = nv50_mmu_new,
.bar = g84_bar_new,
// .volt = nv40_volt_new,
@ -1076,7 +1076,7 @@ nva0_chipset = {
.fuse = nv50_fuse_new,
.gpio = g94_gpio_new,
.i2c = nv50_i2c_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
@ -1107,7 +1107,7 @@ nva3_chipset = {
.fuse = nv50_fuse_new,
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
@ -1140,7 +1140,7 @@ nva5_chipset = {
.fuse = nv50_fuse_new,
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
@ -1172,7 +1172,7 @@ nva8_chipset = {
.fuse = nv50_fuse_new,
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
@ -1204,7 +1204,7 @@ nvaa_chipset = {
.fuse = nv50_fuse_new,
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
@ -1235,7 +1235,7 @@ nvac_chipset = {
.fuse = nv50_fuse_new,
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
@ -1266,7 +1266,7 @@ nvaf_chipset = {
.fuse = nv50_fuse_new,
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .mc = g98_mc_new,
// .mmu = nv50_mmu_new,
// .mxm = nv50_mxm_new,
@ -1299,7 +1299,7 @@ nvc0_chipset = {
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
.ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
@ -1334,7 +1334,7 @@ nvc1_chipset = {
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
.ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
@ -1368,7 +1368,7 @@ nvc3_chipset = {
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
.ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
@ -1402,7 +1402,7 @@ nvc4_chipset = {
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
.ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
@ -1437,7 +1437,7 @@ nvc8_chipset = {
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
.ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
@ -1472,7 +1472,7 @@ nvce_chipset = {
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
.ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf100_mc_new,
// .mmu = gf100_mmu_new,
@ -1507,7 +1507,7 @@ nvcf_chipset = {
.gpio = g94_gpio_new,
.i2c = g94_i2c_new,
.ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
@ -1541,7 +1541,7 @@ nvd7_chipset = {
.gpio = gf119_gpio_new,
.i2c = gf117_i2c_new,
.ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
@ -1573,7 +1573,7 @@ nvd9_chipset = {
.gpio = gf119_gpio_new,
.i2c = gf119_i2c_new,
.ibus = gf100_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gf100_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
@ -1607,7 +1607,7 @@ nve4_chipset = {
.gpio = gk104_gpio_new,
.i2c = gk104_i2c_new,
.ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
@ -1643,7 +1643,7 @@ nve6_chipset = {
.gpio = gk104_gpio_new,
.i2c = gk104_i2c_new,
.ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
@ -1679,7 +1679,7 @@ nve7_chipset = {
.gpio = gk104_gpio_new,
.i2c = gk104_i2c_new,
.ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
@ -1711,7 +1711,7 @@ nvea_chipset = {
.fb = gk20a_fb_new,
.fuse = gf100_fuse_new,
.ibus = gk20a_ibus_new,
// .imem = gk20a_instmem_new,
.imem = gk20a_instmem_new,
// .ltc = gk104_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
@ -1739,7 +1739,7 @@ nvf0_chipset = {
.gpio = gk104_gpio_new,
.i2c = gk104_i2c_new,
.ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
@ -1775,7 +1775,7 @@ nvf1_chipset = {
.gpio = gk104_gpio_new,
.i2c = gf119_i2c_new,
.ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
// .mc = gf106_mc_new,
// .mmu = gf100_mmu_new,
@ -1811,7 +1811,7 @@ nv106_chipset = {
.gpio = gk104_gpio_new,
.i2c = gk104_i2c_new,
.ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
@ -1846,7 +1846,7 @@ nv108_chipset = {
.gpio = gk104_gpio_new,
.i2c = gk104_i2c_new,
.ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gk104_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
@ -1881,7 +1881,7 @@ nv117_chipset = {
.gpio = gk104_gpio_new,
.i2c = gf119_i2c_new,
.ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gm107_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
@ -1910,7 +1910,7 @@ nv124_chipset = {
.gpio = gk104_gpio_new,
.i2c = gm204_i2c_new,
.ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gm107_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
@ -1939,7 +1939,7 @@ nv126_chipset = {
.gpio = gk104_gpio_new,
.i2c = gm204_i2c_new,
.ibus = gk104_ibus_new,
// .imem = nv50_instmem_new,
.imem = nv50_instmem_new,
// .ltc = gm107_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,
@ -1964,7 +1964,7 @@ nv12b_chipset = {
.fb = gk20a_fb_new,
.fuse = gm107_fuse_new,
.ibus = gk20a_ibus_new,
// .imem = gk20a_instmem_new,
.imem = gk20a_instmem_new,
// .ltc = gm107_ltc_new,
// .mc = gk20a_mc_new,
// .mmu = gf100_mmu_new,

9
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
View File

@ -33,7 +33,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -55,7 +54,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -77,7 +75,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -98,7 +95,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -120,7 +116,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -141,7 +136,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -162,7 +156,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gf100_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf100_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -184,7 +177,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -205,7 +197,6 @@ gf100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gf100_fifo_oclass;

8
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
View File

@ -33,7 +33,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -56,7 +55,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gf110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -79,7 +77,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -100,7 +97,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass;
@ -117,7 +113,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -140,7 +135,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gf106_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk110_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -163,7 +157,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -185,7 +178,6 @@ gk104_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;

4
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
View File

@ -33,7 +33,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
@ -66,7 +65,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
#if 0
@ -96,7 +94,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MC ] = gk20a_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gk208_pmu_oclass;
#if 0
@ -122,7 +119,6 @@ gm100_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &gk20a_timer_oclass;
device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = gk20a_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = gf110_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = gm20b_fifo_oclass;

2
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
View File

@ -30,7 +30,6 @@ nv04_identify(struct nvkm_device *device)
case 0x04:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
@ -41,7 +40,6 @@ nv04_identify(struct nvkm_device *device)
case 0x05:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;

8
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
View File

@ -30,7 +30,6 @@ nv10_identify(struct nvkm_device *device)
case 0x10:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_gr_oclass;
@ -39,7 +38,6 @@ nv10_identify(struct nvkm_device *device)
case 0x15:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
@ -50,7 +48,6 @@ nv10_identify(struct nvkm_device *device)
case 0x16:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
@ -61,7 +58,6 @@ nv10_identify(struct nvkm_device *device)
case 0x1a:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
@ -72,7 +68,6 @@ nv10_identify(struct nvkm_device *device)
case 0x11:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
@ -83,7 +78,6 @@ nv10_identify(struct nvkm_device *device)
case 0x17:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@ -94,7 +88,6 @@ nv10_identify(struct nvkm_device *device)
case 0x1f:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@ -105,7 +98,6 @@ nv10_identify(struct nvkm_device *device)
case 0x18:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;

4
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
View File

@ -30,7 +30,6 @@ nv20_identify(struct nvkm_device *device)
case 0x20:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@ -41,7 +40,6 @@ nv20_identify(struct nvkm_device *device)
case 0x25:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@ -52,7 +50,6 @@ nv20_identify(struct nvkm_device *device)
case 0x28:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@ -63,7 +60,6 @@ nv20_identify(struct nvkm_device *device)
case 0x2a:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;

5
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
View File

@ -30,7 +30,6 @@ nv30_identify(struct nvkm_device *device)
case 0x30:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@ -41,7 +40,6 @@ nv30_identify(struct nvkm_device *device)
case 0x35:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@ -52,7 +50,6 @@ nv30_identify(struct nvkm_device *device)
case 0x31:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@ -64,7 +61,6 @@ nv30_identify(struct nvkm_device *device)
case 0x36:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
@ -76,7 +72,6 @@ nv30_identify(struct nvkm_device *device)
case 0x34:
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;

16
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
View File

@ -31,7 +31,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -46,7 +45,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -61,7 +59,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -76,7 +73,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -91,7 +87,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv04_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -106,7 +101,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -121,7 +115,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -136,7 +129,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv41_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -151,7 +143,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -166,7 +157,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -181,7 +171,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -196,7 +185,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -211,7 +199,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -226,7 +213,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -241,7 +227,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;
@ -256,7 +241,6 @@ nv40_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv4c_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv44_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv04_dmaeng_oclass;

14
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
View File

@ -32,7 +32,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@ -48,7 +47,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@ -67,7 +65,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@ -86,7 +83,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@ -105,7 +101,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@ -124,7 +119,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g94_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@ -143,7 +137,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@ -162,7 +155,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@ -181,7 +173,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@ -200,7 +191,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = nv50_dmaeng_oclass;
@ -219,7 +209,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -240,7 +229,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -260,7 +248,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
@ -280,7 +267,6 @@ nv50_identify(struct nvkm_device *device)
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = g98_mc_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_MMU ] = &nv50_mmu_oclass;
device->oclass[NVDEV_SUBDEV_PMU ] = gt215_pmu_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;

3
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.c
View File

@ -353,6 +353,7 @@ nv40_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nvkm_device *device = (void *)parent;
struct nv40_gr *gr;
int ret;
@ -365,7 +366,7 @@ nv40_gr_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
nv_subdev(gr)->unit = 0x00001000;
nv_subdev(gr)->intr = nv40_gr_intr;
if (nv44_gr_class(gr))
if (nv44_gr_class(device))
gr->base.func = &nv44_gr;
else
gr->base.func = &nv40_gr;

4
drivers/gpu/drm/nouveau/nvkm/engine/gr/nv40.h
View File

@ -23,10 +23,8 @@ struct nv40_gr_chan {
* helpful to determine a number of other hardware features
*/
static inline int
nv44_gr_class(void *priv)
nv44_gr_class(struct nvkm_device *device)
{
struct nvkm_device *device = nv_device(priv);
if ((device->chipset & 0xf0) == 0x60)
return 1;

6
drivers/gpu/drm/nouveau/nvkm/engine/mpeg/nv40.c
View File

@ -32,9 +32,9 @@ nv40_mpeg_mthd_dma(struct nvkm_device *device, u32 mthd, u32 data)
{
struct nvkm_instmem *imem = device->imem;
u32 inst = data << 4;
u32 dma0 = imem->func->rd32(imem, inst + 0);
u32 dma1 = imem->func->rd32(imem, inst + 4);
u32 dma2 = imem->func->rd32(imem, inst + 8);
u32 dma0 = nvkm_instmem_rd32(imem, inst + 0);
u32 dma1 = nvkm_instmem_rd32(imem, inst + 4);
u32 dma2 = nvkm_instmem_rd32(imem, inst + 8);
u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
u32 size = dma1 + 1;

97
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.c
View File

@ -168,21 +168,20 @@ nvkm_instobj_func_slow = {
.map = nvkm_instobj_map,
};
static int
int
nvkm_instobj_new(struct nvkm_instmem *imem, u32 size, u32 align, bool zero,
struct nvkm_memory **pmemory)
{
struct nvkm_instmem_impl *impl = (void *)imem->subdev.object.oclass;
struct nvkm_memory *memory;
struct nvkm_memory *memory = NULL;
struct nvkm_instobj *iobj;
u32 offset;
int ret;
ret = impl->memory_new(imem, size, align, zero, &memory);
ret = imem->func->memory_new(imem, size, align, zero, &memory);
if (ret)
goto done;
if (!impl->persistent) {
if (!imem->func->persistent) {
if (!(iobj = kzalloc(sizeof(*iobj), GFP_KERNEL))) {
ret = -ENOMEM;
goto done;
@ -195,7 +194,7 @@ nvkm_instobj_new(struct nvkm_instmem *imem, u32 size, u32 align, bool zero,
memory = &iobj->memory;
}
if (!impl->zero && zero) {
if (!imem->func->zero && zero) {
void __iomem *map = nvkm_kmap(memory);
if (unlikely(!map)) {
for (offset = 0; offset < size; offset += 4)
@ -217,13 +216,28 @@ done:
* instmem subdev base implementation
*****************************************************************************/
int
_nvkm_instmem_fini(struct nvkm_object *object, bool suspend)
u32
nvkm_instmem_rd32(struct nvkm_instmem *imem, u32 addr)
{
struct nvkm_instmem *imem = (void *)object;
return imem->func->rd32(imem, addr);
}
void
nvkm_instmem_wr32(struct nvkm_instmem *imem, u32 addr, u32 data)
{
return imem->func->wr32(imem, addr, data);
}
static int
nvkm_instmem_fini(struct nvkm_subdev *subdev, bool suspend)
{
struct nvkm_instmem *imem = nvkm_instmem(subdev);
struct nvkm_instobj *iobj;
int i;
if (imem->func->fini)
imem->func->fini(imem);
if (suspend) {
list_for_each_entry(iobj, &imem->list, head) {
struct nvkm_memory *memory = iobj->parent;
@ -238,19 +252,24 @@ _nvkm_instmem_fini(struct nvkm_object *object, bool suspend)
}
}
return nvkm_subdev_fini_old(&imem->subdev, suspend);
return 0;
}
int
_nvkm_instmem_init(struct nvkm_object *object)
static int
nvkm_instmem_oneinit(struct nvkm_subdev *subdev)
{
struct nvkm_instmem *imem = (void *)object;
struct nvkm_instobj *iobj;
int ret, i;
struct nvkm_instmem *imem = nvkm_instmem(subdev);
if (imem->func->oneinit)
return imem->func->oneinit(imem);
return 0;
}
ret = nvkm_subdev_init_old(&imem->subdev);
if (ret)
return ret;
static int
nvkm_instmem_init(struct nvkm_subdev *subdev)
{
struct nvkm_instmem *imem = nvkm_instmem(subdev);
struct nvkm_instobj *iobj;
int i;
list_for_each_entry(iobj, &imem->list, head) {
if (iobj->suspend) {
@ -266,23 +285,29 @@ _nvkm_instmem_init(struct nvkm_object *object)
return 0;
}
int
nvkm_instmem_create_(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, int length, void **pobject)
static void *
nvkm_instmem_dtor(struct nvkm_subdev *subdev)
{
struct nvkm_device *device = (void *)parent;
struct nvkm_instmem *imem;
int ret;
ret = nvkm_subdev_create_(parent, engine, oclass, 0, "INSTMEM",
"instmem", length, pobject);
imem = *pobject;
if (ret)
return ret;
device->imem = imem;
INIT_LIST_HEAD(&imem->list);
imem->alloc = nvkm_instobj_new;
return 0;
struct nvkm_instmem *imem = nvkm_instmem(subdev);
if (imem->func->dtor)
return imem->func->dtor(imem);
return imem;
}
static const struct nvkm_subdev_func
nvkm_instmem = {
.dtor = nvkm_instmem_dtor,
.oneinit = nvkm_instmem_oneinit,
.init = nvkm_instmem_init,
.fini = nvkm_instmem_fini,
};
void
nvkm_instmem_ctor(const struct nvkm_instmem_func *func,
struct nvkm_device *device, int index,
struct nvkm_instmem *imem)
{
nvkm_subdev_ctor(&nvkm_instmem, device, index, 0, &imem->subdev);
imem->func = func;
INIT_LIST_HEAD(&imem->list);
}

54
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.c
View File

@ -186,7 +186,7 @@ gk20a_instobj_dtor_dma(struct gk20a_instobj *_node)
{
struct gk20a_instobj_dma *node = (void *)_node;
struct gk20a_instmem *imem = _node->imem;
struct device *dev = nv_device_base(nv_device(imem));
struct device *dev = nv_device_base(imem->base.subdev.device);
if (unlikely(!node->cpuaddr))
return;
@ -372,7 +372,7 @@ gk20a_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero,
struct nvkm_memory **pmemory)
{
struct gk20a_instmem *imem = gk20a_instmem(base);
struct gk20a_instobj *node;
struct gk20a_instobj *node = NULL;
struct nvkm_subdev *subdev = &imem->base.subdev;
int ret;
@ -389,9 +389,9 @@ gk20a_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero,
else
ret = gk20a_instobj_ctor_dma(imem, size >> PAGE_SHIFT,
align, &node);
*pmemory = node ? &node->memory : NULL;
if (ret)
return ret;
*pmemory = &node->memory;
nvkm_memory_ctor(&gk20a_instobj_func, &node->memory);
node->imem = imem;
@ -407,29 +407,31 @@ gk20a_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero,
return 0;
}
static int
gk20a_instmem_fini(struct nvkm_object *object, bool suspend)
static void
gk20a_instmem_fini(struct nvkm_instmem *base)
{
struct gk20a_instmem *imem = (void *)object;
imem->addr = ~0ULL;
return nvkm_instmem_fini(&imem->base, suspend);
gk20a_instmem(base)->addr = ~0ULL;
}
static int
gk20a_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
static const struct nvkm_instmem_func
gk20a_instmem = {
.fini = gk20a_instmem_fini,
.memory_new = gk20a_instobj_new,
.persistent = true,
.zero = false,
};
int
gk20a_instmem_new(struct nvkm_device *device, int index,
struct nvkm_instmem **pimem)
{
struct nvkm_device *device = (void *)parent;
struct gk20a_instmem *imem;
int ret;
ret = nvkm_instmem_create(parent, engine, oclass, &imem);
*pobject = nv_object(imem);
if (ret)
return ret;
if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL)))
return -ENOMEM;
nvkm_instmem_ctor(&gk20a_instmem, device, index, &imem->base);
spin_lock_init(&imem->lock);
*pimem = &imem->base;
if (device->gpu->iommu.domain) {
imem->domain = device->gpu->iommu.domain;
@ -454,17 +456,3 @@ gk20a_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
return 0;
}
struct nvkm_oclass *
gk20a_instmem_oclass = &(struct nvkm_instmem_impl) {
.base.handle = NV_SUBDEV(INSTMEM, 0xea),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = gk20a_instmem_ctor,
.dtor = _nvkm_instmem_dtor,
.init = _nvkm_instmem_init,
.fini = gk20a_instmem_fini,
},
.memory_new = gk20a_instobj_new,
.persistent = true,
.zero = false,
}.base;

75
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c
View File

@ -150,40 +150,13 @@ nv04_instmem_wr32(struct nvkm_instmem *imem, u32 addr, u32 data)
nvkm_wr32(imem->subdev.device, 0x700000 + addr, data);
}
static void
nv04_instmem_dtor(struct nvkm_object *object)
{
struct nv04_instmem *imem = (void *)object;
nvkm_memory_del(&imem->base.ramfc);
nvkm_memory_del(&imem->base.ramro);
nvkm_ramht_del(&imem->base.ramht);
nvkm_memory_del(&imem->base.vbios);
nvkm_mm_fini(&imem->heap);
nvkm_instmem_destroy(&imem->base);
}
static const struct nvkm_instmem_func
nv04_instmem_func = {
.rd32 = nv04_instmem_rd32,
.wr32 = nv04_instmem_wr32,
};
static int
nv04_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
nv04_instmem_oneinit(struct nvkm_instmem *base)
{
struct nvkm_device *device = (void *)parent;
struct nv04_instmem *imem;
struct nv04_instmem *imem = nv04_instmem(base);
struct nvkm_device *device = imem->base.subdev.device;
int ret;
ret = nvkm_instmem_create(parent, engine, oclass, &imem);
*pobject = nv_object(imem);
if (ret)
return ret;
imem->base.func = &nv04_instmem_func;
/* PRAMIN aperture maps over the end of VRAM, reserve it */
imem->base.reserved = 512 * 1024;
@ -217,16 +190,38 @@ nv04_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
return 0;
}
struct nvkm_oclass *
nv04_instmem_oclass = &(struct nvkm_instmem_impl) {
.base.handle = NV_SUBDEV(INSTMEM, 0x04),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv04_instmem_ctor,
.dtor = nv04_instmem_dtor,
.init = _nvkm_instmem_init,
.fini = _nvkm_instmem_fini,
},
static void *
nv04_instmem_dtor(struct nvkm_instmem *base)
{
struct nv04_instmem *imem = nv04_instmem(base);
nvkm_memory_del(&imem->base.ramfc);
nvkm_memory_del(&imem->base.ramro);
nvkm_ramht_del(&imem->base.ramht);
nvkm_memory_del(&imem->base.vbios);
nvkm_mm_fini(&imem->heap);
return imem;
}
static const struct nvkm_instmem_func
nv04_instmem = {
.dtor = nv04_instmem_dtor,
.oneinit = nv04_instmem_oneinit,
.rd32 = nv04_instmem_rd32,
.wr32 = nv04_instmem_wr32,
.memory_new = nv04_instobj_new,
.persistent = false,
.zero = false,
}.base;
};
int
nv04_instmem_new(struct nvkm_device *device, int index,
struct nvkm_instmem **pimem)
{
struct nv04_instmem *imem;
if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL)))
return -ENOMEM;
nvkm_instmem_ctor(&nv04_instmem, device, index, &imem->base);
*pimem = &imem->base;
return 0;
}

122
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c
View File

@ -138,67 +138,23 @@ nv40_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero,
*****************************************************************************/
static u32
nv40_instmem_rd32(struct nvkm_instmem *obj, u32 addr)
nv40_instmem_rd32(struct nvkm_instmem *base, u32 addr)
{
struct nv40_instmem *imem = container_of(obj, typeof(*imem), base);
return ioread32_native(imem->iomem + addr);
return ioread32_native(nv40_instmem(base)->iomem + addr);
}
static void
nv40_instmem_wr32(struct nvkm_instmem *obj, u32 addr, u32 data)
nv40_instmem_wr32(struct nvkm_instmem *base, u32 addr, u32 data)
{
struct nv40_instmem *imem = container_of(obj, typeof(*imem), base);
iowrite32_native(data, imem->iomem + addr);
iowrite32_native(data, nv40_instmem(base)->iomem + addr);
}
static void
nv40_instmem_dtor(struct nvkm_object *object)
{
struct nv40_instmem *imem = (void *)object;
nvkm_memory_del(&imem->base.ramfc);
nvkm_memory_del(&imem->base.ramro);
nvkm_ramht_del(&imem->base.ramht);
nvkm_memory_del(&imem->base.vbios);
nvkm_mm_fini(&imem->heap);
if (imem->iomem)
iounmap(imem->iomem);
nvkm_instmem_destroy(&imem->base);
}
static const struct nvkm_instmem_func
nv40_instmem_func = {
.rd32 = nv40_instmem_rd32,
.wr32 = nv40_instmem_wr32,
};
static int
nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
nv40_instmem_oneinit(struct nvkm_instmem *base)
{
struct nvkm_device *device = (void *)parent;
struct nv40_instmem *imem;
int ret, bar, vs;
ret = nvkm_instmem_create(parent, engine, oclass, &imem);
*pobject = nv_object(imem);
if (ret)
return ret;
imem->base.func = &nv40_instmem_func;
/* map bar */
if (nv_device_resource_len(device, 2))
bar = 2;
else
bar = 3;
imem->iomem = ioremap(nv_device_resource_start(device, bar),
nv_device_resource_len(device, bar));
if (!imem->iomem) {
nvkm_error(&imem->base.subdev, "unable to map PRAMIN BAR\n");
return -EFAULT;
}
struct nv40_instmem *imem = nv40_instmem(base);
struct nvkm_device *device = imem->base.subdev.device;
int ret, vs;
/* PRAMIN aperture maps over the end of vram, reserve enough space
* to fit graphics contexts for every channel, the magics come
@ -207,13 +163,12 @@ nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
vs = hweight8((nvkm_rd32(device, 0x001540) & 0x0000ff00) >> 8);
if (device->chipset == 0x40) imem->base.reserved = 0x6aa0 * vs;
else if (device->chipset < 0x43) imem->base.reserved = 0x4f00 * vs;
else if (nv44_gr_class(imem)) imem->base.reserved = 0x4980 * vs;
else if (nv44_gr_class(device)) imem->base.reserved = 0x4980 * vs;
else imem->base.reserved = 0x4a40 * vs;
imem->base.reserved += 16 * 1024;
imem->base.reserved *= 32; /* per-channel */
imem->base.reserved += 512 * 1024; /* pci(e)gart table */
imem->base.reserved += 512 * 1024; /* object storage */
imem->base.reserved = round_up(imem->base.reserved, 4096);
ret = nvkm_mm_init(&imem->heap, 0, imem->base.reserved, 1);
@ -250,16 +205,55 @@ nv40_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
return 0;
}
struct nvkm_oclass *
nv40_instmem_oclass = &(struct nvkm_instmem_impl) {
.base.handle = NV_SUBDEV(INSTMEM, 0x40),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv40_instmem_ctor,
.dtor = nv40_instmem_dtor,
.init = _nvkm_instmem_init,
.fini = _nvkm_instmem_fini,
},
static void *
nv40_instmem_dtor(struct nvkm_instmem *base)
{
struct nv40_instmem *imem = nv40_instmem(base);
nvkm_memory_del(&imem->base.ramfc);
nvkm_memory_del(&imem->base.ramro);
nvkm_ramht_del(&imem->base.ramht);
nvkm_memory_del(&imem->base.vbios);
nvkm_mm_fini(&imem->heap);
if (imem->iomem)
iounmap(imem->iomem);
return imem;
}
static const struct nvkm_instmem_func
nv40_instmem = {
.dtor = nv40_instmem_dtor,
.oneinit = nv40_instmem_oneinit,
.rd32 = nv40_instmem_rd32,
.wr32 = nv40_instmem_wr32,
.memory_new = nv40_instobj_new,
.persistent = false,
.zero = false,
}.base;
};
int
nv40_instmem_new(struct nvkm_device *device, int index,
struct nvkm_instmem **pimem)
{
struct nv40_instmem *imem;
int bar;
if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL)))
return -ENOMEM;
nvkm_instmem_ctor(&nv40_instmem, device, index, &imem->base);
*pimem = &imem->base;
/* map bar */
if (nv_device_resource_len(device, 2))
bar = 2;
else
bar = 3;
imem->iomem = ioremap(nv_device_resource_start(device, bar),
nv_device_resource_len(device, bar));
if (!imem->iomem) {
nvkm_error(&imem->base.subdev, "unable to map PRAMIN BAR\n");
return -EFAULT;
}
return 0;
}

53
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.c
View File

@ -220,41 +220,30 @@ nv50_instobj_new(struct nvkm_instmem *base, u32 size, u32 align, bool zero,
* instmem subdev implementation
*****************************************************************************/
static int
nv50_instmem_fini(struct nvkm_object *object, bool suspend)
static void
nv50_instmem_fini(struct nvkm_instmem *base)
{
struct nv50_instmem *imem = (void *)object;
imem->addr = ~0ULL;
return nvkm_instmem_fini(&imem->base, suspend);
nv50_instmem(base)->addr = ~0ULL;
}
static int
nv50_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
struct nvkm_oclass *oclass, void *data, u32 size,
struct nvkm_object **pobject)
{
struct nv50_instmem *imem;
int ret;
ret = nvkm_instmem_create(parent, engine, oclass, &imem);
*pobject = nv_object(imem);
if (ret)
return ret;
spin_lock_init(&imem->lock);
return 0;
}
struct nvkm_oclass *
nv50_instmem_oclass = &(struct nvkm_instmem_impl) {
.base.handle = NV_SUBDEV(INSTMEM, 0x50),
.base.ofuncs = &(struct nvkm_ofuncs) {
.ctor = nv50_instmem_ctor,
.dtor = _nvkm_instmem_dtor,
.init = _nvkm_instmem_init,
.fini = nv50_instmem_fini,
},
static const struct nvkm_instmem_func
nv50_instmem = {
.fini = nv50_instmem_fini,
.memory_new = nv50_instobj_new,
.persistent = false,
.zero = false,
}.base;
};
int
nv50_instmem_new(struct nvkm_device *device, int index,
struct nvkm_instmem **pimem)
{
struct nv50_instmem *imem;
if (!(imem = kzalloc(sizeof(*imem), GFP_KERNEL)))
return -ENOMEM;
nvkm_instmem_ctor(&nv50_instmem, device, index, &imem->base);
spin_lock_init(&imem->lock);
*pimem = &imem->base;
return 0;
}

29
drivers/gpu/drm/nouveau/nvkm/subdev/instmem/priv.h
View File

@ -1,31 +1,20 @@
#ifndef __NVKM_INSTMEM_PRIV_H__
#define __NVKM_INSTMEM_PRIV_H__
#define nvkm_instmem(p) container_of((p), struct nvkm_instmem, subdev)
#include <subdev/instmem.h>
struct nvkm_instmem_impl {
struct nvkm_oclass base;
struct nvkm_instmem_func {
void *(*dtor)(struct nvkm_instmem *);
int (*oneinit)(struct nvkm_instmem *);
void (*fini)(struct nvkm_instmem *);
u32 (*rd32)(struct nvkm_instmem *, u32 addr);
void (*wr32)(struct nvkm_instmem *, u32 addr, u32 data);
int (*memory_new)(struct nvkm_instmem *, u32 size, u32 align,
bool zero, struct nvkm_memory **);
bool persistent;
bool zero;
};
#define nvkm_instmem_create(p,e,o,d) \
nvkm_instmem_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nvkm_instmem_destroy(p) \
nvkm_subdev_destroy(&(p)->subdev)
#define nvkm_instmem_init(p) ({ \
struct nvkm_instmem *_imem = (p); \
_nvkm_instmem_init(nv_object(_imem)); \
})
#define nvkm_instmem_fini(p,s) ({ \
struct nvkm_instmem *_imem = (p); \
_nvkm_instmem_fini(nv_object(_imem), (s)); \
})
int nvkm_instmem_create_(struct nvkm_object *, struct nvkm_object *,
struct nvkm_oclass *, int, void **);
#define _nvkm_instmem_dtor _nvkm_subdev_dtor
int _nvkm_instmem_init(struct nvkm_object *);
int _nvkm_instmem_fini(struct nvkm_object *, bool);
void nvkm_instmem_ctor(const struct nvkm_instmem_func *, struct nvkm_device *,
int index, struct nvkm_instmem *);
#endif