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Merge branches 'clk-renesas', 'clk-amlogic', 'clk-allwinner' and 'clk-samsung' into clk-next

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* clk-renesas:
  clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C
  clk: renesas: r8a779h0: Add Audio clocks
  clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP
  dt-bindings: clock: rcar-gen2: Remove obsolete header files
  dt-bindings: clock: r8a7779: Remove duplicate newline
  clk: renesas: Drop "Renesas" from individual driver descriptions
  clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments
  clk: renesas: r8a779h0: Add VIN clocks
  dt-bindings: clock: renesas,rzg2l-cpg: Update description for #reset-cells
  clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlock
  clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock
  clk: renesas: r8a77970: Use common cpg_lock
  clk: renesas: r8a779h0: Add CSI-2 clocks
  clk: renesas: r8a779h0: Add ISPCS clocks

* clk-amlogic:
  clk: meson: add missing MODULE_DESCRIPTION() macros
  dt-bindings: clock: meson: a1: peripherals: support sys_pll input
  dt-bindings: clock: meson: a1: pll: introduce new syspll bindings
  clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLL
  clk: meson: c3: add c3 clock peripherals controller driver
  clk: meson: c3: add support for the C3 SoC PLL clock
  dt-bindings: clock: add Amlogic C3 peripherals clock controller
  dt-bindings: clock: add Amlogic C3 SCMI clock controller support
  dt-bindings: clock: add Amlogic C3 PLL clock controller
  dt-bindings: clock: meson: Convert axg-audio-clkc to YAML format
  clk: meson: s4: fix pwm_j_div parent clock
  clk: meson: s4: fix fixed_pll_dco clock

* clk-allwinner:
  clk: sunxi-ng r40: Constify struct regmap_config
  clk: sunxi-ng: h616: Add clock/reset for GPADC
  dt-bindings: clock: sun50i-h616-ccu: Add GPADC clocks
  clk: sunxi: Remove unused struct 'gates_data'
  clk: sunxi-ng: add missing MODULE_DESCRIPTION() macros

* clk-samsung:
  clk: samsung: gs101: mark gout_hsi2_ufs_embd_i_clk_unipro as critical
  clk: samsung: Switch to use kmemdup_array()
  clk: samsung: exynos-clkout: Remove misleading of_match_table/MODULE_DEVICE_TABLE
This commit is contained in:
Stephen Boyd 2024-07-16 11:24:16 -07:00
commit bc060e6bb7
77 changed files with 3977 additions and 847 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
Documentation/devicetree/bindings/clock/amlogic,a1-peripherals-clkc.yaml
View File

@ -30,6 +30,8 @@ properties:
- description: input fixed pll div7
- description: input hifi pll
- description: input oscillator (usually at 24MHz)
- description: input sys pll
minItems: 6 # sys_pll is optional
clock-names:
items:
@ -39,6 +41,8 @@ properties:
- const: fclk_div7
- const: hifi_pll
- const: xtal
- const: sys_pll
minItems: 6 # sys_pll is optional
required:
- compatible
@ -65,9 +69,10 @@ examples:
<&clkc_pll CLKID_FCLK_DIV5>,
<&clkc_pll CLKID_FCLK_DIV7>,
<&clkc_pll CLKID_HIFI_PLL>,
<&xtal>;
<&xtal>,
<&clkc_pll CLKID_SYS_PLL>;
clock-names = "fclk_div2", "fclk_div3",
"fclk_div5", "fclk_div7",
"hifi_pll", "xtal";
"hifi_pll", "xtal", "sys_pll";
};
};

9
Documentation/devicetree/bindings/clock/amlogic,a1-pll-clkc.yaml
View File

@ -26,11 +26,15 @@ properties:
items:
- description: input fixpll_in
- description: input hifipll_in
- description: input syspll_in
minItems: 2 # syspll_in is optional
clock-names:
items:
- const: fixpll_in
- const: hifipll_in
- const: syspll_in
minItems: 2 # syspll_in is optional
required:
- compatible
@ -53,7 +57,8 @@ examples:
reg = <0 0x7c80 0 0x18c>;
#clock-cells = <1>;
clocks = <&clkc_periphs CLKID_FIXPLL_IN>,
<&clkc_periphs CLKID_HIFIPLL_IN>;
clock-names = "fixpll_in", "hifipll_in";
<&clkc_periphs CLKID_HIFIPLL_IN>,
<&clkc_periphs CLKID_SYSPLL_IN>;
clock-names = "fixpll_in", "hifipll_in", "syspll_in";
};
};

59
Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt
View File

@ -1,59 +0,0 @@
* Amlogic AXG Audio Clock Controllers
The Amlogic AXG audio clock controller generates and supplies clock to the
other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
devices.
Required Properties:
- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D,
"amlogic,g12a-audio-clkc" for G12A,
"amlogic,sm1-audio-clkc" for S905X3.
- reg : physical base address of the clock controller and length of
memory mapped region.
- clocks : a list of phandle + clock-specifier pairs for the clocks listed
in clock-names.
- clock-names : must contain the following:
* "pclk" - Main peripheral bus clock
may contain the following:
* "mst_in[0-7]" - 8 input plls to generate clock signals
* "slv_sclk[0-9]" - 10 slave bit clocks provided by external
components.
* "slv_lrclk[0-9]" - 10 slave sample clocks provided by external
components.
- resets : phandle of the internal reset line
- #clock-cells : should be 1.
- #reset-cells : should be 1 on the g12a (and following) soc family
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All available clocks are defined as
preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be
used in device tree sources.
Example:
clkc_audio: clock-controller@0 {
compatible = "amlogic,axg-audio-clkc";
reg = <0x0 0x0 0x0 0xb4>;
#clock-cells = <1>;
clocks = <&clkc CLKID_AUDIO>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL3>,
<&clkc CLKID_HIFI_PLL>,
<&clkc CLKID_FCLK_DIV3>,
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_GP0_PLL>;
clock-names = "pclk",
"mst_in0",
"mst_in1",
"mst_in2",
"mst_in3",
"mst_in4",
"mst_in5",
"mst_in6",
"mst_in7";
resets = <&reset RESET_AUDIO>;
};

201
Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.yaml Normal file
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@ -0,0 +1,201 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,axg-audio-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic AXG Audio Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Jerome Brunet <jbrunet@baylibre.com>
description:
The Amlogic AXG audio clock controller generates and supplies clock to the
other elements of the audio subsystem, such as fifos, i2s, spdif and pdm
devices.
properties:
compatible:
enum:
- amlogic,axg-audio-clkc
- amlogic,g12a-audio-clkc
- amlogic,sm1-audio-clkc
'#clock-cells':
const: 1
'#reset-cells':
const: 1
reg:
maxItems: 1
clocks:
minItems: 1
items:
- description: main peripheral bus clock
- description: input plls to generate clock signals N0
- description: input plls to generate clock signals N1
- description: input plls to generate clock signals N2
- description: input plls to generate clock signals N3
- description: input plls to generate clock signals N4
- description: input plls to generate clock signals N5
- description: input plls to generate clock signals N6
- description: input plls to generate clock signals N7
- description: slave bit clock N0 provided by external components
- description: slave bit clock N1 provided by external components
- description: slave bit clock N2 provided by external components
- description: slave bit clock N3 provided by external components
- description: slave bit clock N4 provided by external components
- description: slave bit clock N5 provided by external components
- description: slave bit clock N6 provided by external components
- description: slave bit clock N7 provided by external components
- description: slave bit clock N8 provided by external components
- description: slave bit clock N9 provided by external components
- description: slave sample clock N0 provided by external components
- description: slave sample clock N1 provided by external components
- description: slave sample clock N2 provided by external components
- description: slave sample clock N3 provided by external components
- description: slave sample clock N4 provided by external components
- description: slave sample clock N5 provided by external components
- description: slave sample clock N6 provided by external components
- description: slave sample clock N7 provided by external components
- description: slave sample clock N8 provided by external components
- description: slave sample clock N9 provided by external components
clock-names:
minItems: 1
items:
- const: pclk
- const: mst_in0
- const: mst_in1
- const: mst_in2
- const: mst_in3
- const: mst_in4
- const: mst_in5
- const: mst_in6
- const: mst_in7
- const: slv_sclk0
- const: slv_sclk1
- const: slv_sclk2
- const: slv_sclk3
- const: slv_sclk4
- const: slv_sclk5
- const: slv_sclk6
- const: slv_sclk7
- const: slv_sclk8
- const: slv_sclk9
- const: slv_lrclk0
- const: slv_lrclk1
- const: slv_lrclk2
- const: slv_lrclk3
- const: slv_lrclk4
- const: slv_lrclk5
- const: slv_lrclk6
- const: slv_lrclk7
- const: slv_lrclk8
- const: slv_lrclk9
resets:
description: internal reset line
required:
- compatible
- '#clock-cells'
- reg
- clocks
- clock-names
- resets
allOf:
- if:
properties:
compatible:
contains:
enum:
- amlogic,g12a-audio-clkc
- amlogic,sm1-audio-clkc
then:
required:
- '#reset-cells'
else:
properties:
'#reset-cells': false
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/axg-clkc.h>
#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
apb {
#address-cells = <2>;
#size-cells = <2>;
clkc_audio: clock-controller@0 {
compatible = "amlogic,axg-audio-clkc";
reg = <0x0 0x0 0x0 0xb4>;
#clock-cells = <1>;
clocks = <&clkc CLKID_AUDIO>,
<&clkc CLKID_MPLL0>,
<&clkc CLKID_MPLL1>,
<&clkc CLKID_MPLL2>,
<&clkc CLKID_MPLL3>,
<&clkc CLKID_HIFI_PLL>,
<&clkc CLKID_FCLK_DIV3>,
<&clkc CLKID_FCLK_DIV4>,
<&clkc CLKID_GP0_PLL>,
<&slv_sclk0>,
<&slv_sclk1>,
<&slv_sclk2>,
<&slv_sclk3>,
<&slv_sclk4>,
<&slv_sclk5>,
<&slv_sclk6>,
<&slv_sclk7>,
<&slv_sclk8>,
<&slv_sclk9>,
<&slv_lrclk0>,
<&slv_lrclk1>,
<&slv_lrclk2>,
<&slv_lrclk3>,
<&slv_lrclk4>,
<&slv_lrclk5>,
<&slv_lrclk6>,
<&slv_lrclk7>,
<&slv_lrclk8>,
<&slv_lrclk9>;
clock-names = "pclk",
"mst_in0",
"mst_in1",
"mst_in2",
"mst_in3",
"mst_in4",
"mst_in5",
"mst_in6",
"mst_in7",
"slv_sclk0",
"slv_sclk1",
"slv_sclk2",
"slv_sclk3",
"slv_sclk4",
"slv_sclk5",
"slv_sclk6",
"slv_sclk7",
"slv_sclk8",
"slv_sclk9",
"slv_lrclk0",
"slv_lrclk1",
"slv_lrclk2",
"slv_lrclk3",
"slv_lrclk4",
"slv_lrclk5",
"slv_lrclk6",
"slv_lrclk7",
"slv_lrclk8",
"slv_lrclk9";
resets = <&reset RESET_AUDIO>;
};
};

120
Documentation/devicetree/bindings/clock/amlogic,c3-peripherals-clkc.yaml Normal file
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@ -0,0 +1,120 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,c3-peripherals-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic C3 series Peripheral Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Jerome Brunet <jbrunet@baylibre.com>
- Xianwei Zhao <xianwei.zhao@amlogic.com>
- Chuan Liu <chuan.liu@amlogic.com>
properties:
compatible:
const: amlogic,c3-peripherals-clkc
reg:
maxItems: 1
clocks:
minItems: 16
items:
- description: input oscillator (usually at 24MHz)
- description: input oscillators multiplexer
- description: input fix pll
- description: input fclk div 2
- description: input fclk div 2p5
- description: input fclk div 3
- description: input fclk div 4
- description: input fclk div 5
- description: input fclk div 7
- description: input gp0 pll
- description: input gp1 pll
- description: input hifi pll
- description: input sys clk
- description: input axi clk
- description: input sys pll div 16
- description: input cpu clk div 16
- description: input pad clock for rtc clk (optional)
clock-names:
minItems: 16
items:
- const: xtal_24m
- const: oscin
- const: fix
- const: fdiv2
- const: fdiv2p5
- const: fdiv3
- const: fdiv4
- const: fdiv5
- const: fdiv7
- const: gp0
- const: gp1
- const: hifi
- const: sysclk
- const: axiclk
- const: sysplldiv16
- const: cpudiv16
- const: pad_osc
"#clock-cells":
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- "#clock-cells"
additionalProperties: false
examples:
- |
apb {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@0 {
compatible = "amlogic,c3-peripherals-clkc";
reg = <0x0 0x0 0x0 0x49c>;
#clock-cells = <1>;
clocks = <&xtal_24m>,
<&scmi_clk 8>,
<&scmi_clk 12>,
<&clkc_pll 3>,
<&clkc_pll 5>,
<&clkc_pll 7>,
<&clkc_pll 9>,
<&clkc_pll 11>,
<&clkc_pll 13>,
<&clkc_pll 15>,
<&scmi_clk 13>,
<&clkc_pll 17>,
<&scmi_clk 9>,
<&scmi_clk 10>,
<&scmi_clk 14>,
<&scmi_clk 15>;
clock-names = "xtal_24m",
"oscin",
"fix",
"fdiv2",
"fdiv2p5",
"fdiv3",
"fdiv4",
"fdiv5",
"fdiv7",
"gp0",
"gp1",
"hifi",
"sysclk",
"axiclk",
"sysplldiv16",
"cpudiv16";
};
};

59
Documentation/devicetree/bindings/clock/amlogic,c3-pll-clkc.yaml Normal file
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@ -0,0 +1,59 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,c3-pll-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic C3 series PLL Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Jerome Brunet <jbrunet@baylibre.com>
- Chuan Liu <chuan.liu@amlogic.com>
- Xianwei Zhao <xianwei.zhao@amlogic.com>
properties:
compatible:
const: amlogic,c3-pll-clkc
reg:
maxItems: 1
clocks:
items:
- description: input top pll
- description: input mclk pll
clock-names:
items:
- const: top
- const: mclk
"#clock-cells":
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- "#clock-cells"
additionalProperties: false
examples:
- |
apb {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@8000 {
compatible = "amlogic,c3-pll-clkc";
reg = <0x0 0x8000 0x0 0x1a4>;
clocks = <&scmi_clk 2>,
<&scmi_clk 5>;
clock-names = "top", "mclk";
#clock-cells = <1>;
};
};

2
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
View File

@ -62,7 +62,7 @@ properties:
'#reset-cells':
description:
The single reset specifier cell must be the module number, as defined in
The single reset specifier cell must be the reset number, as defined in
<dt-bindings/clock/r9a0*-cpg.h>.
const: 1

27
drivers/clk/meson/Kconfig
View File

@ -132,6 +132,33 @@ config COMMON_CLK_A1_PERIPHERALS
device, A1 SoC Family. Say Y if you want A1 Peripherals clock
controller to work.
config COMMON_CLK_C3_PLL
tristate "Amlogic C3 PLL clock controller"
depends on ARM64
default y
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_PLL
select COMMON_CLK_MESON_CLKC_UTILS
imply COMMON_CLK_SCMI
help
Support for the PLL clock controller on Amlogic C302X and C308L devices,
AKA C3. Say Y if you want the board to work, because PLLs are the parent
of most peripherals.
config COMMON_CLK_C3_PERIPHERALS
tristate "Amlogic C3 peripherals clock controller"
depends on ARM64
default y
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_DUALDIV
select COMMON_CLK_MESON_CLKC_UTILS
imply COMMON_CLK_SCMI
imply COMMON_CLK_C3_PLL
help
Support for the Peripherals clock controller on Amlogic C302X and
C308L devices, AKA C3. Say Y if you want the peripherals clock to
work.
config COMMON_CLK_G12A
tristate "G12 and SM1 SoC clock controllers support"
depends on ARM64

2
drivers/clk/meson/Makefile
View File

@ -20,6 +20,8 @@ obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o
obj-$(CONFIG_COMMON_CLK_C3_PLL) += c3-pll.o
obj-$(CONFIG_COMMON_CLK_C3_PERIPHERALS) += c3-peripherals.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o

3
drivers/clk/meson/a1-peripherals.c
View File

@ -2240,8 +2240,9 @@ static struct platform_driver a1_periphs_clkc_driver = {
.of_match_table = a1_periphs_clkc_match_table,
},
};
module_platform_driver(a1_periphs_clkc_driver);
MODULE_DESCRIPTION("Amlogic A1 Peripherals Clock Controller driver");
MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");
MODULE_AUTHOR("Dmitry Rokosov <ddrokosov@sberdevices.ru>");
MODULE_LICENSE("GPL");

3
drivers/clk/meson/a1-pll.c
View File

@ -354,8 +354,9 @@ static struct platform_driver a1_pll_clkc_driver = {
.of_match_table = a1_pll_clkc_match_table,
},
};
module_platform_driver(a1_pll_clkc_driver);
MODULE_DESCRIPTION("Amlogic S4 PLL Clock Controller driver");
MODULE_AUTHOR("Jian Hu <jian.hu@amlogic.com>");
MODULE_AUTHOR("Dmitry Rokosov <ddrokosov@sberdevices.ru>");
MODULE_LICENSE("GPL");

3
drivers/clk/meson/axg-aoclk.c
View File

@ -338,6 +338,7 @@ static struct platform_driver axg_aoclkc_driver = {
.of_match_table = axg_aoclkc_match_table,
},
};
module_platform_driver(axg_aoclkc_driver);
MODULE_DESCRIPTION("Amlogic AXG Always-ON Clock Controller driver");
MODULE_LICENSE("GPL");

3
drivers/clk/meson/axg.c
View File

@ -2183,6 +2183,7 @@ static struct platform_driver axg_driver = {
.of_match_table = clkc_match_table,
},
};
module_platform_driver(axg_driver);
MODULE_DESCRIPTION("Amlogic AXG Main Clock Controller driver");
MODULE_LICENSE("GPL");

2366
drivers/clk/meson/c3-peripherals.c Normal file
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File diff suppressed because it is too large Load Diff

747
drivers/clk/meson/c3-pll.c Normal file
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@ -0,0 +1,747 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Amlogic C3 PLL Controller Driver
*
* Copyright (c) 2023 Amlogic, inc.
* Author: Chuan Liu <chuan.liu@amlogic.com>
*/
#include <linux/clk-provider.h>
#include <linux/platform_device.h>
#include "clk-regmap.h"
#include "clk-pll.h"
#include "meson-clkc-utils.h"
#include <dt-bindings/clock/amlogic,c3-pll-clkc.h>
#define ANACTRL_FIXPLL_CTRL4 0x50
#define ANACTRL_GP0PLL_CTRL0 0x80
#define ANACTRL_GP0PLL_CTRL1 0x84
#define ANACTRL_GP0PLL_CTRL2 0x88
#define ANACTRL_GP0PLL_CTRL3 0x8c
#define ANACTRL_GP0PLL_CTRL4 0x90
#define ANACTRL_GP0PLL_CTRL5 0x94
#define ANACTRL_GP0PLL_CTRL6 0x98
#define ANACTRL_HIFIPLL_CTRL0 0x100
#define ANACTRL_HIFIPLL_CTRL1 0x104
#define ANACTRL_HIFIPLL_CTRL2 0x108
#define ANACTRL_HIFIPLL_CTRL3 0x10c
#define ANACTRL_HIFIPLL_CTRL4 0x110
#define ANACTRL_HIFIPLL_CTRL5 0x114
#define ANACTRL_HIFIPLL_CTRL6 0x118
#define ANACTRL_MPLL_CTRL0 0x180
#define ANACTRL_MPLL_CTRL1 0x184
#define ANACTRL_MPLL_CTRL2 0x188
#define ANACTRL_MPLL_CTRL3 0x18c
#define ANACTRL_MPLL_CTRL4 0x190
static struct clk_regmap fclk_50m_en = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_FIXPLL_CTRL4,
.bit_idx = 0,
},
.hw.init = &(struct clk_init_data) {
.name = "fclk_50m_en",
.ops = &clk_regmap_gate_ro_ops,
.parent_data = &(const struct clk_parent_data) {
.fw_name = "fix"
},
.num_parents = 1,
},
};
static struct clk_fixed_factor fclk_50m = {
.mult = 1,
.div = 40,
.hw.init = &(struct clk_init_data) {
.name = "fclk_50m",
.ops = &clk_fixed_factor_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_50m_en.hw
},
.num_parents = 1,
},
};
static struct clk_fixed_factor fclk_div2_div = {
.mult = 1,
.div = 2,
.hw.init = &(struct clk_init_data) {
.name = "fclk_div2_div",
.ops = &clk_fixed_factor_ops,
.parent_data = &(const struct clk_parent_data) {
.fw_name = "fix"
},
.num_parents = 1,
},
};
static struct clk_regmap fclk_div2 = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_FIXPLL_CTRL4,
.bit_idx = 24,
},
.hw.init = &(struct clk_init_data) {
.name = "fclk_div2",
.ops = &clk_regmap_gate_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_div2_div.hw
},
.num_parents = 1,
},
};
static struct clk_fixed_factor fclk_div2p5_div = {
.mult = 2,
.div = 5,
.hw.init = &(struct clk_init_data) {
.name = "fclk_div2p5_div",
.ops = &clk_fixed_factor_ops,
.parent_data = &(const struct clk_parent_data) {
.fw_name = "fix"
},
.num_parents = 1,
},
};
static struct clk_regmap fclk_div2p5 = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_FIXPLL_CTRL4,
.bit_idx = 4,
},
.hw.init = &(struct clk_init_data) {
.name = "fclk_div2p5",
.ops = &clk_regmap_gate_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_div2p5_div.hw
},
.num_parents = 1,
},
};
static struct clk_fixed_factor fclk_div3_div = {
.mult = 1,
.div = 3,
.hw.init = &(struct clk_init_data) {
.name = "fclk_div3_div",
.ops = &clk_fixed_factor_ops,
.parent_data = &(const struct clk_parent_data) {
.fw_name = "fix"
},
.num_parents = 1,
},
};
static struct clk_regmap fclk_div3 = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_FIXPLL_CTRL4,
.bit_idx = 20,
},
.hw.init = &(struct clk_init_data) {
.name = "fclk_div3",
.ops = &clk_regmap_gate_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_div3_div.hw
},
.num_parents = 1,
},
};
static struct clk_fixed_factor fclk_div4_div = {
.mult = 1,
.div = 4,
.hw.init = &(struct clk_init_data) {
.name = "fclk_div4_div",
.ops = &clk_fixed_factor_ops,
.parent_data = &(const struct clk_parent_data) {
.fw_name = "fix"
},
.num_parents = 1,
},
};
static struct clk_regmap fclk_div4 = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_FIXPLL_CTRL4,
.bit_idx = 21,
},
.hw.init = &(struct clk_init_data) {
.name = "fclk_div4",
.ops = &clk_regmap_gate_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_div4_div.hw
},
.num_parents = 1,
},
};
static struct clk_fixed_factor fclk_div5_div = {
.mult = 1,
.div = 5,
.hw.init = &(struct clk_init_data) {
.name = "fclk_div5_div",
.ops = &clk_fixed_factor_ops,
.parent_data = &(const struct clk_parent_data) {
.fw_name = "fix"
},
.num_parents = 1,
},
};
static struct clk_regmap fclk_div5 = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_FIXPLL_CTRL4,
.bit_idx = 22,
},
.hw.init = &(struct clk_init_data) {
.name = "fclk_div5",
.ops = &clk_regmap_gate_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_div5_div.hw
},
.num_parents = 1,
},
};
static struct clk_fixed_factor fclk_div7_div = {
.mult = 1,
.div = 7,
.hw.init = &(struct clk_init_data) {
.name = "fclk_div7_div",
.ops = &clk_fixed_factor_ops,
.parent_data = &(const struct clk_parent_data) {
.fw_name = "fix"
},
.num_parents = 1,
},
};
static struct clk_regmap fclk_div7 = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_FIXPLL_CTRL4,
.bit_idx = 23,
},
.hw.init = &(struct clk_init_data) {
.name = "fclk_div7",
.ops = &clk_regmap_gate_ro_ops,
.parent_hws = (const struct clk_hw *[]) {
&fclk_div7_div.hw
},
.num_parents = 1,
},
};
static const struct reg_sequence c3_gp0_init_regs[] = {
{ .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x0 },
{ .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 },
{ .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 },
{ .reg = ANACTRL_GP0PLL_CTRL5, .def = 0x3927200a },
{ .reg = ANACTRL_GP0PLL_CTRL6, .def = 0x56540000 },
};
static const struct pll_mult_range c3_gp0_pll_mult_range = {
.min = 125,
.max = 250,
};
static struct clk_regmap gp0_pll_dco = {
.data = &(struct meson_clk_pll_data) {
.en = {
.reg_off = ANACTRL_GP0PLL_CTRL0,
.shift = 28,
.width = 1,
},
.m = {
.reg_off = ANACTRL_GP0PLL_CTRL0,
.shift = 0,
.width = 9,
},
.frac = {
.reg_off = ANACTRL_GP0PLL_CTRL1,
.shift = 0,
.width = 19,
},
.n = {
.reg_off = ANACTRL_GP0PLL_CTRL0,
.shift = 10,
.width = 5,
},
.l = {
.reg_off = ANACTRL_GP0PLL_CTRL0,
.shift = 31,
.width = 1,
},
.rst = {
.reg_off = ANACTRL_GP0PLL_CTRL0,
.shift = 29,
.width = 1,
},
.range = &c3_gp0_pll_mult_range,
.init_regs = c3_gp0_init_regs,
.init_count = ARRAY_SIZE(c3_gp0_init_regs),
},
.hw.init = &(struct clk_init_data) {
.name = "gp0_pll_dco",
.ops = &meson_clk_pll_ops,
.parent_data = &(const struct clk_parent_data) {
.fw_name = "top",
},
.num_parents = 1,
},
};
/* The maximum frequency divider supports is 32, not 128(2^7) */
static const struct clk_div_table c3_gp0_pll_od_table[] = {
{ 0, 1 },
{ 1, 2 },
{ 2, 4 },
{ 3, 8 },
{ 4, 16 },
{ 5, 32 },
{ /* sentinel */ }
};
static struct clk_regmap gp0_pll = {
.data = &(struct clk_regmap_div_data) {
.offset = ANACTRL_GP0PLL_CTRL0,
.shift = 16,
.width = 3,
.table = c3_gp0_pll_od_table,
},
.hw.init = &(struct clk_init_data) {
.name = "gp0_pll",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&gp0_pll_dco.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct reg_sequence c3_hifi_init_regs[] = {
{ .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x0 },
{ .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 },
{ .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 },
{ .reg = ANACTRL_HIFIPLL_CTRL5, .def = 0x3927200a },
{ .reg = ANACTRL_HIFIPLL_CTRL6, .def = 0x56540000 },
};
static struct clk_regmap hifi_pll_dco = {
.data = &(struct meson_clk_pll_data) {
.en = {
.reg_off = ANACTRL_HIFIPLL_CTRL0,
.shift = 28,
.width = 1,
},
.m = {
.reg_off = ANACTRL_HIFIPLL_CTRL0,
.shift = 0,
.width = 8,
},
.frac = {
.reg_off = ANACTRL_HIFIPLL_CTRL1,
.shift = 0,
.width = 19,
},
.n = {
.reg_off = ANACTRL_HIFIPLL_CTRL0,
.shift = 10,
.width = 5,
},
.l = {
.reg_off = ANACTRL_HIFIPLL_CTRL0,
.shift = 31,
.width = 1,
},
.rst = {
.reg_off = ANACTRL_HIFIPLL_CTRL0,
.shift = 29,
.width = 1,
},
.range = &c3_gp0_pll_mult_range,
.init_regs = c3_hifi_init_regs,
.init_count = ARRAY_SIZE(c3_hifi_init_regs),
},
.hw.init = &(struct clk_init_data) {
.name = "hifi_pll_dco",
.ops = &meson_clk_pll_ops,
.parent_data = &(const struct clk_parent_data) {
.fw_name = "top",
},
.num_parents = 1,
},
};
static struct clk_regmap hifi_pll = {
.data = &(struct clk_regmap_div_data) {
.offset = ANACTRL_HIFIPLL_CTRL0,
.shift = 16,
.width = 2,
.flags = CLK_DIVIDER_POWER_OF_TWO,
},
.hw.init = &(struct clk_init_data) {
.name = "hifi_pll",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&hifi_pll_dco.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct reg_sequence c3_mclk_init_regs[] = {
{ .reg = ANACTRL_MPLL_CTRL1, .def = 0x1420500f },
{ .reg = ANACTRL_MPLL_CTRL2, .def = 0x00023041 },
{ .reg = ANACTRL_MPLL_CTRL3, .def = 0x18180000 },
{ .reg = ANACTRL_MPLL_CTRL2, .def = 0x00023001 }
};
static const struct pll_mult_range c3_mclk_pll_mult_range = {
.min = 67,
.max = 133,
};
static struct clk_regmap mclk_pll_dco = {
.data = &(struct meson_clk_pll_data) {
.en = {
.reg_off = ANACTRL_MPLL_CTRL0,
.shift = 28,
.width = 1,
},
.m = {
.reg_off = ANACTRL_MPLL_CTRL0,
.shift = 0,
.width = 8,
},
.n = {
.reg_off = ANACTRL_MPLL_CTRL0,
.shift = 16,
.width = 5,
},
.l = {
.reg_off = ANACTRL_MPLL_CTRL0,
.shift = 31,
.width = 1,
},
.rst = {
.reg_off = ANACTRL_MPLL_CTRL0,
.shift = 29,
.width = 1,
},
.range = &c3_mclk_pll_mult_range,
.init_regs = c3_mclk_init_regs,
.init_count = ARRAY_SIZE(c3_mclk_init_regs),
},
.hw.init = &(struct clk_init_data) {
.name = "mclk_pll_dco",
.ops = &meson_clk_pll_ops,
.parent_data = &(const struct clk_parent_data) {
.fw_name = "mclk",
},
.num_parents = 1,
},
};
static const struct clk_div_table c3_mpll_od_table[] = {
{ 0, 1 },
{ 1, 2 },
{ 2, 4 },
{ 3, 8 },
{ 4, 16 },
{ /* sentinel */ }
};
static struct clk_regmap mclk_pll_od = {
.data = &(struct clk_regmap_div_data) {
.offset = ANACTRL_MPLL_CTRL0,
.shift = 12,
.width = 3,
.table = c3_mpll_od_table,
},
.hw.init = &(struct clk_init_data) {
.name = "mclk_pll_od",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&mclk_pll_dco.hw },
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
/* both value 0 and 1 gives divide the input rate by one */
static struct clk_regmap mclk_pll = {
.data = &(struct clk_regmap_div_data) {
.offset = ANACTRL_MPLL_CTRL4,
.shift = 16,
.width = 5,
.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
},
.hw.init = &(struct clk_init_data) {
.name = "mclk_pll",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&mclk_pll_od.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct clk_parent_data mclk_parent[] = {
{ .hw = &mclk_pll.hw },
{ .fw_name = "mclk" },
{ .hw = &fclk_50m.hw }
};
static struct clk_regmap mclk0_sel = {
.data = &(struct clk_regmap_mux_data) {
.offset = ANACTRL_MPLL_CTRL4,
.mask = 0x3,
.shift = 4,
},
.hw.init = &(struct clk_init_data) {
.name = "mclk0_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = mclk_parent,
.num_parents = ARRAY_SIZE(mclk_parent),
},
};
static struct clk_regmap mclk0_div_en = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_MPLL_CTRL4,
.bit_idx = 1,
},
.hw.init = &(struct clk_init_data) {
.name = "mclk0_div_en",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&mclk0_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap mclk0_div = {
.data = &(struct clk_regmap_div_data) {
.offset = ANACTRL_MPLL_CTRL4,
.shift = 2,
.width = 1,
},
.hw.init = &(struct clk_init_data) {
.name = "mclk0_div",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&mclk0_div_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap mclk0 = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_MPLL_CTRL4,
.bit_idx = 0,
},
.hw.init = &(struct clk_init_data) {
.name = "mclk0",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&mclk0_div.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap mclk1_sel = {
.data = &(struct clk_regmap_mux_data) {
.offset = ANACTRL_MPLL_CTRL4,
.mask = 0x3,
.shift = 12,
},
.hw.init = &(struct clk_init_data) {
.name = "mclk1_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = mclk_parent,
.num_parents = ARRAY_SIZE(mclk_parent),
},
};
static struct clk_regmap mclk1_div_en = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_MPLL_CTRL4,
.bit_idx = 9,
},
.hw.init = &(struct clk_init_data) {
.name = "mclk1_div_en",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&mclk1_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap mclk1_div = {
.data = &(struct clk_regmap_div_data) {
.offset = ANACTRL_MPLL_CTRL4,
.shift = 10,
.width = 1,
},
.hw.init = &(struct clk_init_data) {
.name = "mclk1_div",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&mclk1_div_en.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap mclk1 = {
.data = &(struct clk_regmap_gate_data) {
.offset = ANACTRL_MPLL_CTRL4,
.bit_idx = 8,
},
.hw.init = &(struct clk_init_data) {
.name = "mclk1",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&mclk1_div.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_hw *c3_pll_hw_clks[] = {
[CLKID_FCLK_50M_EN] = &fclk_50m_en.hw,
[CLKID_FCLK_50M] = &fclk_50m.hw,
[CLKID_FCLK_DIV2_DIV] = &fclk_div2_div.hw,
[CLKID_FCLK_DIV2] = &fclk_div2.hw,
[CLKID_FCLK_DIV2P5_DIV] = &fclk_div2p5_div.hw,
[CLKID_FCLK_DIV2P5] = &fclk_div2p5.hw,
[CLKID_FCLK_DIV3_DIV] = &fclk_div3_div.hw,
[CLKID_FCLK_DIV3] = &fclk_div3.hw,
[CLKID_FCLK_DIV4_DIV] = &fclk_div4_div.hw,
[CLKID_FCLK_DIV4] = &fclk_div4.hw,
[CLKID_FCLK_DIV5_DIV] = &fclk_div5_div.hw,
[CLKID_FCLK_DIV5] = &fclk_div5.hw,
[CLKID_FCLK_DIV7_DIV] = &fclk_div7_div.hw,
[CLKID_FCLK_DIV7] = &fclk_div7.hw,
[CLKID_GP0_PLL_DCO] = &gp0_pll_dco.hw,
[CLKID_GP0_PLL] = &gp0_pll.hw,
[CLKID_HIFI_PLL_DCO] = &hifi_pll_dco.hw,
[CLKID_HIFI_PLL] = &hifi_pll.hw,
[CLKID_MCLK_PLL_DCO] = &mclk_pll_dco.hw,
[CLKID_MCLK_PLL_OD] = &mclk_pll_od.hw,
[CLKID_MCLK_PLL] = &mclk_pll.hw,
[CLKID_MCLK0_SEL] = &mclk0_sel.hw,
[CLKID_MCLK0_SEL_EN] = &mclk0_div_en.hw,
[CLKID_MCLK0_DIV] = &mclk0_div.hw,
[CLKID_MCLK0] = &mclk0.hw,
[CLKID_MCLK1_SEL] = &mclk1_sel.hw,
[CLKID_MCLK1_SEL_EN] = &mclk1_div_en.hw,
[CLKID_MCLK1_DIV] = &mclk1_div.hw,
[CLKID_MCLK1] = &mclk1.hw
};
/* Convenience table to populate regmap in .probe */
static struct clk_regmap *const c3_pll_clk_regmaps[] = {
&fclk_50m_en,
&fclk_div2,
&fclk_div2p5,
&fclk_div3,
&fclk_div4,
&fclk_div5,
&fclk_div7,
&gp0_pll_dco,
&gp0_pll,
&hifi_pll_dco,
&hifi_pll,
&mclk_pll_dco,
&mclk_pll_od,
&mclk_pll,
&mclk0_sel,
&mclk0_div_en,
&mclk0_div,
&mclk0,
&mclk1_sel,
&mclk1_div_en,
&mclk1_div,
&mclk1,
};
static struct regmap_config clkc_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = ANACTRL_MPLL_CTRL4,
};
static struct meson_clk_hw_data c3_pll_clks = {
.hws = c3_pll_hw_clks,
.num = ARRAY_SIZE(c3_pll_hw_clks),
};
static int c3_pll_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct regmap *regmap;
void __iomem *base;
int clkid, ret, i;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
return PTR_ERR(base);
regmap = devm_regmap_init_mmio(dev, base, &clkc_regmap_config);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* Populate regmap for the regmap backed clocks */
for (i = 0; i < ARRAY_SIZE(c3_pll_clk_regmaps); i++)
c3_pll_clk_regmaps[i]->map = regmap;
for (clkid = 0; clkid < c3_pll_clks.num; clkid++) {
/* array might be sparse */
if (!c3_pll_clks.hws[clkid])
continue;
ret = devm_clk_hw_register(dev, c3_pll_clks.hws[clkid]);
if (ret) {
dev_err(dev, "Clock registration failed\n");
return ret;
}
}
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get,
&c3_pll_clks);
}
static const struct of_device_id c3_pll_clkc_match_table[] = {
{
.compatible = "amlogic,c3-pll-clkc",
},
{}
};
MODULE_DEVICE_TABLE(of, c3_pll_clkc_match_table);
static struct platform_driver c3_pll_driver = {
.probe = c3_pll_probe,
.driver = {
.name = "c3-pll-clkc",
.of_match_table = c3_pll_clkc_match_table,
},
};
module_platform_driver(c3_pll_driver);
MODULE_DESCRIPTION("Amlogic C3 PLL Clock Controller driver");
MODULE_AUTHOR("Chuan Liu <chuan.liu@amlogic.com>");
MODULE_LICENSE("GPL");

46
drivers/clk/meson/clk-pll.c
View File

@ -289,25 +289,6 @@ static int meson_clk_pll_wait_lock(struct clk_hw *hw)
return -ETIMEDOUT;
}
static int meson_clk_pll_init(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
if (pll->init_count) {
if (MESON_PARM_APPLICABLE(&pll->rst))
meson_parm_write(clk->map, &pll->rst, 1);
regmap_multi_reg_write(clk->map, pll->init_regs,
pll->init_count);
if (MESON_PARM_APPLICABLE(&pll->rst))
meson_parm_write(clk->map, &pll->rst, 0);
}
return 0;
}
static int meson_clk_pll_is_enabled(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
@ -324,6 +305,33 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw)
return 1;
}
static int meson_clk_pll_init(struct clk_hw *hw)
{
struct clk_regmap *clk = to_clk_regmap(hw);
struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
/*
* Keep the clock running, which was already initialized and enabled
* from the bootloader stage, to avoid any glitches.
*/
if ((pll->flags & CLK_MESON_PLL_NOINIT_ENABLED) &&
meson_clk_pll_is_enabled(hw))
return 0;
if (pll->init_count) {
if (MESON_PARM_APPLICABLE(&pll->rst))
meson_parm_write(clk->map, &pll->rst, 1);
regmap_multi_reg_write(clk->map, pll->init_regs,
pll->init_count);
if (MESON_PARM_APPLICABLE(&pll->rst))
meson_parm_write(clk->map, &pll->rst, 0);
}
return 0;
}
static int meson_clk_pcie_pll_enable(struct clk_hw *hw)
{
int retries = 10;

1
drivers/clk/meson/clk-pll.h
View File

@ -28,6 +28,7 @@ struct pll_mult_range {
}
#define CLK_MESON_PLL_ROUND_CLOSEST BIT(0)
#define CLK_MESON_PLL_NOINIT_ENABLED BIT(1)
struct meson_clk_pll_data {
struct parm en;

3
drivers/clk/meson/g12a-aoclk.c
View File

@ -473,6 +473,7 @@ static struct platform_driver g12a_aoclkc_driver = {
.of_match_table = g12a_aoclkc_match_table,
},
};
module_platform_driver(g12a_aoclkc_driver);
MODULE_DESCRIPTION("Amlogic G12A Always-ON Clock Controller driver");
MODULE_LICENSE("GPL");

3
drivers/clk/meson/g12a.c
View File

@ -5612,6 +5612,7 @@ static struct platform_driver g12a_driver = {
.of_match_table = clkc_match_table,
},
};
module_platform_driver(g12a_driver);
MODULE_DESCRIPTION("Amlogic G12/SM1 Main Clock Controller driver");
MODULE_LICENSE("GPL");

2
drivers/clk/meson/gxbb-aoclk.c
View File

@ -300,4 +300,6 @@ static struct platform_driver gxbb_aoclkc_driver = {
},
};
module_platform_driver(gxbb_aoclkc_driver);
MODULE_DESCRIPTION("Amlogic GXBB Always-ON Clock Controller driver");
MODULE_LICENSE("GPL");

3
drivers/clk/meson/gxbb.c
View File

@ -3567,6 +3567,7 @@ static struct platform_driver gxbb_driver = {
.of_match_table = clkc_match_table,
},
};
module_platform_driver(gxbb_driver);
MODULE_DESCRIPTION("Amlogic GXBB Main Clock Controller driver");
MODULE_LICENSE("GPL");

2
drivers/clk/meson/meson-aoclk.c
View File

@ -89,4 +89,6 @@ int meson_aoclkc_probe(struct platform_device *pdev)
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
}
EXPORT_SYMBOL_GPL(meson_aoclkc_probe);
MODULE_DESCRIPTION("Amlogic Always-ON Clock Controller helpers");
MODULE_LICENSE("GPL");

1
drivers/clk/meson/meson-clkc-utils.c
View File

@ -22,4 +22,5 @@ struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_da
}
EXPORT_SYMBOL_GPL(meson_clk_hw_get);
MODULE_DESCRIPTION("Amlogic Clock Controller Utilities");
MODULE_LICENSE("GPL");

2
drivers/clk/meson/meson-eeclk.c
View File

@ -58,4 +58,6 @@ int meson_eeclkc_probe(struct platform_device *pdev)
return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->hw_clks);
}
EXPORT_SYMBOL_GPL(meson_eeclkc_probe);
MODULE_DESCRIPTION("Amlogic Main Clock Controller Helpers");
MODULE_LICENSE("GPL");

5
drivers/clk/meson/s4-peripherals.c
View File

@ -2978,7 +2978,7 @@ static struct clk_regmap s4_pwm_j_div = {
.name = "pwm_j_div",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&s4_pwm_h_mux.hw
&s4_pwm_j_mux.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
@ -3809,7 +3809,8 @@ static struct platform_driver s4_driver = {
.of_match_table = clkc_match_table,
},
};
module_platform_driver(s4_driver);
MODULE_DESCRIPTION("Amlogic S4 Peripherals Clock Controller driver");
MODULE_AUTHOR("Yu Tu <yu.tu@amlogic.com>");
MODULE_LICENSE("GPL");

8
drivers/clk/meson/s4-pll.c
View File

@ -38,6 +38,11 @@ static struct clk_regmap s4_fixed_pll_dco = {
.shift = 0,
.width = 8,
},
.frac = {
.reg_off = ANACTRL_FIXPLL_CTRL1,
.shift = 0,
.width = 17,
},
.n = {
.reg_off = ANACTRL_FIXPLL_CTRL0,
.shift = 10,
@ -863,7 +868,8 @@ static struct platform_driver s4_driver = {
.of_match_table = clkc_match_table,
},
};
module_platform_driver(s4_driver);
MODULE_DESCRIPTION("Amlogic S4 PLL Clock Controller driver");
MODULE_AUTHOR("Yu Tu <yu.tu@amlogic.com>");
MODULE_LICENSE("GPL");

4
drivers/clk/renesas/Kconfig
View File

@ -218,14 +218,14 @@ config CLK_RCAR_GEN4_CPG
select CLK_RENESAS_CPG_MSSR
config CLK_RCAR_USB2_CLOCK_SEL
bool "Renesas R-Car USB2 clock selector support"
bool "R-Car USB2 clock selector support"
depends on ARCH_RENESAS || COMPILE_TEST
select RESET_CONTROLLER
help
This is a driver for R-Car USB2 clock selector
config CLK_RZG2L
bool "Renesas RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST
bool "RZ/{G2L,G2UL,G3S,V2L} family clock support" if COMPILE_TEST
select RESET_CONTROLLER
# Generic

5
drivers/clk/renesas/r8a77970-cpg-mssr.c
View File

@ -18,6 +18,7 @@
#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
#include "renesas-cpg-mssr.h"
#include "rcar-cpg-lib.h"
#include "rcar-gen3-cpg.h"
#define CPG_SD0CKCR 0x0074
@ -47,8 +48,6 @@ enum clk_ids {
MOD_CLK_BASE
};
static spinlock_t cpg_lock;
static const struct clk_div_table cpg_sd0h_div_table[] = {
{ 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
{ 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
@ -213,8 +212,6 @@ static int __init r8a77970_cpg_mssr_init(struct device *dev)
if (error)
return error;
spin_lock_init(&cpg_lock);
cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);

28
drivers/clk/renesas/r8a779h0-cpg-mssr.c
View File

@ -176,6 +176,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC),
DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC),
DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC),
DEF_MOD("csi40", 331, R8A779H0_CLK_CSI),
DEF_MOD("csi41", 400, R8A779H0_CLK_CSI),
DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1),
DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1),
DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1),
@ -185,6 +187,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
DEF_MOD("i2c2", 520, R8A779H0_CLK_S0D6_PER),
DEF_MOD("i2c3", 521, R8A779H0_CLK_S0D6_PER),
DEF_MOD("irqc", 611, R8A779H0_CLK_CL16M),
DEF_MOD("ispcs0", 612, R8A779H0_CLK_S0D2_VIO),
DEF_MOD("ispcs1", 613, R8A779H0_CLK_S0D2_VIO),
DEF_MOD("msi0", 618, R8A779H0_CLK_MSO),
DEF_MOD("msi1", 619, R8A779H0_CLK_MSO),
DEF_MOD("msi2", 620, R8A779H0_CLK_MSO),
@ -204,6 +208,22 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
DEF_MOD("tmu2", 715, R8A779H0_CLK_SASYNCPERD2),
DEF_MOD("tmu3", 716, R8A779H0_CLK_SASYNCPERD2),
DEF_MOD("tmu4", 717, R8A779H0_CLK_SASYNCPERD2),
DEF_MOD("vin00", 730, R8A779H0_CLK_S0D4_VIO),
DEF_MOD("vin01", 731, R8A779H0_CLK_S0D4_VIO),
DEF_MOD("vin02", 800, R8A779H0_CLK_S0D4_VIO),
DEF_MOD("vin03", 801, R8A779H0_CLK_S0D4_VIO),
DEF_MOD("vin04", 802, R8A779H0_CLK_S0D4_VIO),
DEF_MOD("vin05", 803, R8A779H0_CLK_S0D4_VIO),
DEF_MOD("vin06", 804, R8A779H0_CLK_S0D4_VIO),
DEF_MOD("vin07", 805, R8A779H0_CLK_S0D4_VIO),
DEF_MOD("vin10", 806, R8A779H0_CLK_S0D4_VIO),
DEF_MOD("vin11", 807, R8A779H0_CLK_S0D4_VIO),
DEF_MOD("vin12", 808, R8A779H0_CLK_S0D4_VIO),
DEF_MOD("vin13", 809, R8A779H0_CLK_S0D4_VIO),
DEF_MOD("vin14", 810, R8A779H0_CLK_S0D4_VIO),
DEF_MOD("vin15", 811, R8A779H0_CLK_S0D4_VIO),
DEF_MOD("vin16", 812, R8A779H0_CLK_S0D4_VIO),
DEF_MOD("vin17", 813, R8A779H0_CLK_S0D4_VIO),
DEF_MOD("wdt1:wdt0", 907, R8A779H0_CLK_R),
DEF_MOD("cmt0", 910, R8A779H0_CLK_R),
DEF_MOD("cmt1", 911, R8A779H0_CLK_R),
@ -213,6 +233,8 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
DEF_MOD("pfc2", 917, R8A779H0_CLK_CP),
DEF_MOD("tsc2:tsc1", 919, R8A779H0_CLK_CL16M),
DEF_MOD("ssiu", 2926, R8A779H0_CLK_S0D6_PER),
DEF_MOD("ssi", 2927, R8A779H0_CLK_S0D6_PER),
};
/*
@ -222,10 +244,10 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
* MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
* 14 13 (MHz)
* ------------------------------------------------------------------------
* 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16
* 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19
* 0 0 16.66 / 1 x192 x240 x192 x240 x192 x168 /16
* 0 1 20 / 1 x160 x200 x160 x200 x160 x140 /19
* 1 0 Prohibited setting
* 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32
* 1 1 33.33 / 2 x192 x240 x192 x240 x192 x168 /32
*/
#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))

26
drivers/clk/renesas/r9a08g045-cpg.c
View File

@ -213,8 +213,13 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1),
DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1),
DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9),
DEF_MOD("i2c0_pclk", R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0),
DEF_MOD("i2c1_pclk", R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1),
DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2),
DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3),
DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0),
DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0),
DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0),
};
static const struct rzg2l_reset r9a08g045_resets[] = {
@ -227,10 +232,15 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
DEF_RST(R9A08G045_SDHI2_IXRST, 0x854, 2),
DEF_RST(R9A08G045_ETH0_RST_HW_N, 0x87c, 0),
DEF_RST(R9A08G045_ETH1_RST_HW_N, 0x87c, 1),
DEF_RST(R9A08G045_I2C0_MRST, 0x880, 0),
DEF_RST(R9A08G045_I2C1_MRST, 0x880, 1),
DEF_RST(R9A08G045_I2C2_MRST, 0x880, 2),
DEF_RST(R9A08G045_I2C3_MRST, 0x880, 3),
DEF_RST(R9A08G045_SCIF0_RST_SYSTEM_N, 0x884, 0),
DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0),
DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1),
DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2),
DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0),
};
static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
@ -238,6 +248,7 @@ static const unsigned int r9a08g045_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A08G045_IA55_PCLK,
MOD_CLK_BASE + R9A08G045_IA55_CLK,
MOD_CLK_BASE + R9A08G045_DMAC_ACLK,
MOD_CLK_BASE + R9A08G045_VBAT_BCLK,
};
static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
@ -272,9 +283,24 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08g045_pm_domains[] = {
DEF_PD("eth1", R9A08G045_PD_ETHER1,
DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(3)),
RZG2L_PD_F_NONE),
DEF_PD("i2c0", R9A08G045_PD_I2C0,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(10)),
RZG2L_PD_F_NONE),
DEF_PD("i2c1", R9A08G045_PD_I2C1,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(11)),
RZG2L_PD_F_NONE),
DEF_PD("i2c2", R9A08G045_PD_I2C2,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(12)),
RZG2L_PD_F_NONE),
DEF_PD("i2c3", R9A08G045_PD_I2C3,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(13)),
RZG2L_PD_F_NONE),
DEF_PD("scif0", R9A08G045_PD_SCIF0,
DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(1)),
RZG2L_PD_F_NONE),
DEF_PD("vbat", R9A08G045_PD_VBAT,
DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)),
RZG2L_PD_F_ALWAYS_ON),
};
const struct rzg2l_cpg_info r9a08g045_cpg_info = {

2
drivers/clk/renesas/rcar-cpg-lib.c
View File

@ -22,7 +22,7 @@
#include "rcar-cpg-lib.h"
spinlock_t cpg_lock;
DEFINE_SPINLOCK(cpg_lock);
void cpg_reg_modify(void __iomem *reg, u32 clear, u32 set)
{

4
drivers/clk/renesas/rcar-gen2-cpg.c
View File

@ -30,7 +30,7 @@
#define CPG_ADSPCKCR 0x025c
#define CPG_RCANCKCR 0x0270
static spinlock_t cpg_lock;
static DEFINE_SPINLOCK(cpg_lock);
/*
* Z Clock
@ -387,7 +387,5 @@ int __init rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config,
cpg_quirks = (uintptr_t)attr->data;
pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
spin_lock_init(&cpg_lock);
return 0;
}

2
drivers/clk/renesas/rcar-gen3-cpg.c
View File

@ -551,7 +551,5 @@ int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
cpg_quirks = (uintptr_t)attr->data;
pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, cpg_quirks);
spin_lock_init(&cpg_lock);
return 0;
}

2
drivers/clk/renesas/rcar-gen4-cpg.c
View File

@ -466,7 +466,5 @@ int __init rcar_gen4_cpg_init(const struct rcar_gen4_cpg_pll_config *config,
cpg_clk_extalr = clk_extalr;
cpg_mode = mode;
spin_lock_init(&cpg_lock);
return 0;
}

4
drivers/clk/samsung/clk-cpu.c
View File

@ -689,8 +689,8 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
for (num_cfgs = 0; clk_data->cfg[num_cfgs].prate != 0; )
num_cfgs++;
cpuclk->cfg = kmemdup(clk_data->cfg, sizeof(*clk_data->cfg) * num_cfgs,
GFP_KERNEL);
cpuclk->cfg = kmemdup_array(clk_data->cfg, num_cfgs, sizeof(*cpuclk->cfg),
GFP_KERNEL);
if (!cpuclk->cfg) {
ret = -ENOMEM;
goto unregister_clk_nb;

7
drivers/clk/samsung/clk-exynos-clkout.c
View File

@ -17,6 +17,8 @@
#include <linux/platform_device.h>
#include <linux/pm.h>
#define DRV_NAME "exynos-clkout"
#define EXYNOS_CLKOUT_NR_CLKS 1
#define EXYNOS_CLKOUT_PARENTS 32
@ -75,7 +77,6 @@ static const struct of_device_id exynos_clkout_ids[] = {
.data = &exynos_clkout_exynos5,
}, { }
};
MODULE_DEVICE_TABLE(of, exynos_clkout_ids);
/*
* Device will be instantiated as child of PMU device without its own
@ -236,8 +237,7 @@ static SIMPLE_DEV_PM_OPS(exynos_clkout_pm_ops, exynos_clkout_suspend,
static struct platform_driver exynos_clkout_driver = {
.driver = {
.name = "exynos-clkout",
.of_match_table = exynos_clkout_ids,
.name = DRV_NAME,
.pm = &exynos_clkout_pm_ops,
},
.probe = exynos_clkout_probe,
@ -248,4 +248,5 @@ module_platform_driver(exynos_clkout_driver);
MODULE_AUTHOR("Krzysztof Kozlowski <krzk@kernel.org>");
MODULE_AUTHOR("Tomasz Figa <tomasz.figa@gmail.com>");
MODULE_DESCRIPTION("Samsung Exynos clock output driver");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_LICENSE("GPL");

2
drivers/clk/samsung/clk-gs101.c
View File

@ -2846,7 +2846,7 @@ static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = {
GATE(CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO,
"gout_hsi2_ufs_embd_i_clk_unipro", "mout_hsi2_ufs_embd_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
21, 0, 0),
21, CLK_IS_CRITICAL, 0),
GATE(CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK,
"gout_hsi2_ufs_embd_i_fmp_clk", "mout_hsi2_bus_user",
CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,

8
drivers/clk/samsung/clk-pll.c
View File

@ -1286,10 +1286,10 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
len++;
pll->rate_count = len;
pll->rate_table = kmemdup(pll_clk->rate_table,
pll->rate_count *
sizeof(struct samsung_pll_rate_table),
GFP_KERNEL);
pll->rate_table = kmemdup_array(pll_clk->rate_table,
pll->rate_count,
sizeof(*pll->rate_table),
GFP_KERNEL);
WARN(!pll->rate_table,
"%s: could not allocate rate table for %s\n",
__func__, pll_clk->name);

1
drivers/clk/sunxi-ng/ccu-sun20i-d1-r.c
View File

@ -138,4 +138,5 @@ static struct platform_driver sun20i_d1_r_ccu_driver = {
module_platform_driver(sun20i_d1_r_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner D1/R528/T113 PRCM CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun20i-d1.c
View File

@ -1407,4 +1407,5 @@ static struct platform_driver sun20i_d1_ccu_driver = {
module_platform_driver(sun20i_d1_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner D1/R528/T113 CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun4i-a10.c
View File

@ -1494,4 +1494,5 @@ static struct platform_driver sun4i_a10_ccu_driver = {
module_platform_driver(sun4i_a10_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner A10/A20 CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
View File

@ -215,4 +215,5 @@ static struct platform_driver sun50i_a100_r_ccu_driver = {
module_platform_driver(sun50i_a100_r_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner A100 PRCM CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun50i-a100.c
View File

@ -1277,4 +1277,5 @@ static struct platform_driver sun50i_a100_ccu_driver = {
module_platform_driver(sun50i_a100_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner A100 CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun50i-a64.c
View File

@ -995,4 +995,5 @@ static struct platform_driver sun50i_a64_ccu_driver = {
module_platform_driver(sun50i_a64_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner A64 CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
View File

@ -257,4 +257,5 @@ static struct platform_driver sun50i_h6_r_ccu_driver = {
module_platform_driver(sun50i_h6_r_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner H6 and H616 PRCM CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
View File

@ -1287,4 +1287,5 @@ static struct platform_driver sun50i_h6_ccu_driver = {
module_platform_driver(sun50i_h6_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner H6 CCU");
MODULE_LICENSE("GPL");

6
drivers/clk/sunxi-ng/ccu-sun50i-h616.c
View File

@ -489,6 +489,8 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0,
static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb1", 0x9ec, BIT(0), 0);
static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
static const char * const audio_parents[] = { "pll-audio-1x", "pll-audio-2x",
@ -807,6 +809,7 @@ static struct ccu_common *sun50i_h616_ccu_clks[] = {
&bus_emac1_clk.common,
&ts_clk.common,
&bus_ts_clk.common,
&bus_gpadc_clk.common,
&bus_ths_clk.common,
&spdif_clk.common,
&bus_spdif_clk.common,
@ -940,6 +943,7 @@ static struct clk_hw_onecell_data sun50i_h616_hw_clks = {
[CLK_BUS_EMAC1] = &bus_emac1_clk.common.hw,
[CLK_TS] = &ts_clk.common.hw,
[CLK_BUS_TS] = &bus_ts_clk.common.hw,
[CLK_BUS_GPADC] = &bus_gpadc_clk.common.hw,
[CLK_BUS_THS] = &bus_ths_clk.common.hw,
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
@ -1021,6 +1025,7 @@ static struct ccu_reset_map sun50i_h616_ccu_resets[] = {
[RST_BUS_EMAC0] = { 0x97c, BIT(16) },
[RST_BUS_EMAC1] = { 0x97c, BIT(17) },
[RST_BUS_TS] = { 0x9bc, BIT(16) },
[RST_BUS_GPADC] = { 0x9ec, BIT(16) },
[RST_BUS_THS] = { 0x9fc, BIT(16) },
[RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
[RST_BUS_DMIC] = { 0xa4c, BIT(16) },
@ -1167,4 +1172,5 @@ static struct platform_driver sun50i_h616_ccu_driver = {
module_platform_driver(sun50i_h616_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner H616 CCU");
MODULE_LICENSE("GPL");

2
drivers/clk/sunxi-ng/ccu-sun50i-h616.h
View File

@ -51,6 +51,6 @@
#define CLK_BUS_DRAM 56
#define CLK_NUMBER (CLK_PLL_SYSTEM_32K + 1)
#define CLK_NUMBER (CLK_BUS_GPADC + 1)
#endif /* _CCU_SUN50I_H616_H_ */

1
drivers/clk/sunxi-ng/ccu-sun6i-a31.c
View File

@ -1284,4 +1284,5 @@ static struct platform_driver sun6i_a31_ccu_driver = {
module_platform_driver(sun6i_a31_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner A31/A31s CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun6i-rtc.c
View File

@ -382,4 +382,5 @@ int sun6i_rtc_ccu_probe(struct device *dev, void __iomem *reg)
}
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner H616/R329 RTC CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun8i-a23.c
View File

@ -764,4 +764,5 @@ static struct platform_driver sun8i_a23_ccu_driver = {
module_platform_driver(sun8i_a23_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner A23 CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun8i-a33.c
View File

@ -836,4 +836,5 @@ static struct platform_driver sun8i_a33_ccu_driver = {
module_platform_driver(sun8i_a33_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner A33 CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
View File

@ -924,4 +924,5 @@ static struct platform_driver sun8i_a83t_ccu_driver = {
module_platform_driver(sun8i_a83t_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner A83T CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun8i-de2.c
View File

@ -349,4 +349,5 @@ static struct platform_driver sunxi_de2_clk_driver = {
module_platform_driver(sunxi_de2_clk_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner SoCs DE2 CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun8i-h3.c
View File

@ -1095,4 +1095,5 @@ static struct platform_driver sun8i_h3_ccu_driver = {
module_platform_driver(sun8i_h3_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner H3 CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun8i-r.c
View File

@ -275,4 +275,5 @@ static struct platform_driver sun8i_r_ccu_driver = {
module_platform_driver(sun8i_r_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for Allwinner SoCs' PRCM CCUs");
MODULE_LICENSE("GPL");

3
drivers/clk/sunxi-ng/ccu-sun8i-r40.c
View File

@ -1292,7 +1292,7 @@ static bool sun8i_r40_ccu_regmap_accessible_reg(struct device *dev,
return false;
}
static struct regmap_config sun8i_r40_ccu_regmap_config = {
static const struct regmap_config sun8i_r40_ccu_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
@ -1376,4 +1376,5 @@ static struct platform_driver sun8i_r40_ccu_driver = {
module_platform_driver(sun8i_r40_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner R40 CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
View File

@ -781,4 +781,5 @@ static struct platform_driver sun8i_v3s_ccu_driver = {
module_platform_driver(sun8i_v3s_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner V3s CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun9i-a80-de.c
View File

@ -267,4 +267,5 @@ static struct platform_driver sun9i_a80_de_clk_driver = {
module_platform_driver(sun9i_a80_de_clk_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner A80 Display Engine CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun9i-a80-usb.c
View File

@ -139,4 +139,5 @@ static struct platform_driver sun9i_a80_usb_clk_driver = {
module_platform_driver(sun9i_a80_usb_clk_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner A80 USB CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-sun9i-a80.c
View File

@ -1249,4 +1249,5 @@ static struct platform_driver sun9i_a80_ccu_driver = {
module_platform_driver(sun9i_a80_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner A80 CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
View File

@ -578,4 +578,5 @@ static struct platform_driver suniv_f1c100s_ccu_driver = {
module_platform_driver(suniv_f1c100s_ccu_driver);
MODULE_IMPORT_NS(SUNXI_CCU);
MODULE_DESCRIPTION("Support for the Allwinner newer F1C100s CCU");
MODULE_LICENSE("GPL");

1
drivers/clk/sunxi-ng/ccu_common.c
View File

@ -247,4 +247,5 @@ void of_sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
}
}
MODULE_DESCRIPTION("Common clock support for Allwinner SoCs");
MODULE_LICENSE("GPL");

11
drivers/clk/sunxi/clk-sunxi.c
View File

@ -852,17 +852,6 @@ CLK_OF_DECLARE(sun8i_axi, "allwinner,sun8i-a23-axi-clk",
sun8i_axi_clk_setup);
/*
* sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
*/
#define SUNXI_GATES_MAX_SIZE 64
struct gates_data {
DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
};
/*
* sunxi_divs_clk_setup() helper data
*/

1
include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h
View File

@ -164,5 +164,6 @@
#define CLKID_DMC_SEL 151
#define CLKID_DMC_DIV 152
#define CLKID_DMC_SEL2 153
#define CLKID_SYS_PLL_DIV16 154
#endif /* __A1_PERIPHERALS_CLKC_H */

1
include/dt-bindings/clock/amlogic,a1-pll-clkc.h
View File

@ -21,5 +21,6 @@
#define CLKID_FCLK_DIV5 8
#define CLKID_FCLK_DIV7 9
#define CLKID_HIFI_PLL 10
#define CLKID_SYS_PLL 11
#endif /* __A1_PLL_CLKC_H */

212
include/dt-bindings/clock/amlogic,c3-peripherals-clkc.h Normal file
View File

@ -0,0 +1,212 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright (c) 2023 Amlogic, Inc. All rights reserved.
* Author: Chuan Liu <chuan.liu@amlogic.com>
*/
#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H
#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H
#define CLKID_RTC_XTAL_CLKIN 0
#define CLKID_RTC_32K_DIV 1
#define CLKID_RTC_32K_MUX 2
#define CLKID_RTC_32K 3
#define CLKID_RTC_CLK 4
#define CLKID_SYS_RESET_CTRL 5
#define CLKID_SYS_PWR_CTRL 6
#define CLKID_SYS_PAD_CTRL 7
#define CLKID_SYS_CTRL 8
#define CLKID_SYS_TS_PLL 9
#define CLKID_SYS_DEV_ARB 10
#define CLKID_SYS_MMC_PCLK 11
#define CLKID_SYS_CPU_CTRL 12
#define CLKID_SYS_JTAG_CTRL 13
#define CLKID_SYS_IR_CTRL 14
#define CLKID_SYS_IRQ_CTRL 15
#define CLKID_SYS_MSR_CLK 16
#define CLKID_SYS_ROM 17
#define CLKID_SYS_UART_F 18
#define CLKID_SYS_CPU_ARB 19
#define CLKID_SYS_RSA 20
#define CLKID_SYS_SAR_ADC 21
#define CLKID_SYS_STARTUP 22
#define CLKID_SYS_SECURE 23
#define CLKID_SYS_SPIFC 24
#define CLKID_SYS_NNA 25
#define CLKID_SYS_ETH_MAC 26
#define CLKID_SYS_GIC 27
#define CLKID_SYS_RAMA 28
#define CLKID_SYS_BIG_NIC 29
#define CLKID_SYS_RAMB 30
#define CLKID_SYS_AUDIO_PCLK 31
#define CLKID_SYS_PWM_KL 32
#define CLKID_SYS_PWM_IJ 33
#define CLKID_SYS_USB 34
#define CLKID_SYS_SD_EMMC_A 35
#define CLKID_SYS_SD_EMMC_C 36
#define CLKID_SYS_PWM_AB 37
#define CLKID_SYS_PWM_CD 38
#define CLKID_SYS_PWM_EF 39
#define CLKID_SYS_PWM_GH 40
#define CLKID_SYS_SPICC_1 41
#define CLKID_SYS_SPICC_0 42
#define CLKID_SYS_UART_A 43
#define CLKID_SYS_UART_B 44
#define CLKID_SYS_UART_C 45
#define CLKID_SYS_UART_D 46
#define CLKID_SYS_UART_E 47
#define CLKID_SYS_I2C_M_A 48
#define CLKID_SYS_I2C_M_B 49
#define CLKID_SYS_I2C_M_C 50
#define CLKID_SYS_I2C_M_D 51
#define CLKID_SYS_I2S_S_A 52
#define CLKID_SYS_RTC 53
#define CLKID_SYS_GE2D 54
#define CLKID_SYS_ISP 55
#define CLKID_SYS_GPV_ISP_NIC 56
#define CLKID_SYS_GPV_CVE_NIC 57
#define CLKID_SYS_MIPI_DSI_HOST 58
#define CLKID_SYS_MIPI_DSI_PHY 59
#define CLKID_SYS_ETH_PHY 60
#define CLKID_SYS_ACODEC 61
#define CLKID_SYS_DWAP 62
#define CLKID_SYS_DOS 63
#define CLKID_SYS_CVE 64
#define CLKID_SYS_VOUT 65
#define CLKID_SYS_VC9000E 66
#define CLKID_SYS_PWM_MN 67
#define CLKID_SYS_SD_EMMC_B 68
#define CLKID_AXI_SYS_NIC 69
#define CLKID_AXI_ISP_NIC 70
#define CLKID_AXI_CVE_NIC 71
#define CLKID_AXI_RAMB 72
#define CLKID_AXI_RAMA 73
#define CLKID_AXI_CPU_DMC 74
#define CLKID_AXI_NIC 75
#define CLKID_AXI_DMA 76
#define CLKID_AXI_MUX_NIC 77
#define CLKID_AXI_CVE 78
#define CLKID_AXI_DEV1_DMC 79
#define CLKID_AXI_DEV0_DMC 80
#define CLKID_AXI_DSP_DMC 81
#define CLKID_12_24M_IN 82
#define CLKID_12M_24M 83
#define CLKID_FCLK_25M_DIV 84
#define CLKID_FCLK_25M 85
#define CLKID_GEN_SEL 86
#define CLKID_GEN_DIV 87
#define CLKID_GEN 88
#define CLKID_SARADC_SEL 89
#define CLKID_SARADC_DIV 90
#define CLKID_SARADC 91
#define CLKID_PWM_A_SEL 92
#define CLKID_PWM_A_DIV 93
#define CLKID_PWM_A 94
#define CLKID_PWM_B_SEL 95
#define CLKID_PWM_B_DIV 96
#define CLKID_PWM_B 97
#define CLKID_PWM_C_SEL 98
#define CLKID_PWM_C_DIV 99
#define CLKID_PWM_C 100
#define CLKID_PWM_D_SEL 101
#define CLKID_PWM_D_DIV 102
#define CLKID_PWM_D 103
#define CLKID_PWM_E_SEL 104
#define CLKID_PWM_E_DIV 105
#define CLKID_PWM_E 106
#define CLKID_PWM_F_SEL 107
#define CLKID_PWM_F_DIV 108
#define CLKID_PWM_F 109
#define CLKID_PWM_G_SEL 110
#define CLKID_PWM_G_DIV 111
#define CLKID_PWM_G 112
#define CLKID_PWM_H_SEL 113
#define CLKID_PWM_H_DIV 114
#define CLKID_PWM_H 115
#define CLKID_PWM_I_SEL 116
#define CLKID_PWM_I_DIV 117
#define CLKID_PWM_I 118
#define CLKID_PWM_J_SEL 119
#define CLKID_PWM_J_DIV 120
#define CLKID_PWM_J 121
#define CLKID_PWM_K_SEL 122
#define CLKID_PWM_K_DIV 123
#define CLKID_PWM_K 124
#define CLKID_PWM_L_SEL 125
#define CLKID_PWM_L_DIV 126
#define CLKID_PWM_L 127
#define CLKID_PWM_M_SEL 128
#define CLKID_PWM_M_DIV 129
#define CLKID_PWM_M 130
#define CLKID_PWM_N_SEL 131
#define CLKID_PWM_N_DIV 132
#define CLKID_PWM_N 133
#define CLKID_SPICC_A_SEL 134
#define CLKID_SPICC_A_DIV 135
#define CLKID_SPICC_A 136
#define CLKID_SPICC_B_SEL 137
#define CLKID_SPICC_B_DIV 138
#define CLKID_SPICC_B 139
#define CLKID_SPIFC_SEL 140
#define CLKID_SPIFC_DIV 141
#define CLKID_SPIFC 142
#define CLKID_SD_EMMC_A_SEL 143
#define CLKID_SD_EMMC_A_DIV 144
#define CLKID_SD_EMMC_A 145
#define CLKID_SD_EMMC_B_SEL 146
#define CLKID_SD_EMMC_B_DIV 147
#define CLKID_SD_EMMC_B 148
#define CLKID_SD_EMMC_C_SEL 149
#define CLKID_SD_EMMC_C_DIV 150
#define CLKID_SD_EMMC_C 151
#define CLKID_TS_DIV 152
#define CLKID_TS 153
#define CLKID_ETH_125M_DIV 154
#define CLKID_ETH_125M 155
#define CLKID_ETH_RMII_DIV 156
#define CLKID_ETH_RMII 157
#define CLKID_MIPI_DSI_MEAS_SEL 158
#define CLKID_MIPI_DSI_MEAS_DIV 159
#define CLKID_MIPI_DSI_MEAS 160
#define CLKID_DSI_PHY_SEL 161
#define CLKID_DSI_PHY_DIV 162
#define CLKID_DSI_PHY 163
#define CLKID_VOUT_MCLK_SEL 164
#define CLKID_VOUT_MCLK_DIV 165
#define CLKID_VOUT_MCLK 166
#define CLKID_VOUT_ENC_SEL 167
#define CLKID_VOUT_ENC_DIV 168
#define CLKID_VOUT_ENC 169
#define CLKID_HCODEC_0_SEL 170
#define CLKID_HCODEC_0_DIV 171
#define CLKID_HCODEC_0 172
#define CLKID_HCODEC_1_SEL 173
#define CLKID_HCODEC_1_DIV 174
#define CLKID_HCODEC_1 175
#define CLKID_HCODEC 176
#define CLKID_VC9000E_ACLK_SEL 177
#define CLKID_VC9000E_ACLK_DIV 178
#define CLKID_VC9000E_ACLK 179
#define CLKID_VC9000E_CORE_SEL 180
#define CLKID_VC9000E_CORE_DIV 181
#define CLKID_VC9000E_CORE 182
#define CLKID_CSI_PHY0_SEL 183
#define CLKID_CSI_PHY0_DIV 184
#define CLKID_CSI_PHY0 185
#define CLKID_DEWARPA_SEL 186
#define CLKID_DEWARPA_DIV 187
#define CLKID_DEWARPA 188
#define CLKID_ISP0_SEL 189
#define CLKID_ISP0_DIV 190
#define CLKID_ISP0 191
#define CLKID_NNA_CORE_SEL 192
#define CLKID_NNA_CORE_DIV 193
#define CLKID_NNA_CORE 194
#define CLKID_GE2D_SEL 195
#define CLKID_GE2D_DIV 196
#define CLKID_GE2D 197
#define CLKID_VAPB_SEL 198
#define CLKID_VAPB_DIV 199
#define CLKID_VAPB 200
#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PERIPHERALS_CLKC_H */

40
include/dt-bindings/clock/amlogic,c3-pll-clkc.h Normal file
View File

@ -0,0 +1,40 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright (c) 2023 Amlogic, Inc. All rights reserved.
* Author: Chuan Liu <chuan.liu@amlogic.com>
*/
#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
#define _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H
#define CLKID_FCLK_50M_EN 0
#define CLKID_FCLK_50M 1
#define CLKID_FCLK_DIV2_DIV 2
#define CLKID_FCLK_DIV2 3
#define CLKID_FCLK_DIV2P5_DIV 4
#define CLKID_FCLK_DIV2P5 5
#define CLKID_FCLK_DIV3_DIV 6
#define CLKID_FCLK_DIV3 7
#define CLKID_FCLK_DIV4_DIV 8
#define CLKID_FCLK_DIV4 9
#define CLKID_FCLK_DIV5_DIV 10
#define CLKID_FCLK_DIV5 11
#define CLKID_FCLK_DIV7_DIV 12
#define CLKID_FCLK_DIV7 13
#define CLKID_GP0_PLL_DCO 14
#define CLKID_GP0_PLL 15
#define CLKID_HIFI_PLL_DCO 16
#define CLKID_HIFI_PLL 17
#define CLKID_MCLK_PLL_DCO 18
#define CLKID_MCLK_PLL_OD 19
#define CLKID_MCLK_PLL 20
#define CLKID_MCLK0_SEL 21
#define CLKID_MCLK0_SEL_EN 22
#define CLKID_MCLK0_DIV 23
#define CLKID_MCLK0 24
#define CLKID_MCLK1_SEL 25
#define CLKID_MCLK1_SEL_EN 26
#define CLKID_MCLK1_DIV 27
#define CLKID_MCLK1 28
#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_C3_PLL_CLKC_H */

27
include/dt-bindings/clock/amlogic,c3-scmi-clkc.h Normal file
View File

@ -0,0 +1,27 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
/*
* Copyright (c) 2023 Amlogic, Inc. All rights reserved.
* Author: Chuan Liu <chuan.liu@amlogic.com>
*/
#ifndef __AMLOGIC_C3_SCMI_CLKC_H
#define __AMLOGIC_C3_SCMI_CLKC_H
#define CLKID_DDR_PLL_OSC 0
#define CLKID_DDR_PHY 1
#define CLKID_TOP_PLL_OSC 2
#define CLKID_USB_PLL_OSC 3
#define CLKID_MIPIISP_VOUT 4
#define CLKID_MCLK_PLL_OSC 5
#define CLKID_USB_CTRL 6
#define CLKID_ETH_PLL_OSC 7
#define CLKID_OSC 8
#define CLKID_SYS_CLK 9
#define CLKID_AXI_CLK 10
#define CLKID_CPU_CLK 11
#define CLKID_FIXED_PLL_OSC 12
#define CLKID_GP1_PLL_OSC 13
#define CLKID_SYS_PLL_DIV16 14
#define CLKID_CPU_CLK_DIV16 15
#endif /* __AMLOGIC_C3_SCMI_CLKC_H */

1
include/dt-bindings/clock/r8a7779-clock.h
View File

@ -57,5 +57,4 @@
#define R8A7779_CLK_MMC1 30
#define R8A7779_CLK_MMC0 31
#endif /* __DT_BINDINGS_CLOCK_R8A7779_H__ */

158
include/dt-bindings/clock/r8a7790-clock.h
View File

@ -1,158 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2013 Ideas On Board SPRL
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
#define __DT_BINDINGS_CLOCK_R8A7790_H__
/* CPG */
#define R8A7790_CLK_MAIN 0
#define R8A7790_CLK_PLL0 1
#define R8A7790_CLK_PLL1 2
#define R8A7790_CLK_PLL3 3
#define R8A7790_CLK_LB 4
#define R8A7790_CLK_QSPI 5
#define R8A7790_CLK_SDH 6
#define R8A7790_CLK_SD0 7
#define R8A7790_CLK_SD1 8
#define R8A7790_CLK_Z 9
#define R8A7790_CLK_RCAN 10
#define R8A7790_CLK_ADSP 11
/* MSTP0 */
#define R8A7790_CLK_MSIOF0 0
/* MSTP1 */
#define R8A7790_CLK_VCP1 0
#define R8A7790_CLK_VCP0 1
#define R8A7790_CLK_VPC1 2
#define R8A7790_CLK_VPC0 3
#define R8A7790_CLK_JPU 6
#define R8A7790_CLK_SSP1 9
#define R8A7790_CLK_TMU1 11
#define R8A7790_CLK_3DG 12
#define R8A7790_CLK_2DDMAC 15
#define R8A7790_CLK_FDP1_2 17
#define R8A7790_CLK_FDP1_1 18
#define R8A7790_CLK_FDP1_0 19
#define R8A7790_CLK_TMU3 21
#define R8A7790_CLK_TMU2 22
#define R8A7790_CLK_CMT0 24
#define R8A7790_CLK_TMU0 25
#define R8A7790_CLK_VSP1_DU1 27
#define R8A7790_CLK_VSP1_DU0 28
#define R8A7790_CLK_VSP1_R 30
#define R8A7790_CLK_VSP1_S 31
/* MSTP2 */
#define R8A7790_CLK_SCIFA2 2
#define R8A7790_CLK_SCIFA1 3
#define R8A7790_CLK_SCIFA0 4
#define R8A7790_CLK_MSIOF2 5
#define R8A7790_CLK_SCIFB0 6
#define R8A7790_CLK_SCIFB1 7
#define R8A7790_CLK_MSIOF1 8
#define R8A7790_CLK_MSIOF3 15
#define R8A7790_CLK_SCIFB2 16
#define R8A7790_CLK_SYS_DMAC1 18
#define R8A7790_CLK_SYS_DMAC0 19
/* MSTP3 */
#define R8A7790_CLK_IIC2 0
#define R8A7790_CLK_TPU0 4
#define R8A7790_CLK_MMCIF1 5
#define R8A7790_CLK_SCIF2 10
#define R8A7790_CLK_SDHI3 11
#define R8A7790_CLK_SDHI2 12
#define R8A7790_CLK_SDHI1 13
#define R8A7790_CLK_SDHI0 14
#define R8A7790_CLK_MMCIF0 15
#define R8A7790_CLK_IIC0 18
#define R8A7790_CLK_PCIEC 19
#define R8A7790_CLK_IIC1 23
#define R8A7790_CLK_SSUSB 28
#define R8A7790_CLK_CMT1 29
#define R8A7790_CLK_USBDMAC0 30
#define R8A7790_CLK_USBDMAC1 31
/* MSTP4 */
#define R8A7790_CLK_IRQC 7
#define R8A7790_CLK_INTC_SYS 8
/* MSTP5 */
#define R8A7790_CLK_AUDIO_DMAC1 1
#define R8A7790_CLK_AUDIO_DMAC0 2
#define R8A7790_CLK_ADSP_MOD 6
#define R8A7790_CLK_THERMAL 22
#define R8A7790_CLK_PWM 23
/* MSTP7 */
#define R8A7790_CLK_EHCI 3
#define R8A7790_CLK_HSUSB 4
#define R8A7790_CLK_HSCIF1 16
#define R8A7790_CLK_HSCIF0 17
#define R8A7790_CLK_SCIF1 20
#define R8A7790_CLK_SCIF0 21
#define R8A7790_CLK_DU2 22
#define R8A7790_CLK_DU1 23
#define R8A7790_CLK_DU0 24
#define R8A7790_CLK_LVDS1 25
#define R8A7790_CLK_LVDS0 26
/* MSTP8 */
#define R8A7790_CLK_MLB 2
#define R8A7790_CLK_VIN3 8
#define R8A7790_CLK_VIN2 9
#define R8A7790_CLK_VIN1 10
#define R8A7790_CLK_VIN0 11
#define R8A7790_CLK_ETHERAVB 12
#define R8A7790_CLK_ETHER 13
#define R8A7790_CLK_SATA1 14
#define R8A7790_CLK_SATA0 15
/* MSTP9 */
#define R8A7790_CLK_GPIO5 7
#define R8A7790_CLK_GPIO4 8
#define R8A7790_CLK_GPIO3 9
#define R8A7790_CLK_GPIO2 10
#define R8A7790_CLK_GPIO1 11
#define R8A7790_CLK_GPIO0 12
#define R8A7790_CLK_RCAN1 15
#define R8A7790_CLK_RCAN0 16
#define R8A7790_CLK_QSPI_MOD 17
#define R8A7790_CLK_IICDVFS 26
#define R8A7790_CLK_I2C3 28
#define R8A7790_CLK_I2C2 29
#define R8A7790_CLK_I2C1 30
#define R8A7790_CLK_I2C0 31
/* MSTP10 */
#define R8A7790_CLK_SSI_ALL 5
#define R8A7790_CLK_SSI9 6
#define R8A7790_CLK_SSI8 7
#define R8A7790_CLK_SSI7 8
#define R8A7790_CLK_SSI6 9
#define R8A7790_CLK_SSI5 10
#define R8A7790_CLK_SSI4 11
#define R8A7790_CLK_SSI3 12
#define R8A7790_CLK_SSI2 13
#define R8A7790_CLK_SSI1 14
#define R8A7790_CLK_SSI0 15
#define R8A7790_CLK_SCU_ALL 17
#define R8A7790_CLK_SCU_DVC1 18
#define R8A7790_CLK_SCU_DVC0 19
#define R8A7790_CLK_SCU_CTU1_MIX1 20
#define R8A7790_CLK_SCU_CTU0_MIX0 21
#define R8A7790_CLK_SCU_SRC9 22
#define R8A7790_CLK_SCU_SRC8 23
#define R8A7790_CLK_SCU_SRC7 24
#define R8A7790_CLK_SCU_SRC6 25
#define R8A7790_CLK_SCU_SRC5 26
#define R8A7790_CLK_SCU_SRC4 27
#define R8A7790_CLK_SCU_SRC3 28
#define R8A7790_CLK_SCU_SRC2 29
#define R8A7790_CLK_SCU_SRC1 30
#define R8A7790_CLK_SCU_SRC0 31
#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */

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include/dt-bindings/clock/r8a7791-clock.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright 2013 Ideas On Board SPRL
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
#define __DT_BINDINGS_CLOCK_R8A7791_H__
/* CPG */
#define R8A7791_CLK_MAIN 0
#define R8A7791_CLK_PLL0 1
#define R8A7791_CLK_PLL1 2
#define R8A7791_CLK_PLL3 3
#define R8A7791_CLK_LB 4
#define R8A7791_CLK_QSPI 5
#define R8A7791_CLK_SDH 6
#define R8A7791_CLK_SD0 7
#define R8A7791_CLK_Z 8
#define R8A7791_CLK_RCAN 9
#define R8A7791_CLK_ADSP 10
/* MSTP0 */
#define R8A7791_CLK_MSIOF0 0
/* MSTP1 */
#define R8A7791_CLK_VCP0 1
#define R8A7791_CLK_VPC0 3
#define R8A7791_CLK_JPU 6
#define R8A7791_CLK_SSP1 9
#define R8A7791_CLK_TMU1 11
#define R8A7791_CLK_3DG 12
#define R8A7791_CLK_2DDMAC 15
#define R8A7791_CLK_FDP1_1 18
#define R8A7791_CLK_FDP1_0 19
#define R8A7791_CLK_TMU3 21
#define R8A7791_CLK_TMU2 22
#define R8A7791_CLK_CMT0 24
#define R8A7791_CLK_TMU0 25
#define R8A7791_CLK_VSP1_DU1 27
#define R8A7791_CLK_VSP1_DU0 28
#define R8A7791_CLK_VSP1_S 31
/* MSTP2 */
#define R8A7791_CLK_SCIFA2 2
#define R8A7791_CLK_SCIFA1 3
#define R8A7791_CLK_SCIFA0 4
#define R8A7791_CLK_MSIOF2 5
#define R8A7791_CLK_SCIFB0 6
#define R8A7791_CLK_SCIFB1 7
#define R8A7791_CLK_MSIOF1 8
#define R8A7791_CLK_SCIFB2 16
#define R8A7791_CLK_SYS_DMAC1 18
#define R8A7791_CLK_SYS_DMAC0 19
/* MSTP3 */
#define R8A7791_CLK_TPU0 4
#define R8A7791_CLK_SDHI2 11
#define R8A7791_CLK_SDHI1 12
#define R8A7791_CLK_SDHI0 14
#define R8A7791_CLK_MMCIF0 15
#define R8A7791_CLK_IIC0 18
#define R8A7791_CLK_PCIEC 19
#define R8A7791_CLK_IIC1 23
#define R8A7791_CLK_SSUSB 28
#define R8A7791_CLK_CMT1 29
#define R8A7791_CLK_USBDMAC0 30
#define R8A7791_CLK_USBDMAC1 31
/* MSTP4 */
#define R8A7791_CLK_IRQC 7
#define R8A7791_CLK_INTC_SYS 8
/* MSTP5 */
#define R8A7791_CLK_AUDIO_DMAC1 1
#define R8A7791_CLK_AUDIO_DMAC0 2
#define R8A7791_CLK_ADSP_MOD 6
#define R8A7791_CLK_THERMAL 22
#define R8A7791_CLK_PWM 23
/* MSTP7 */
#define R8A7791_CLK_EHCI 3
#define R8A7791_CLK_HSUSB 4
#define R8A7791_CLK_HSCIF2 13
#define R8A7791_CLK_SCIF5 14
#define R8A7791_CLK_SCIF4 15
#define R8A7791_CLK_HSCIF1 16
#define R8A7791_CLK_HSCIF0 17
#define R8A7791_CLK_SCIF3 18
#define R8A7791_CLK_SCIF2 19
#define R8A7791_CLK_SCIF1 20
#define R8A7791_CLK_SCIF0 21
#define R8A7791_CLK_DU1 23
#define R8A7791_CLK_DU0 24
#define R8A7791_CLK_LVDS0 26
/* MSTP8 */
#define R8A7791_CLK_IPMMU_SGX 0
#define R8A7791_CLK_MLB 2
#define R8A7791_CLK_VIN2 9
#define R8A7791_CLK_VIN1 10
#define R8A7791_CLK_VIN0 11
#define R8A7791_CLK_ETHERAVB 12
#define R8A7791_CLK_ETHER 13
#define R8A7791_CLK_SATA1 14
#define R8A7791_CLK_SATA0 15
/* MSTP9 */
#define R8A7791_CLK_GYROADC 1
#define R8A7791_CLK_GPIO7 4
#define R8A7791_CLK_GPIO6 5
#define R8A7791_CLK_GPIO5 7
#define R8A7791_CLK_GPIO4 8
#define R8A7791_CLK_GPIO3 9
#define R8A7791_CLK_GPIO2 10
#define R8A7791_CLK_GPIO1 11
#define R8A7791_CLK_GPIO0 12
#define R8A7791_CLK_RCAN1 15
#define R8A7791_CLK_RCAN0 16
#define R8A7791_CLK_QSPI_MOD 17
#define R8A7791_CLK_I2C5 25
#define R8A7791_CLK_IICDVFS 26
#define R8A7791_CLK_I2C4 27
#define R8A7791_CLK_I2C3 28
#define R8A7791_CLK_I2C2 29
#define R8A7791_CLK_I2C1 30
#define R8A7791_CLK_I2C0 31
/* MSTP10 */
#define R8A7791_CLK_SSI_ALL 5
#define R8A7791_CLK_SSI9 6
#define R8A7791_CLK_SSI8 7
#define R8A7791_CLK_SSI7 8
#define R8A7791_CLK_SSI6 9
#define R8A7791_CLK_SSI5 10
#define R8A7791_CLK_SSI4 11
#define R8A7791_CLK_SSI3 12
#define R8A7791_CLK_SSI2 13
#define R8A7791_CLK_SSI1 14
#define R8A7791_CLK_SSI0 15
#define R8A7791_CLK_SCU_ALL 17
#define R8A7791_CLK_SCU_DVC1 18
#define R8A7791_CLK_SCU_DVC0 19
#define R8A7791_CLK_SCU_CTU1_MIX1 20
#define R8A7791_CLK_SCU_CTU0_MIX0 21
#define R8A7791_CLK_SCU_SRC9 22
#define R8A7791_CLK_SCU_SRC8 23
#define R8A7791_CLK_SCU_SRC7 24
#define R8A7791_CLK_SCU_SRC6 25
#define R8A7791_CLK_SCU_SRC5 26
#define R8A7791_CLK_SCU_SRC4 27
#define R8A7791_CLK_SCU_SRC3 28
#define R8A7791_CLK_SCU_SRC2 29
#define R8A7791_CLK_SCU_SRC1 30
#define R8A7791_CLK_SCU_SRC0 31
/* MSTP11 */
#define R8A7791_CLK_SCIFA3 6
#define R8A7791_CLK_SCIFA4 7
#define R8A7791_CLK_SCIFA5 8
#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */

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include/dt-bindings/clock/r8a7792-clock.h
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (C) 2016 Cogent Embedded, Inc.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__
#define __DT_BINDINGS_CLOCK_R8A7792_H__
/* CPG */
#define R8A7792_CLK_MAIN 0
#define R8A7792_CLK_PLL0 1
#define R8A7792_CLK_PLL1 2
#define R8A7792_CLK_PLL3 3
#define R8A7792_CLK_LB 4
#define R8A7792_CLK_QSPI 5
/* MSTP0 */
#define R8A7792_CLK_MSIOF0 0
/* MSTP1 */
#define R8A7792_CLK_JPU 6
#define R8A7792_CLK_TMU1 11
#define R8A7792_CLK_TMU3 21
#define R8A7792_CLK_TMU2 22
#define R8A7792_CLK_CMT0 24
#define R8A7792_CLK_TMU0 25
#define R8A7792_CLK_VSP1DU1 27
#define R8A7792_CLK_VSP1DU0 28
#define R8A7792_CLK_VSP1_SY 31
/* MSTP2 */
#define R8A7792_CLK_MSIOF1 8
#define R8A7792_CLK_SYS_DMAC1 18
#define R8A7792_CLK_SYS_DMAC0 19
/* MSTP3 */
#define R8A7792_CLK_TPU0 4
#define R8A7792_CLK_SDHI0 14
#define R8A7792_CLK_CMT1 29
/* MSTP4 */
#define R8A7792_CLK_IRQC 7
#define R8A7792_CLK_INTC_SYS 8
/* MSTP5 */
#define R8A7792_CLK_AUDIO_DMAC0 2
#define R8A7792_CLK_THERMAL 22
#define R8A7792_CLK_PWM 23
/* MSTP7 */
#define R8A7792_CLK_HSCIF1 16
#define R8A7792_CLK_HSCIF0 17
#define R8A7792_CLK_SCIF3 18
#define R8A7792_CLK_SCIF2 19
#define R8A7792_CLK_SCIF1 20
#define R8A7792_CLK_SCIF0 21
#define R8A7792_CLK_DU1 23
#define R8A7792_CLK_DU0 24
/* MSTP8 */
#define R8A7792_CLK_VIN5 4
#define R8A7792_CLK_VIN4 5
#define R8A7792_CLK_VIN3 8
#define R8A7792_CLK_VIN2 9
#define R8A7792_CLK_VIN1 10
#define R8A7792_CLK_VIN0 11
#define R8A7792_CLK_ETHERAVB 12
/* MSTP9 */
#define R8A7792_CLK_GPIO7 4
#define R8A7792_CLK_GPIO6 5
#define R8A7792_CLK_GPIO5 7
#define R8A7792_CLK_GPIO4 8
#define R8A7792_CLK_GPIO3 9
#define R8A7792_CLK_GPIO2 10
#define R8A7792_CLK_GPIO1 11
#define R8A7792_CLK_GPIO0 12
#define R8A7792_CLK_GPIO11 13
#define R8A7792_CLK_GPIO10 14
#define R8A7792_CLK_CAN1 15
#define R8A7792_CLK_CAN0 16
#define R8A7792_CLK_QSPI_MOD 17
#define R8A7792_CLK_GPIO9 19
#define R8A7792_CLK_GPIO8 21
#define R8A7792_CLK_I2C5 25
#define R8A7792_CLK_IICDVFS 26
#define R8A7792_CLK_I2C4 27
#define R8A7792_CLK_I2C3 28
#define R8A7792_CLK_I2C2 29
#define R8A7792_CLK_I2C1 30
#define R8A7792_CLK_I2C0 31
/* MSTP10 */
#define R8A7792_CLK_SSI_ALL 5
#define R8A7792_CLK_SSI4 11
#define R8A7792_CLK_SSI3 12
#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */

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include/dt-bindings/clock/r8a7793-clock.h
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/* SPDX-License-Identifier: GPL-2.0
*
* r8a7793 clock definition
*
* Copyright (C) 2014 Renesas Electronics Corporation
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__
#define __DT_BINDINGS_CLOCK_R8A7793_H__
/* CPG */
#define R8A7793_CLK_MAIN 0
#define R8A7793_CLK_PLL0 1
#define R8A7793_CLK_PLL1 2
#define R8A7793_CLK_PLL3 3
#define R8A7793_CLK_LB 4
#define R8A7793_CLK_QSPI 5
#define R8A7793_CLK_SDH 6
#define R8A7793_CLK_SD0 7
#define R8A7793_CLK_Z 8
#define R8A7793_CLK_RCAN 9
#define R8A7793_CLK_ADSP 10
/* MSTP0 */
#define R8A7793_CLK_MSIOF0 0
/* MSTP1 */
#define R8A7793_CLK_VCP0 1
#define R8A7793_CLK_VPC0 3
#define R8A7793_CLK_SSP1 9
#define R8A7793_CLK_TMU1 11
#define R8A7793_CLK_3DG 12
#define R8A7793_CLK_2DDMAC 15
#define R8A7793_CLK_FDP1_1 18
#define R8A7793_CLK_FDP1_0 19
#define R8A7793_CLK_TMU3 21
#define R8A7793_CLK_TMU2 22
#define R8A7793_CLK_CMT0 24
#define R8A7793_CLK_TMU0 25
#define R8A7793_CLK_VSP1_DU1 27
#define R8A7793_CLK_VSP1_DU0 28
#define R8A7793_CLK_VSP1_S 31
/* MSTP2 */
#define R8A7793_CLK_SCIFA2 2
#define R8A7793_CLK_SCIFA1 3
#define R8A7793_CLK_SCIFA0 4
#define R8A7793_CLK_MSIOF2 5
#define R8A7793_CLK_SCIFB0 6
#define R8A7793_CLK_SCIFB1 7
#define R8A7793_CLK_MSIOF1 8
#define R8A7793_CLK_SCIFB2 16
#define R8A7793_CLK_SYS_DMAC1 18
#define R8A7793_CLK_SYS_DMAC0 19
/* MSTP3 */
#define R8A7793_CLK_TPU0 4
#define R8A7793_CLK_SDHI2 11
#define R8A7793_CLK_SDHI1 12
#define R8A7793_CLK_SDHI0 14
#define R8A7793_CLK_MMCIF0 15
#define R8A7793_CLK_IIC0 18
#define R8A7793_CLK_PCIEC 19
#define R8A7793_CLK_IIC1 23
#define R8A7793_CLK_SSUSB 28
#define R8A7793_CLK_CMT1 29
#define R8A7793_CLK_USBDMAC0 30
#define R8A7793_CLK_USBDMAC1 31
/* MSTP4 */
#define R8A7793_CLK_IRQC 7
#define R8A7793_CLK_INTC_SYS 8
/* MSTP5 */
#define R8A7793_CLK_AUDIO_DMAC1 1
#define R8A7793_CLK_AUDIO_DMAC0 2
#define R8A7793_CLK_ADSP_MOD 6
#define R8A7793_CLK_THERMAL 22
#define R8A7793_CLK_PWM 23
/* MSTP7 */
#define R8A7793_CLK_EHCI 3
#define R8A7793_CLK_HSUSB 4
#define R8A7793_CLK_HSCIF2 13
#define R8A7793_CLK_SCIF5 14
#define R8A7793_CLK_SCIF4 15
#define R8A7793_CLK_HSCIF1 16
#define R8A7793_CLK_HSCIF0 17
#define R8A7793_CLK_SCIF3 18
#define R8A7793_CLK_SCIF2 19
#define R8A7793_CLK_SCIF1 20
#define R8A7793_CLK_SCIF0 21
#define R8A7793_CLK_DU1 23
#define R8A7793_CLK_DU0 24
#define R8A7793_CLK_LVDS0 26
/* MSTP8 */
#define R8A7793_CLK_IPMMU_SGX 0
#define R8A7793_CLK_VIN2 9
#define R8A7793_CLK_VIN1 10
#define R8A7793_CLK_VIN0 11
#define R8A7793_CLK_ETHER 13
#define R8A7793_CLK_SATA1 14
#define R8A7793_CLK_SATA0 15
/* MSTP9 */
#define R8A7793_CLK_GPIO7 4
#define R8A7793_CLK_GPIO6 5
#define R8A7793_CLK_GPIO5 7
#define R8A7793_CLK_GPIO4 8
#define R8A7793_CLK_GPIO3 9
#define R8A7793_CLK_GPIO2 10
#define R8A7793_CLK_GPIO1 11
#define R8A7793_CLK_GPIO0 12
#define R8A7793_CLK_RCAN1 15
#define R8A7793_CLK_RCAN0 16
#define R8A7793_CLK_QSPI_MOD 17
#define R8A7793_CLK_I2C5 25
#define R8A7793_CLK_IICDVFS 26
#define R8A7793_CLK_I2C4 27
#define R8A7793_CLK_I2C3 28
#define R8A7793_CLK_I2C2 29
#define R8A7793_CLK_I2C1 30
#define R8A7793_CLK_I2C0 31
/* MSTP10 */
#define R8A7793_CLK_SSI_ALL 5
#define R8A7793_CLK_SSI9 6
#define R8A7793_CLK_SSI8 7
#define R8A7793_CLK_SSI7 8
#define R8A7793_CLK_SSI6 9
#define R8A7793_CLK_SSI5 10
#define R8A7793_CLK_SSI4 11
#define R8A7793_CLK_SSI3 12
#define R8A7793_CLK_SSI2 13
#define R8A7793_CLK_SSI1 14
#define R8A7793_CLK_SSI0 15
#define R8A7793_CLK_SCU_ALL 17
#define R8A7793_CLK_SCU_DVC1 18
#define R8A7793_CLK_SCU_DVC0 19
#define R8A7793_CLK_SCU_CTU1_MIX1 20
#define R8A7793_CLK_SCU_CTU0_MIX0 21
#define R8A7793_CLK_SCU_SRC9 22
#define R8A7793_CLK_SCU_SRC8 23
#define R8A7793_CLK_SCU_SRC7 24
#define R8A7793_CLK_SCU_SRC6 25
#define R8A7793_CLK_SCU_SRC5 26
#define R8A7793_CLK_SCU_SRC4 27
#define R8A7793_CLK_SCU_SRC3 28
#define R8A7793_CLK_SCU_SRC2 29
#define R8A7793_CLK_SCU_SRC1 30
#define R8A7793_CLK_SCU_SRC0 31
/* MSTP11 */
#define R8A7793_CLK_SCIFA3 6
#define R8A7793_CLK_SCIFA4 7
#define R8A7793_CLK_SCIFA5 8
#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */

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include/dt-bindings/clock/r8a7794-clock.h
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/* SPDX-License-Identifier: GPL-2.0+
*
* Copyright (C) 2014 Renesas Electronics Corporation
* Copyright 2013 Ideas On Board SPRL
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7794_H__
#define __DT_BINDINGS_CLOCK_R8A7794_H__
/* CPG */
#define R8A7794_CLK_MAIN 0
#define R8A7794_CLK_PLL0 1
#define R8A7794_CLK_PLL1 2
#define R8A7794_CLK_PLL3 3
#define R8A7794_CLK_LB 4
#define R8A7794_CLK_QSPI 5
#define R8A7794_CLK_SDH 6
#define R8A7794_CLK_SD0 7
#define R8A7794_CLK_RCAN 8
/* MSTP0 */
#define R8A7794_CLK_MSIOF0 0
/* MSTP1 */
#define R8A7794_CLK_VCP0 1
#define R8A7794_CLK_VPC0 3
#define R8A7794_CLK_TMU1 11
#define R8A7794_CLK_3DG 12
#define R8A7794_CLK_2DDMAC 15
#define R8A7794_CLK_FDP1_0 19
#define R8A7794_CLK_TMU3 21
#define R8A7794_CLK_TMU2 22
#define R8A7794_CLK_CMT0 24
#define R8A7794_CLK_TMU0 25
#define R8A7794_CLK_VSP1_DU0 28
#define R8A7794_CLK_VSP1_S 31
/* MSTP2 */
#define R8A7794_CLK_SCIFA2 2
#define R8A7794_CLK_SCIFA1 3
#define R8A7794_CLK_SCIFA0 4
#define R8A7794_CLK_MSIOF2 5
#define R8A7794_CLK_SCIFB0 6
#define R8A7794_CLK_SCIFB1 7
#define R8A7794_CLK_MSIOF1 8
#define R8A7794_CLK_SCIFB2 16
#define R8A7794_CLK_SYS_DMAC1 18
#define R8A7794_CLK_SYS_DMAC0 19
/* MSTP3 */
#define R8A7794_CLK_SDHI2 11
#define R8A7794_CLK_SDHI1 12
#define R8A7794_CLK_SDHI0 14
#define R8A7794_CLK_MMCIF0 15
#define R8A7794_CLK_IIC0 18
#define R8A7794_CLK_IIC1 23
#define R8A7794_CLK_CMT1 29
#define R8A7794_CLK_USBDMAC0 30
#define R8A7794_CLK_USBDMAC1 31
/* MSTP4 */
#define R8A7794_CLK_IRQC 7
#define R8A7794_CLK_INTC_SYS 8
/* MSTP5 */
#define R8A7794_CLK_AUDIO_DMAC0 2
#define R8A7794_CLK_PWM 23
/* MSTP7 */
#define R8A7794_CLK_EHCI 3
#define R8A7794_CLK_HSUSB 4
#define R8A7794_CLK_HSCIF2 13
#define R8A7794_CLK_SCIF5 14
#define R8A7794_CLK_SCIF4 15
#define R8A7794_CLK_HSCIF1 16
#define R8A7794_CLK_HSCIF0 17
#define R8A7794_CLK_SCIF3 18
#define R8A7794_CLK_SCIF2 19
#define R8A7794_CLK_SCIF1 20
#define R8A7794_CLK_SCIF0 21
#define R8A7794_CLK_DU1 23
#define R8A7794_CLK_DU0 24
/* MSTP8 */
#define R8A7794_CLK_VIN1 10
#define R8A7794_CLK_VIN0 11
#define R8A7794_CLK_ETHERAVB 12
#define R8A7794_CLK_ETHER 13
/* MSTP9 */
#define R8A7794_CLK_GPIO6 5
#define R8A7794_CLK_GPIO5 7
#define R8A7794_CLK_GPIO4 8
#define R8A7794_CLK_GPIO3 9
#define R8A7794_CLK_GPIO2 10
#define R8A7794_CLK_GPIO1 11
#define R8A7794_CLK_GPIO0 12
#define R8A7794_CLK_RCAN1 15
#define R8A7794_CLK_RCAN0 16
#define R8A7794_CLK_QSPI_MOD 17
#define R8A7794_CLK_I2C5 25
#define R8A7794_CLK_I2C4 27
#define R8A7794_CLK_I2C3 28
#define R8A7794_CLK_I2C2 29
#define R8A7794_CLK_I2C1 30
#define R8A7794_CLK_I2C0 31
/* MSTP10 */
#define R8A7794_CLK_SSI_ALL 5
#define R8A7794_CLK_SSI9 6
#define R8A7794_CLK_SSI8 7
#define R8A7794_CLK_SSI7 8
#define R8A7794_CLK_SSI6 9
#define R8A7794_CLK_SSI5 10
#define R8A7794_CLK_SSI4 11
#define R8A7794_CLK_SSI3 12
#define R8A7794_CLK_SSI2 13
#define R8A7794_CLK_SSI1 14
#define R8A7794_CLK_SSI0 15
#define R8A7794_CLK_SCU_ALL 17
#define R8A7794_CLK_SCU_DVC1 18
#define R8A7794_CLK_SCU_DVC0 19
#define R8A7794_CLK_SCU_CTU1_MIX1 20
#define R8A7794_CLK_SCU_CTU0_MIX0 21
#define R8A7794_CLK_SCU_SRC6 25
#define R8A7794_CLK_SCU_SRC5 26
#define R8A7794_CLK_SCU_SRC4 27
#define R8A7794_CLK_SCU_SRC3 28
#define R8A7794_CLK_SCU_SRC2 29
#define R8A7794_CLK_SCU_SRC1 30
/* MSTP11 */
#define R8A7794_CLK_SCIFA3 6
#define R8A7794_CLK_SCIFA4 7
#define R8A7794_CLK_SCIFA5 8
#endif /* __DT_BINDINGS_CLOCK_R8A7794_H__ */

1
include/dt-bindings/clock/sun50i-h616-ccu.h
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@ -112,5 +112,6 @@
#define CLK_HDCP 126
#define CLK_BUS_HDCP 127
#define CLK_PLL_SYSTEM_32K 128
#define CLK_BUS_GPADC 129
#endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */

1
include/dt-bindings/reset/sun50i-h616-ccu.h
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@ -66,5 +66,6 @@
#define RST_BUS_TVE0 57
#define RST_BUS_HDCP 58
#define RST_BUS_KEYADC 59
#define RST_BUS_GPADC 60
#endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */