Kernel/linux-next
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git synced 2025-01-17 13:58:46 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

ASoC: arizona: Update handling for input change on an active FLL

Browse Source 
Currently, the driver places no restrictions on changes that can be
applied to an active FLL. However, it is only possible to change the
input for an active FLL, to change the output the FLL should be stopped
and then recofigured. This patch disallows changes in output frequency
and adds some additional handling to ensure the output remains
consistent across an input transition.

Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
This commit is contained in:
Charles Keepax 2014-07-09 17:41:49 +01:00 committed by Mark Brown
parent 5e39a50bf8
commit c8badda8ee
1 changed files with 19 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
sound/soc/codecs/arizona.c
View File

@ -1500,6 +1500,12 @@ static int arizona_validate_fll(struct arizona_fll *fll,
{
unsigned int Fvco_min;
if (fll->fout && Fout != fll->fout) {
arizona_fll_err(fll,
"Can't change output on active FLL\n");
return -EINVAL;
}
if (Fref / ARIZONA_FLL_MAX_REFDIV > ARIZONA_FLL_MAX_FREF) {
arizona_fll_err(fll,
"Can't scale %dMHz in to <=13.5MHz\n",
@ -1743,6 +1749,15 @@ static int arizona_enable_fll(struct arizona_fll *fll)
if (already_enabled < 0)
return already_enabled;
if (already_enabled) {
/* Facilitate smooth refclk across the transition */
regmap_update_bits_async(fll->arizona->regmap, fll->base + 0x7,
ARIZONA_FLL1_GAIN_MASK, 0);
regmap_update_bits_async(fll->arizona->regmap, fll->base + 1,
ARIZONA_FLL1_FREERUN,
ARIZONA_FLL1_FREERUN);
}
/*
* If we have both REFCLK and SYNCCLK then enable both,
* otherwise apply the SYNCCLK settings to REFCLK.
@ -1798,6 +1813,10 @@ static int arizona_enable_fll(struct arizona_fll *fll)
ARIZONA_FLL1_SYNC_ENA,
ARIZONA_FLL1_SYNC_ENA);
if (already_enabled)
regmap_update_bits_async(arizona->regmap, fll->base + 1,
ARIZONA_FLL1_FREERUN, 0);
ret = wait_for_completion_timeout(&fll->ok,
msecs_to_jiffies(250));
if (ret == 0)