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net: stmmac: dwmac-s32: add basic NXP S32G/S32R glue driver
NXP S32G2xx/S32G3xx and S32R45 are automotive grade SoCs that integrate one or two Synopsys DWMAC 5.10/5.20 IPs. The basic driver supports only RGMII interface. Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com> Link: https://patch.msgid.link/20241205-upstream_s32cc_gmac-v8-14-ec1d180df815@oss.nxp.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jan Petrous (OSS)
Jakub Kicinski
parent
91f10e5895
commit
cd197ac5d6
@ -154,6 +154,18 @@ config DWMAC_RZN1
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the stmmac device driver. This support can make use of a custom MII
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converter PCS device.
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config DWMAC_S32
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tristate "NXP S32G/S32R GMAC support"
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default ARCH_S32
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depends on OF && (ARCH_S32 || COMPILE_TEST)
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help
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Support for ethernet controller on NXP S32CC SOCs.
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This selects NXP SoC glue layer support for the stmmac
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device driver. This driver is used for the S32CC series
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SOCs GMAC ethernet controller, ie. S32G2xx, S32G3xx and
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S32R45.
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config DWMAC_SOCFPGA
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tristate "SOCFPGA dwmac support"
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default ARCH_INTEL_SOCFPGA
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@ -22,6 +22,7 @@ obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o
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obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-ethqos.o
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obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o
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obj-$(CONFIG_DWMAC_RZN1) += dwmac-rzn1.o
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obj-$(CONFIG_DWMAC_S32) += dwmac-s32.o
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obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o
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obj-$(CONFIG_DWMAC_STARFIVE) += dwmac-starfive.o
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obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o
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202
drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
Normal file
202
drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
Normal file
@ -0,0 +1,202 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* NXP S32G/R GMAC glue layer
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*
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* Copyright 2019-2024 NXP
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*
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/ethtool.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_mdio.h>
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#include <linux/of_address.h>
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#include <linux/phy.h>
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#include <linux/phylink.h>
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#include <linux/platform_device.h>
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#include <linux/stmmac.h>
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#include "stmmac_platform.h"
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#define GMAC_INTF_RATE_125M 125000000 /* 125MHz */
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/* SoC PHY interface control register */
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#define PHY_INTF_SEL_MII 0x00
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#define PHY_INTF_SEL_SGMII 0x01
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#define PHY_INTF_SEL_RGMII 0x02
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#define PHY_INTF_SEL_RMII 0x08
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struct s32_priv_data {
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void __iomem *ioaddr;
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void __iomem *ctrl_sts;
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struct device *dev;
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phy_interface_t *intf_mode;
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struct clk *tx_clk;
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struct clk *rx_clk;
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};
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static int s32_gmac_write_phy_intf_select(struct s32_priv_data *gmac)
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{
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writel(PHY_INTF_SEL_RGMII, gmac->ctrl_sts);
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dev_dbg(gmac->dev, "PHY mode set to %s\n", phy_modes(*gmac->intf_mode));
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return 0;
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}
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static int s32_gmac_init(struct platform_device *pdev, void *priv)
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{
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struct s32_priv_data *gmac = priv;
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int ret;
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/* Set initial TX interface clock */
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ret = clk_prepare_enable(gmac->tx_clk);
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if (ret) {
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dev_err(&pdev->dev, "Can't enable tx clock\n");
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return ret;
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}
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ret = clk_set_rate(gmac->tx_clk, GMAC_INTF_RATE_125M);
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if (ret) {
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dev_err(&pdev->dev, "Can't set tx clock\n");
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goto err_tx_disable;
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}
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/* Set initial RX interface clock */
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ret = clk_prepare_enable(gmac->rx_clk);
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if (ret) {
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dev_err(&pdev->dev, "Can't enable rx clock\n");
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goto err_tx_disable;
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}
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ret = clk_set_rate(gmac->rx_clk, GMAC_INTF_RATE_125M);
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if (ret) {
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dev_err(&pdev->dev, "Can't set rx clock\n");
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goto err_txrx_disable;
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}
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/* Set interface mode */
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ret = s32_gmac_write_phy_intf_select(gmac);
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if (ret) {
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dev_err(&pdev->dev, "Can't set PHY interface mode\n");
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goto err_txrx_disable;
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}
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return 0;
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err_txrx_disable:
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clk_disable_unprepare(gmac->rx_clk);
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err_tx_disable:
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clk_disable_unprepare(gmac->tx_clk);
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return ret;
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}
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static void s32_gmac_exit(struct platform_device *pdev, void *priv)
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{
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struct s32_priv_data *gmac = priv;
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clk_disable_unprepare(gmac->tx_clk);
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clk_disable_unprepare(gmac->rx_clk);
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}
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static void s32_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode)
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{
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struct s32_priv_data *gmac = priv;
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long tx_clk_rate;
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int ret;
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tx_clk_rate = rgmii_clock(speed);
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if (tx_clk_rate < 0) {
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dev_err(gmac->dev, "Unsupported/Invalid speed: %d\n", speed);
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return;
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}
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dev_dbg(gmac->dev, "Set tx clock to %ld Hz\n", tx_clk_rate);
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ret = clk_set_rate(gmac->tx_clk, tx_clk_rate);
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if (ret)
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dev_err(gmac->dev, "Can't set tx clock\n");
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}
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static int s32_dwmac_probe(struct platform_device *pdev)
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{
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struct plat_stmmacenet_data *plat;
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struct device *dev = &pdev->dev;
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struct stmmac_resources res;
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struct s32_priv_data *gmac;
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int ret;
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gmac = devm_kzalloc(&pdev->dev, sizeof(*gmac), GFP_KERNEL);
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if (!gmac)
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return -ENOMEM;
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gmac->dev = &pdev->dev;
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ret = stmmac_get_platform_resources(pdev, &res);
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if (ret)
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return dev_err_probe(dev, ret,
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"Failed to get platform resources\n");
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plat = devm_stmmac_probe_config_dt(pdev, res.mac);
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if (IS_ERR(plat))
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return dev_err_probe(dev, PTR_ERR(plat),
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"dt configuration failed\n");
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/* PHY interface mode control reg */
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gmac->ctrl_sts = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
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if (IS_ERR(gmac->ctrl_sts))
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return dev_err_probe(dev, PTR_ERR(gmac->ctrl_sts),
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"S32CC config region is missing\n");
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/* tx clock */
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gmac->tx_clk = devm_clk_get(&pdev->dev, "tx");
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if (IS_ERR(gmac->tx_clk))
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return dev_err_probe(dev, PTR_ERR(gmac->tx_clk),
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"tx clock not found\n");
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/* rx clock */
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gmac->rx_clk = devm_clk_get(&pdev->dev, "rx");
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if (IS_ERR(gmac->rx_clk))
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return dev_err_probe(dev, PTR_ERR(gmac->rx_clk),
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"rx clock not found\n");
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gmac->intf_mode = &plat->phy_interface;
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gmac->ioaddr = res.addr;
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/* S32CC core feature set */
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plat->has_gmac4 = true;
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plat->pmt = 1;
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plat->flags |= STMMAC_FLAG_SPH_DISABLE;
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plat->rx_fifo_size = 20480;
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plat->tx_fifo_size = 20480;
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plat->init = s32_gmac_init;
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plat->exit = s32_gmac_exit;
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plat->fix_mac_speed = s32_fix_mac_speed;
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plat->bsp_priv = gmac;
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return stmmac_pltfr_probe(pdev, plat, &res);
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}
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static const struct of_device_id s32_dwmac_match[] = {
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{ .compatible = "nxp,s32g2-dwmac" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, s32_dwmac_match);
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static struct platform_driver s32_dwmac_driver = {
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.probe = s32_dwmac_probe,
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.remove = stmmac_pltfr_remove,
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.driver = {
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.name = "s32-dwmac",
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.pm = &stmmac_pltfr_pm_ops,
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.of_match_table = s32_dwmac_match,
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},
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};
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module_platform_driver(s32_dwmac_driver);
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MODULE_AUTHOR("Jan Petrous (OSS) <jan.petrous@oss.nxp.com>");
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MODULE_DESCRIPTION("NXP S32G/R common chassis GMAC driver");
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MODULE_LICENSE("GPL");
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