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irqchip/gic(v3): Replace gic_irq() with irqd_to_hwirq()
GIC & GIC-v3 share same gic_irq() implementations, both of which serve exact same purpose as irqd_to_hwirq(). irqd_to_hwirq() is a generic and top level API of the interrupt subsystem, it's independent of any chip implementation. Replace gic_irq() with irqd_to_hwirq() and convert struct irq_data::hwirq to irq_hw_number_t explicitly. Suggested-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Dawei Li <dawei.li@shingroup.cn> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Link: https://lore.kernel.org/r/20240122085716.2999875-3-dawei.li@shingroup.cn
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@ -181,11 +181,6 @@ static enum gic_intid_range get_intid_range(struct irq_data *d)
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return __get_intid_range(d->hwirq);
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}
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static inline unsigned int gic_irq(struct irq_data *d)
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{
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return d->hwirq;
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}
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static inline bool gic_irq_in_rdist(struct irq_data *d)
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{
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switch (get_intid_range(d)) {
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@ -542,7 +537,7 @@ static int gic_irq_nmi_setup(struct irq_data *d)
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* A secondary irq_chip should be in charge of LPI request,
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* it should not be possible to get there
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*/
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if (WARN_ON(gic_irq(d) >= 8192))
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if (WARN_ON(irqd_to_hwirq(d) >= 8192))
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return -EINVAL;
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/* desc lock should already be held */
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@ -582,7 +577,7 @@ static void gic_irq_nmi_teardown(struct irq_data *d)
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* A secondary irq_chip should be in charge of LPI request,
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* it should not be possible to get there
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*/
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if (WARN_ON(gic_irq(d) >= 8192))
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if (WARN_ON(irqd_to_hwirq(d) >= 8192))
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return;
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/* desc lock should already be held */
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@ -620,7 +615,7 @@ static bool gic_arm64_erratum_2941627_needed(struct irq_data *d)
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static void gic_eoi_irq(struct irq_data *d)
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{
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write_gicreg(gic_irq(d), ICC_EOIR1_EL1);
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write_gicreg(irqd_to_hwirq(d), ICC_EOIR1_EL1);
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isb();
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if (gic_arm64_erratum_2941627_needed(d)) {
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@ -640,19 +635,19 @@ static void gic_eoimode1_eoi_irq(struct irq_data *d)
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* No need to deactivate an LPI, or an interrupt that
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* is is getting forwarded to a vcpu.
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*/
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if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
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if (irqd_to_hwirq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d))
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return;
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if (!gic_arm64_erratum_2941627_needed(d))
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gic_write_dir(gic_irq(d));
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gic_write_dir(irqd_to_hwirq(d));
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else
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gic_poke_irq(d, GICD_ICACTIVER);
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}
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static int gic_set_type(struct irq_data *d, unsigned int type)
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{
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irq_hw_number_t irq = irqd_to_hwirq(d);
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enum gic_intid_range range;
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unsigned int irq = gic_irq(d);
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void __iomem *base;
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u32 offset, index;
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int ret;
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@ -678,7 +673,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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ret = gic_configure_irq(index, type, base + offset, NULL);
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if (ret && (range == PPI_RANGE || range == EPPI_RANGE)) {
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/* Misconfigured PPIs are usually not fatal */
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pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq);
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pr_warn("GIC: PPI INTID%ld is secure or misconfigured\n", irq);
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ret = 0;
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}
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@ -162,11 +162,6 @@ static inline void __iomem *gic_cpu_base(struct irq_data *d)
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return gic_data_cpu_base(gic_data);
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}
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static inline unsigned int gic_irq(struct irq_data *d)
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{
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return d->hwirq;
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}
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static inline bool cascading_gic_irq(struct irq_data *d)
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{
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void *data = irq_data_get_irq_handler_data(d);
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@ -183,14 +178,16 @@ static inline bool cascading_gic_irq(struct irq_data *d)
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*/
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static void gic_poke_irq(struct irq_data *d, u32 offset)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
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u32 mask = 1 << (irqd_to_hwirq(d) % 32);
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writel_relaxed(mask, gic_dist_base(d) + offset + (irqd_to_hwirq(d) / 32) * 4);
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}
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static int gic_peek_irq(struct irq_data *d, u32 offset)
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{
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u32 mask = 1 << (gic_irq(d) % 32);
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return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
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u32 mask = 1 << (irqd_to_hwirq(d) % 32);
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return !!(readl_relaxed(gic_dist_base(d) + offset + (irqd_to_hwirq(d) / 32) * 4) & mask);
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}
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static void gic_mask_irq(struct irq_data *d)
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@ -220,7 +217,7 @@ static void gic_unmask_irq(struct irq_data *d)
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static void gic_eoi_irq(struct irq_data *d)
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{
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u32 hwirq = gic_irq(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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if (hwirq < 16)
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hwirq = this_cpu_read(sgi_intid);
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@ -230,7 +227,7 @@ static void gic_eoi_irq(struct irq_data *d)
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static void gic_eoimode1_eoi_irq(struct irq_data *d)
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{
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u32 hwirq = gic_irq(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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/* Do not deactivate an IRQ forwarded to a vcpu. */
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if (irqd_is_forwarded_to_vcpu(d))
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@ -293,8 +290,8 @@ static int gic_irq_get_irqchip_state(struct irq_data *d,
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static int gic_set_type(struct irq_data *d, unsigned int type)
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{
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irq_hw_number_t gicirq = irqd_to_hwirq(d);
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void __iomem *base = gic_dist_base(d);
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unsigned int gicirq = gic_irq(d);
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int ret;
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/* Interrupt configuration for SGIs can't be changed */
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@ -309,7 +306,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL);
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if (ret && gicirq < 32) {
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/* Misconfigured PPIs are usually not fatal */
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pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16);
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pr_warn("GIC: PPI%ld is secure or misconfigured\n", gicirq - 16);
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ret = 0;
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}
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@ -319,7 +316,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
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static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
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{
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/* Only interrupts on the primary GIC can be forwarded to a vcpu. */
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if (cascading_gic_irq(d) || gic_irq(d) < 16)
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if (cascading_gic_irq(d) || irqd_to_hwirq(d) < 16)
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return -EINVAL;
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if (vcpu)
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@ -796,7 +793,7 @@ static void rmw_writeb(u8 bval, void __iomem *addr)
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static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
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bool force)
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{
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void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
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void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + irqd_to_hwirq(d);
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struct gic_chip_data *gic = irq_data_get_irq_chip_data(d);
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unsigned int cpu;
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@ -179,7 +179,7 @@ struct irq_common_data {
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struct irq_data {
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u32 mask;
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unsigned int irq;
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unsigned long hwirq;
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irq_hw_number_t hwirq;
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struct irq_common_data *common;
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struct irq_chip *chip;
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struct irq_domain *domain;
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