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pinctrl: renesas: r8a779a0: Share QSPI pin group data

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Pin groups qspi[01]_data2 are subsets of qspi[01]_data4.

This reduces kernel size by 32 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/bba05f9ac803ecd55c6c480fa139fa1a0d268d78.1640269757.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven 2021-12-23 15:41:46 +01:00
parent 7caf7b3a8f
commit d67194a5e8
1 changed files with 8 additions and 22 deletions
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30
drivers/pinctrl/renesas/pfc-r8a779a0.c
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@ -2368,19 +2368,12 @@ static const unsigned int qspi0_ctrl_pins[] = {
static const unsigned int qspi0_ctrl_mux[] = { static const unsigned int qspi0_ctrl_mux[] = {
QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
}; };
static const unsigned int qspi0_data2_pins[] = { static const unsigned int qspi0_data_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
};
static const unsigned int qspi0_data2_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
};
static const unsigned int qspi0_data4_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
}; };
static const unsigned int qspi0_data4_mux[] = { static const unsigned int qspi0_data_mux[] = {
QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
QSPI0_IO2_MARK, QSPI0_IO3_MARK QSPI0_IO2_MARK, QSPI0_IO3_MARK
}; };
@ -2393,19 +2386,12 @@ static const unsigned int qspi1_ctrl_pins[] = {
static const unsigned int qspi1_ctrl_mux[] = { static const unsigned int qspi1_ctrl_mux[] = {
QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
}; };
static const unsigned int qspi1_data2_pins[] = { static const unsigned int qspi1_data_pins[] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
};
static const unsigned int qspi1_data2_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
};
static const unsigned int qspi1_data4_pins[] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */ /* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
}; };
static const unsigned int qspi1_data4_mux[] = { static const unsigned int qspi1_data_mux[] = {
QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
QSPI1_IO2_MARK, QSPI1_IO3_MARK QSPI1_IO2_MARK, QSPI1_IO3_MARK
}; };
@ -2751,11 +2737,11 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(pwm4), SH_PFC_PIN_GROUP(pwm4),
SH_PFC_PIN_GROUP(qspi0_ctrl), SH_PFC_PIN_GROUP(qspi0_ctrl),
SH_PFC_PIN_GROUP(qspi0_data2), BUS_DATA_PIN_GROUP(qspi0_data, 2),
SH_PFC_PIN_GROUP(qspi0_data4), BUS_DATA_PIN_GROUP(qspi0_data, 4),
SH_PFC_PIN_GROUP(qspi1_ctrl), SH_PFC_PIN_GROUP(qspi1_ctrl),
SH_PFC_PIN_GROUP(qspi1_data2), BUS_DATA_PIN_GROUP(qspi1_data, 2),
SH_PFC_PIN_GROUP(qspi1_data4), BUS_DATA_PIN_GROUP(qspi1_data, 4),
SH_PFC_PIN_GROUP(scif0_data), SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk), SH_PFC_PIN_GROUP(scif0_clk),