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sh: mach-sdk7786: pm_power_off support.

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This wires up power-off support for the SDK7786 board.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt 2010-04-19 16:27:47 +09:00
parent dc825b1790
commit d9c944463d
2 changed files with 23 additions and 0 deletions
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14
arch/sh/boards/mach-sdk7786/setup.c
View File

@ -165,6 +165,19 @@ static void sdk7786_restart(char *cmd)
fpga_write_reg(0xa5a5, SRSTR);
}
static void sdk7786_power_off(void)
{
fpga_write_reg(fpga_read_reg(PWRCR) | PWRCR_PDWNREQ, PWRCR);
/*
* It can take up to 20us for the R8C to do its job, back off and
* wait a bit until we've been shut off. Even though newer FPGA
* versions don't set the ACK bit, the latency issue remains.
*/
while ((fpga_read_reg(PWRCR) & PWRCR_PDWNACK) == 0)
cpu_sleep();
}
/* Initialize the board */
static void __init sdk7786_setup(char **cmdline_p)
{
@ -175,6 +188,7 @@ static void __init sdk7786_setup(char **cmdline_p)
pr_info("\tPCB revision:\t%d\n", fpga_read_reg(PCBRR) & 0xf);
machine_ops.restart = sdk7786_restart;
pm_power_off = sdk7786_power_off;
}
/*

9
arch/sh/include/mach-sdk7786/mach/fpga.h
View File

@ -42,6 +42,15 @@
#define SCBR_I2CCEN BIT(1) /* CPU I2C master enable */
#define PWRCR 0x1a0
#define PWRCR_SCISEL0 BIT(0)
#define PWRCR_SCISEL1 BIT(1)
#define PWRCR_SCIEN BIT(2) /* Serial port enable */
#define PWRCR_PDWNACK BIT(5) /* Power down acknowledge */
#define PWRCR_PDWNREQ BIT(7) /* Power down request */
#define PWRCR_INT2 BIT(11) /* INT2 connection to power manager */
#define PWRCR_BUPINIT BIT(13) /* DDR backup initialize */
#define PWRCR_BKPRST BIT(15) /* Backup power reset */
#define SPCBR 0x1b0
#define SPICR 0x1c0
#define SPIDR 0x1d0