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cxl/pci: Get rid of pointer arithmetic reading CDAT table
Reading the CDAT table using DOE requires a Table Access Response
Header in addition to the CDAT entry. In current implementation this
has caused offsets with sizeof(__le32) to the actual buffers. This led
to hardly readable code and even bugs. E.g., see fix of devm_kfree()
in read_cdat_data():
commit c65efe3685
("cxl/cdat: Free correct buffer on checksum error")
Rework code to avoid calculations with sizeof(__le32). Introduce
struct cdat_doe_rsp for this which contains the Table Access Response
Header and a variable payload size for various data structures
afterwards to access the CDAT table and its CDAT Data Structures
without recalculating buffer offsets.
Cc: Lukas Wunner <lukas@wunner.de>
Cc: Fan Ni <nifan.cxl@gmail.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20240216155844.406996-3-rrichter@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
parent
ec8ffff3a9
commit
e0c818e004
@ -544,55 +544,57 @@ static int cxl_cdat_get_length(struct device *dev,
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static int cxl_cdat_read_table(struct device *dev,
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struct pci_doe_mb *doe_mb,
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void *cdat_table, size_t *cdat_length)
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struct cdat_doe_rsp *rsp, size_t *length)
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{
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size_t length = *cdat_length + sizeof(__le32);
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__le32 *data = cdat_table;
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int entry_handle = 0;
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size_t received, remaining = *length;
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unsigned int entry_handle = 0;
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union cdat_data *data;
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__le32 saved_dw = 0;
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do {
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__le32 request = CDAT_DOE_REQ(entry_handle);
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struct cdat_entry_header *entry;
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size_t entry_dw;
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int rc;
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rc = pci_doe(doe_mb, PCI_DVSEC_VENDOR_ID_CXL,
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CXL_DOE_PROTOCOL_TABLE_ACCESS,
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&request, sizeof(request),
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data, length);
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rsp, sizeof(*rsp) + remaining);
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if (rc < 0) {
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dev_err(dev, "DOE failed: %d", rc);
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return rc;
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}
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/* 1 DW Table Access Response Header + CDAT entry */
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entry = (struct cdat_entry_header *)(data + 1);
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if ((entry_handle == 0 &&
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rc != sizeof(__le32) + sizeof(struct cdat_header)) ||
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(entry_handle > 0 &&
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(rc < sizeof(__le32) + sizeof(*entry) ||
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rc != sizeof(__le32) + le16_to_cpu(entry->length))))
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if (rc < sizeof(*rsp))
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return -EIO;
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data = (union cdat_data *)rsp->data;
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received = rc - sizeof(*rsp);
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if (entry_handle == 0) {
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if (received != sizeof(data->header))
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return -EIO;
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} else {
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if (received < sizeof(data->entry) ||
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received != le16_to_cpu(data->entry.length))
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return -EIO;
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}
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/* Get the CXL table access header entry handle */
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entry_handle = FIELD_GET(CXL_DOE_TABLE_ACCESS_ENTRY_HANDLE,
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le32_to_cpu(data[0]));
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entry_dw = rc / sizeof(__le32);
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/* Skip Header */
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entry_dw -= 1;
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le32_to_cpu(rsp->doe_header));
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/*
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* Table Access Response Header overwrote the last DW of
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* previous entry, so restore that DW
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*/
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*data = saved_dw;
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length -= entry_dw * sizeof(__le32);
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data += entry_dw;
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saved_dw = *data;
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rsp->doe_header = saved_dw;
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remaining -= received;
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rsp = (void *)rsp + received;
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saved_dw = rsp->doe_header;
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} while (entry_handle != CXL_DOE_TABLE_ACCESS_LAST_ENTRY);
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/* Length in CDAT header may exceed concatenation of CDAT entries */
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*cdat_length -= length - sizeof(__le32);
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*length -= remaining;
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return 0;
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}
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@ -620,8 +622,8 @@ void read_cdat_data(struct cxl_port *port)
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struct pci_doe_mb *doe_mb;
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struct pci_dev *pdev = NULL;
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struct cxl_memdev *cxlmd;
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size_t cdat_length;
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void *cdat_table, *cdat_buf;
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struct cdat_doe_rsp *buf;
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size_t length;
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int rc;
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if (is_cxl_memdev(uport)) {
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@ -647,30 +649,33 @@ void read_cdat_data(struct cxl_port *port)
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port->cdat_available = true;
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if (cxl_cdat_get_length(dev, doe_mb, &cdat_length)) {
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if (cxl_cdat_get_length(dev, doe_mb, &length)) {
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dev_dbg(dev, "No CDAT length\n");
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return;
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}
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cdat_buf = devm_kzalloc(dev, cdat_length + sizeof(__le32), GFP_KERNEL);
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if (!cdat_buf)
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return;
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/*
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* The begin of the CDAT buffer needs space for additional 4
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* bytes for the DOE header. Table data starts afterwards.
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*/
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buf = devm_kzalloc(dev, sizeof(*buf) + length, GFP_KERNEL);
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if (!buf)
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goto err;
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rc = cxl_cdat_read_table(dev, doe_mb, cdat_buf, &cdat_length);
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rc = cxl_cdat_read_table(dev, doe_mb, buf, &length);
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if (rc)
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goto err;
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cdat_table = cdat_buf + sizeof(__le32);
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if (cdat_checksum(cdat_table, cdat_length))
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if (cdat_checksum(buf->data, length))
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goto err;
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port->cdat.table = cdat_table;
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port->cdat.length = cdat_length;
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return;
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port->cdat.table = buf->data;
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port->cdat.length = length;
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return;
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err:
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/* Don't leave table data allocated on error */
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devm_kfree(dev, cdat_buf);
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devm_kfree(dev, buf);
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dev_err(dev, "Failed to read/validate CDAT.\n");
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}
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EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL);
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@ -71,6 +71,15 @@ enum cxl_regloc_type {
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CXL_REGLOC_RBI_TYPES
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};
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/*
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* Table Access DOE, CDAT Read Entry Response
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*
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* Spec refs:
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*
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* CXL 3.1 8.1.11, Table 8-14: Read Entry Response
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* CDAT Specification 1.03: 2 CDAT Data Structures
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*/
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struct cdat_header {
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__le32 length;
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u8 revision;
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@ -85,6 +94,21 @@ struct cdat_entry_header {
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__le16 length;
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} __packed;
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/*
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* The DOE CDAT read response contains a CDAT read entry (either the
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* CDAT header or a structure).
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*/
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union cdat_data {
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struct cdat_header header;
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struct cdat_entry_header entry;
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} __packed;
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/* There is an additional CDAT response header of 4 bytes. */
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struct cdat_doe_rsp {
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__le32 doe_header;
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u8 data[];
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} __packed;
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/*
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* CXL v3.0 6.2.3 Table 6-4
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* The table indicates that if PCIe Flit Mode is set, then CXL is in 256B flits
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