mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
synced 2024-12-28 16:52:18 +00:00
Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
This commit is contained in:
Stephen Rothwell
commit
e1c6109e87
@ -240,6 +240,9 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- samsung,c1s # Samsung Galaxy Note20 5G (SM-N981B)
|
||||
- samsung,r8s # Samsung Galaxy S20 FE (SM-G780F)
|
||||
- samsung,x1s # Samsung Galaxy S20 5G (SM-G981B)
|
||||
- samsung,x1slte # Samsung Galaxy S20 (SM-G980F)
|
||||
- const: samsung,exynos990
|
||||
|
||||
- description: Exynos Auto v9 based boards
|
||||
|
||||
@ -0,0 +1,121 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/samsung,exynos990-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos990 SoC clock controller
|
||||
|
||||
maintainers:
|
||||
- Igor Belwon <igor.belwon@mentallysanemainliners.org>
|
||||
- Chanwoo Choi <cw00.choi@samsung.com>
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
description: |
|
||||
Exynos990 clock controller is comprised of several CMU units, generating
|
||||
clocks for different domains. Those CMU units are modeled as separate device
|
||||
tree nodes, and might depend on each other. The root clock in that root tree
|
||||
is an external clock: OSCCLK (26 MHz). This external clock must be defined
|
||||
as a fixed-rate clock in dts.
|
||||
|
||||
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
|
||||
dividers; all other clocks of function blocks (other CMUs) are usually
|
||||
derived from CMU_TOP.
|
||||
|
||||
Each clock is assigned an identifier and client nodes can use this identifier
|
||||
to specify the clock which they consume. All clocks available for usage
|
||||
in clock consumer nodes are defined as preprocessor macros in
|
||||
'include/dt-bindings/clock/samsung,exynos990.h' header.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos990-cmu-hsi0
|
||||
- samsung,exynos990-cmu-top
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- "#clock-cells"
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos990-cmu-hsi0
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
- description: CMU_HSI0 BUS clock (from CMU_TOP)
|
||||
- description: CMU_HSI0 USB31DRD clock (from CMU_TOP)
|
||||
- description: CMU_HSI0 USBDP_DEBUG clock (from CMU_TOP)
|
||||
- description: CMU_HSI0 DPGTC clock (from CMU_TOP)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
- const: bus
|
||||
- const: usb31drd
|
||||
- const: usbdp_debug
|
||||
- const: dpgtc
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: samsung,exynos990-cmu-top
|
||||
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External reference clock (26 MHz)
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: oscclk
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/samsung,exynos990.h>
|
||||
|
||||
cmu_hsi0: clock-controller@10a00000 {
|
||||
compatible = "samsung,exynos990-cmu-hsi0";
|
||||
reg = <0x10a00000 0x8000>;
|
||||
#clock-cells = <1>;
|
||||
|
||||
clocks = <&oscclk>,
|
||||
<&cmu_top CLK_DOUT_CMU_HSI0_BUS>,
|
||||
<&cmu_top CLK_DOUT_CMU_HSI0_USB31DRD>,
|
||||
<&cmu_top CLK_DOUT_CMU_HSI0_USBDP_DEBUG>,
|
||||
<&cmu_top CLK_DOUT_CMU_HSI0_DPGTC>;
|
||||
clock-names = "oscclk",
|
||||
"bus",
|
||||
"usb31drd",
|
||||
"usbdp_debug",
|
||||
"dpgtc";
|
||||
};
|
||||
|
||||
...
|
||||
@ -55,6 +55,7 @@ properties:
|
||||
- samsung,exynos7885-pmu
|
||||
- samsung,exynos8895-pmu
|
||||
- samsung,exynos9810-pmu
|
||||
- samsung,exynos990-pmu
|
||||
- samsung,exynosautov9-pmu
|
||||
- samsung,exynosautov920-pmu
|
||||
- tesla,fsd-pmu
|
||||
|
||||
@ -9761,9 +9761,12 @@ F: drivers/firmware/google/
|
||||
|
||||
GOOGLE TENSOR SoC SUPPORT
|
||||
M: Peter Griffin <peter.griffin@linaro.org>
|
||||
R: André Draszik <andre.draszik@linaro.org>
|
||||
R: Tudor Ambarus <tudor.ambarus@linaro.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-samsung-soc@vger.kernel.org
|
||||
S: Maintained
|
||||
C: irc://irc.oftc.net/pixel6-kernel-dev
|
||||
F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
|
||||
F: arch/arm64/boot/dts/exynos/google/
|
||||
F: drivers/clk/samsung/clk-gs101.c
|
||||
|
||||
@ -9,5 +9,8 @@ dtb-$(CONFIG_ARCH_EXYNOS) += \
|
||||
exynos850-e850-96.dtb \
|
||||
exynos8895-dreamlte.dtb \
|
||||
exynos990-c1s.dtb \
|
||||
exynos990-r8s.dtb \
|
||||
exynos990-x1s.dtb \
|
||||
exynos990-x1slte.dtb \
|
||||
exynosautov9-sadk.dtb \
|
||||
exynosautov920-sadk.dtb
|
||||
|
||||
@ -38,7 +38,17 @@ arm-a53-pmu {
|
||||
<&cpu3>;
|
||||
};
|
||||
|
||||
/* There's no PMU model for the Mongoose cores */
|
||||
mongoose-m2-pmu {
|
||||
compatible = "samsung,mongoose-pmu";
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu4>,
|
||||
<&cpu5>,
|
||||
<&cpu6>,
|
||||
<&cpu7>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
@ -218,6 +228,19 @@ cmu_peric0: clock-controller@10400000 {
|
||||
"usi1", "usi2", "usi3";
|
||||
};
|
||||
|
||||
serial_0: serial@10430000 {
|
||||
compatible = "samsung,exynos8895-uart";
|
||||
reg = <0x10430000 0x100>;
|
||||
clocks = <&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_PCLK>,
|
||||
<&cmu_peric0 CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_bus>;
|
||||
samsung,uart-fifosize = <256>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl_peric0: pinctrl@104d0000 {
|
||||
compatible = "samsung,exynos8895-pinctrl";
|
||||
reg = <0x104d0000 0x1000>;
|
||||
@ -250,6 +273,19 @@ cmu_peric1: clock-controller@10800000 {
|
||||
"usi10", "usi11", "usi12", "usi13";
|
||||
};
|
||||
|
||||
serial_1: serial@10830000 {
|
||||
compatible = "samsung,exynos8895-uart";
|
||||
reg = <0x10830000 0x100>;
|
||||
clocks = <&cmu_peric1 CLK_GOUT_PERIC1_UART_BT_PCLK>,
|
||||
<&cmu_peric1 CLK_GOUT_PERIC1_UART_BT_EXT_UCLK>;
|
||||
clock-names = "uart", "clk_uart_baud0";
|
||||
interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_bus>;
|
||||
samsung,uart-fifosize = <256>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl_peric1: pinctrl@10980000 {
|
||||
compatible = "samsung,exynos8895-pinctrl";
|
||||
reg = <0x10980000 0x1000>;
|
||||
|
||||
115
arch/arm64/boot/dts/exynos/exynos990-r8s.dts
Normal file
115
arch/arm64/boot/dts/exynos/exynos990-r8s.dts
Normal file
@ -0,0 +1,115 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* Samsung Galaxy S20 FE (r8s/SM-G780F) device tree source
|
||||
*
|
||||
* Copyright (c) 2024, Denzeel Oliva <wachiturroxd150@gmail.com>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "exynos990.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "Samsung Galaxy S20 FE";
|
||||
compatible = "samsung,r8s", "samsung,exynos990";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
chosen {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
framebuffer0: framebuffer@f1000000 {
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0 0xf1000000 0 (1080 * 2400 * 4)>;
|
||||
width = <1080>;
|
||||
height = <2400>;
|
||||
stride = <(1080 * 4)>;
|
||||
format = "a8r8g8b8";
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x0 0x3ab00000>,
|
||||
/* Memory hole */
|
||||
<0x0 0xc1200000 0x0 0x1ee00000>,
|
||||
/* Memory hole */
|
||||
<0x0 0xe1900000 0x0 0x1e700000>,
|
||||
/* Memory hole - last block */
|
||||
<0x8 0x80000000 0x0 0xc0000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
cont_splash_mem: framebuffer@f1000000 {
|
||||
reg = <0 0xf1000000 0 0x13c6800>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
abox_reserved: audio@f7fb0000 {
|
||||
reg = <0 0xf7fb0000 0 0x2a50000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&key_power &key_voldown &key_volup>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power-key {
|
||||
label = "Power";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
voldown-key {
|
||||
label = "Volume Down";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
gpios = <&gpa0 4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
volup-key {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&oscclk {
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
&pinctrl_alive {
|
||||
key_power: key-power-pins {
|
||||
samsung,pins = "gpa2-4";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
key_voldown: key-voldown-pins {
|
||||
samsung,pins = "gpa0-4";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
key_volup: key-volup-pins {
|
||||
samsung,pins = "gpa0-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
98
arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi
Normal file
98
arch/arm64/boot/dts/exynos/exynos990-x1s-common.dtsi
Normal file
@ -0,0 +1,98 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* Samsung Galaxy S20 Series device tree source
|
||||
*
|
||||
* Copyright (c) 2024, Umer Uddin <umer.uddin@mentallysanemainliners.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "exynos990.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
framebuffer0: framebuffer@f1000000 {
|
||||
compatible = "simple-framebuffer";
|
||||
reg = <0 0xf1000000 0 (1440 * 3200 * 4)>;
|
||||
width = <1440>;
|
||||
height = <3200>;
|
||||
stride = <(1440 * 4)>;
|
||||
format = "a8r8g8b8";
|
||||
};
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
cont_splash_mem: framebuffer@f1000000 {
|
||||
reg = <0 0xf1000000 0 0x1194000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
abox_reserved: audio@f7fb0000 {
|
||||
reg = <0 0xf7fb0000 0 0x2a50000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-0 = <&key_power &key_voldown &key_volup>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power-key {
|
||||
label = "Power";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
voldown-key {
|
||||
label = "Volume Down";
|
||||
linux,code = <KEY_VOLUMEDOWN>;
|
||||
gpios = <&gpa0 4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
volup-key {
|
||||
label = "Volume Up";
|
||||
linux,code = <KEY_VOLUMEUP>;
|
||||
gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&oscclk {
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
&pinctrl_alive {
|
||||
key_power: key-power-pins {
|
||||
samsung,pins = "gpa2-4";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
key_voldown: key-voldown-pins {
|
||||
samsung,pins = "gpa0-4";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
|
||||
key_volup: key-volup-pins {
|
||||
samsung,pins = "gpa0-3";
|
||||
samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
|
||||
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
|
||||
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV1>;
|
||||
};
|
||||
};
|
||||
28
arch/arm64/boot/dts/exynos/exynos990-x1s.dts
Normal file
28
arch/arm64/boot/dts/exynos/exynos990-x1s.dts
Normal file
@ -0,0 +1,28 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* Samsung Galaxy S20 5G (x1s/SM-G981B) device tree source
|
||||
*
|
||||
* Copyright (c) 2024, Umer Uddin <umer.uddin@mentallysanemainliners.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "exynos990-x1s-common.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
model = "Samsung Galaxy S20 5G";
|
||||
compatible = "samsung,x1s", "samsung,exynos990";
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x0 0x3ab00000>,
|
||||
/* Memory hole */
|
||||
<0x0 0xc1200000 0x0 0x1ee00000>,
|
||||
/* Memory hole */
|
||||
<0x0 0xe1900000 0x0 0x1e700000>,
|
||||
/* Memory hole */
|
||||
<0x8 0x80000000 0x2 0x7e800000>;
|
||||
};
|
||||
};
|
||||
28
arch/arm64/boot/dts/exynos/exynos990-x1slte.dts
Normal file
28
arch/arm64/boot/dts/exynos/exynos990-x1slte.dts
Normal file
@ -0,0 +1,28 @@
|
||||
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
|
||||
/*
|
||||
* Samsung Galaxy S20 (x1slte/SM-G980F) device tree source
|
||||
*
|
||||
* Copyright (c) 2024, Umer Uddin <umer.uddin@mentallysanemainliners.org>
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "exynos990-x1s-common.dtsi"
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
model = "Samsung Galaxy S20";
|
||||
compatible = "samsung,x1slte", "samsung,exynos990";
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x80000000 0x0 0x3ab00000>,
|
||||
/* Memory hole */
|
||||
<0x0 0xc1200000 0x0 0x1ee00000>,
|
||||
/* Memory hole */
|
||||
<0x0 0xe1900000 0x0 0x1e700000>,
|
||||
/* Memory hole */
|
||||
<0x8 0x80000000 0x1 0x7ec00000>;
|
||||
};
|
||||
};
|
||||
@ -227,6 +227,20 @@ wakeup-interrupt-controller {
|
||||
};
|
||||
};
|
||||
|
||||
pmu_system_controller: system-controller@15860000 {
|
||||
compatible = "samsung,exynos990-pmu",
|
||||
"samsung,exynos7-pmu", "syscon";
|
||||
reg = <0x15860000 0x10000>;
|
||||
|
||||
reboot: syscon-reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&pmu_system_controller>;
|
||||
offset = <0x3a00>; /* SWRESET */
|
||||
mask = <0x2>; /* SWRESET_TRIGGER */
|
||||
value = <0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_cmgp: pinctrl@15c30000 {
|
||||
compatible = "samsung,exynos990-pinctrl";
|
||||
reg = <0x15c30000 0x1000>;
|
||||
|
||||
@ -183,6 +183,26 @@ cmu_misc: clock-controller@10020000 {
|
||||
"noc";
|
||||
};
|
||||
|
||||
watchdog_cl0: watchdog@10060000 {
|
||||
compatible = "samsung,exynosautov920-wdt";
|
||||
reg = <0x10060000 0x100>;
|
||||
interrupts = <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&xtcxo>, <&xtcxo>;
|
||||
clock-names = "watchdog", "watchdog_src";
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
samsung,cluster-index = <0>;
|
||||
};
|
||||
|
||||
watchdog_cl1: watchdog@10070000 {
|
||||
compatible = "samsung,exynosautov920-wdt";
|
||||
reg = <0x10070000 0x100>;
|
||||
interrupts = <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&xtcxo>, <&xtcxo>;
|
||||
clock-names = "watchdog", "watchdog_src";
|
||||
samsung,syscon-phandle = <&pmu_system_controller>;
|
||||
samsung,cluster-index = <1>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@10400000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
@ -193,6 +213,69 @@ gic: interrupt-controller@10400000 {
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spdma0: dma-controller@10180000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x10180000 0x1000>;
|
||||
interrupts = <GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
spdma1: dma-controller@10190000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x10190000 0x1000>;
|
||||
interrupts = <GIC_SPI 917 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
pdma0: dma-controller@101a0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x101a0000 0x1000>;
|
||||
interrupts = <GIC_SPI 916 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
pdma1: dma-controller@101b0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x101b0000 0x1000>;
|
||||
interrupts = <GIC_SPI 915 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
pdma2: dma-controller@101c0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x101c0000 0x1000>;
|
||||
interrupts = <GIC_SPI 914 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
pdma3: dma-controller@101d0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x101d0000 0x1000>;
|
||||
interrupts = <GIC_SPI 913 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
pdma4: dma-controller@101e0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x101e0000 0x1000>;
|
||||
interrupts = <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cmu_misc CLK_MOUT_MISC_NOC_USER>;
|
||||
clock-names = "apb_pclk";
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
cmu_peric0: clock-controller@10800000 {
|
||||
compatible = "samsung,exynosautov920-cmu-peric0";
|
||||
reg = <0x10800000 0x8000>;
|
||||
|
||||
@ -1267,7 +1267,7 @@ cmu_hsi0: clock-controller@11000000 {
|
||||
|
||||
usbdrd31_phy: phy@11100000 {
|
||||
compatible = "google,gs101-usb31drd-phy";
|
||||
reg = <0x11100000 0x0100>,
|
||||
reg = <0x11100000 0x0200>,
|
||||
<0x110f0000 0x0800>,
|
||||
<0x110e0000 0x2800>;
|
||||
reg-names = "phy", "pcs", "pma";
|
||||
@ -1302,6 +1302,9 @@ usbdrd31_dwc3: usb@0 {
|
||||
interrupts = <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
phys = <&usbdrd31_phy 0>, <&usbdrd31_phy 1>;
|
||||
phy-names = "usb2-phy", "usb3-phy";
|
||||
snps,has-lpm-erratum;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
snps,dis_u3_susphy_quirk;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
@ -1125,6 +1125,7 @@ CONFIG_USB_MASS_STORAGE=m
|
||||
CONFIG_TYPEC=m
|
||||
CONFIG_TYPEC_TCPM=m
|
||||
CONFIG_TYPEC_TCPCI=m
|
||||
CONFIG_TYPEC_TCPCI_MAXIM=m
|
||||
CONFIG_TYPEC_FUSB302=m
|
||||
CONFIG_TYPEC_QCOM_PMIC=m
|
||||
CONFIG_TYPEC_UCSI=m
|
||||
|
||||
@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos8895.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos990.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o
|
||||
|
||||
1343
drivers/clk/samsung/clk-exynos990.c
Normal file
1343
drivers/clk/samsung/clk-exynos990.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -430,7 +430,10 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops = {
|
||||
#define PLL0822X_LOCK_STAT_SHIFT (29)
|
||||
#define PLL0822X_ENABLE_SHIFT (31)
|
||||
|
||||
/* PLL1418x is similar to PLL0822x, except that MDIV is one bit smaller */
|
||||
/*
|
||||
* PLL1418x, PLL0717x and PLL0718x are similar
|
||||
* to PLL0822x, except that MDIV is one bit smaller
|
||||
*/
|
||||
#define PLL1418X_MDIV_MASK (0x1FF)
|
||||
|
||||
static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
|
||||
@ -441,10 +444,14 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
|
||||
u64 fvco = parent_rate;
|
||||
|
||||
pll_con3 = readl_relaxed(pll->con_reg);
|
||||
if (pll->type != pll_1418x)
|
||||
|
||||
if (pll->type != pll_1418x &&
|
||||
pll->type != pll_0717x &&
|
||||
pll->type != pll_0718x)
|
||||
mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;
|
||||
else
|
||||
mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL1418X_MDIV_MASK;
|
||||
|
||||
pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
|
||||
sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
|
||||
|
||||
@ -1377,6 +1384,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
|
||||
case pll_0516x:
|
||||
case pll_0517x:
|
||||
case pll_0518x:
|
||||
case pll_0717x:
|
||||
case pll_0718x:
|
||||
case pll_0732x:
|
||||
pll->enable_offs = PLL0822X_ENABLE_SHIFT;
|
||||
pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
|
||||
if (!pll->rate_table)
|
||||
|
||||
@ -45,6 +45,9 @@ enum samsung_pll_type {
|
||||
pll_531x,
|
||||
pll_1051x,
|
||||
pll_1052x,
|
||||
pll_0717x,
|
||||
pll_0718x,
|
||||
pll_0732x,
|
||||
};
|
||||
|
||||
#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \
|
||||
|
||||
236
include/dt-bindings/clock/samsung,exynos990.h
Normal file
236
include/dt-bindings/clock/samsung,exynos990.h
Normal file
@ -0,0 +1,236 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Copyright (C) 2024 Igor Belwon <igor.belwon@mentallysanemainliners.org>
|
||||
*
|
||||
* Device Tree binding constants for Exynos990 clock controller.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLOCK_EXYNOS_990_H
|
||||
#define _DT_BINDINGS_CLOCK_EXYNOS_990_H
|
||||
|
||||
/* CMU_TOP */
|
||||
#define CLK_FOUT_SHARED0_PLL 1
|
||||
#define CLK_FOUT_SHARED1_PLL 2
|
||||
#define CLK_FOUT_SHARED2_PLL 3
|
||||
#define CLK_FOUT_SHARED3_PLL 4
|
||||
#define CLK_FOUT_SHARED4_PLL 5
|
||||
#define CLK_FOUT_G3D_PLL 6
|
||||
#define CLK_FOUT_MMC_PLL 7
|
||||
#define CLK_MOUT_PLL_SHARED0 8
|
||||
#define CLK_MOUT_PLL_SHARED1 9
|
||||
#define CLK_MOUT_PLL_SHARED2 10
|
||||
#define CLK_MOUT_PLL_SHARED3 11
|
||||
#define CLK_MOUT_PLL_SHARED4 12
|
||||
#define CLK_MOUT_PLL_MMC 13
|
||||
#define CLK_MOUT_PLL_G3D 14
|
||||
#define CLK_MOUT_CMU_APM_BUS 15
|
||||
#define CLK_MOUT_CMU_AUD_CPU 16
|
||||
#define CLK_MOUT_CMU_BUS0_BUS 17
|
||||
#define CLK_MOUT_CMU_BUS1_BUS 18
|
||||
#define CLK_MOUT_CMU_BUS1_SSS 19
|
||||
#define CLK_MOUT_CMU_CIS_CLK0 20
|
||||
#define CLK_MOUT_CMU_CIS_CLK1 21
|
||||
#define CLK_MOUT_CMU_CIS_CLK2 22
|
||||
#define CLK_MOUT_CMU_CIS_CLK3 23
|
||||
#define CLK_MOUT_CMU_CIS_CLK4 24
|
||||
#define CLK_MOUT_CMU_CIS_CLK5 25
|
||||
#define CLK_MOUT_CMU_CMU_BOOST 26
|
||||
#define CLK_MOUT_CMU_CORE_BUS 27
|
||||
#define CLK_MOUT_CMU_CPUCL0_DBG_BUS 28
|
||||
#define CLK_MOUT_CMU_CPUCL0_SWITCH 29
|
||||
#define CLK_MOUT_CMU_CPUCL1_SWITCH 30
|
||||
#define CLK_MOUT_CMU_CPUCL2_BUSP 31
|
||||
#define CLK_MOUT_CMU_CPUCL2_SWITCH 32
|
||||
#define CLK_MOUT_CMU_CSIS_BUS 33
|
||||
#define CLK_MOUT_CMU_CSIS_OIS_MCU 34
|
||||
#define CLK_MOUT_CMU_DNC_BUS 35
|
||||
#define CLK_MOUT_CMU_DNC_BUSM 36
|
||||
#define CLK_MOUT_CMU_DNS_BUS 37
|
||||
#define CLK_MOUT_CMU_DPU 38
|
||||
#define CLK_MOUT_CMU_DPU_ALT 39
|
||||
#define CLK_MOUT_CMU_DSP_BUS 40
|
||||
#define CLK_MOUT_CMU_G2D_G2D 41
|
||||
#define CLK_MOUT_CMU_G2D_MSCL 42
|
||||
#define CLK_MOUT_CMU_HPM 43
|
||||
#define CLK_MOUT_CMU_HSI0_BUS 44
|
||||
#define CLK_MOUT_CMU_HSI0_DPGTC 45
|
||||
#define CLK_MOUT_CMU_HSI0_USB31DRD 46
|
||||
#define CLK_MOUT_CMU_HSI0_USBDP_DEBUG 47
|
||||
#define CLK_MOUT_CMU_HSI1_BUS 48
|
||||
#define CLK_MOUT_CMU_HSI1_MMC_CARD 49
|
||||
#define CLK_MOUT_CMU_HSI1_PCIE 50
|
||||
#define CLK_MOUT_CMU_HSI1_UFS_CARD 51
|
||||
#define CLK_MOUT_CMU_HSI1_UFS_EMBD 52
|
||||
#define CLK_MOUT_CMU_HSI2_BUS 53
|
||||
#define CLK_MOUT_CMU_HSI2_PCIE 54
|
||||
#define CLK_MOUT_CMU_IPP_BUS 55
|
||||
#define CLK_MOUT_CMU_ITP_BUS 56
|
||||
#define CLK_MOUT_CMU_MCSC_BUS 57
|
||||
#define CLK_MOUT_CMU_MCSC_GDC 58
|
||||
#define CLK_MOUT_CMU_CMU_BOOST_CPU 59
|
||||
#define CLK_MOUT_CMU_MFC0_MFC0 60
|
||||
#define CLK_MOUT_CMU_MFC0_WFD 61
|
||||
#define CLK_MOUT_CMU_MIF_BUSP 62
|
||||
#define CLK_MOUT_CMU_MIF_SWITCH 63
|
||||
#define CLK_MOUT_CMU_NPU_BUS 64
|
||||
#define CLK_MOUT_CMU_PERIC0_BUS 65
|
||||
#define CLK_MOUT_CMU_PERIC0_IP 66
|
||||
#define CLK_MOUT_CMU_PERIC1_BUS 67
|
||||
#define CLK_MOUT_CMU_PERIC1_IP 68
|
||||
#define CLK_MOUT_CMU_PERIS_BUS 69
|
||||
#define CLK_MOUT_CMU_SSP_BUS 70
|
||||
#define CLK_MOUT_CMU_TNR_BUS 71
|
||||
#define CLK_MOUT_CMU_VRA_BUS 72
|
||||
#define CLK_DOUT_CMU_APM_BUS 73
|
||||
#define CLK_DOUT_CMU_AUD_CPU 74
|
||||
#define CLK_DOUT_CMU_BUS0_BUS 75
|
||||
#define CLK_DOUT_CMU_BUS1_BUS 76
|
||||
#define CLK_DOUT_CMU_BUS1_SSS 77
|
||||
#define CLK_DOUT_CMU_CIS_CLK0 78
|
||||
#define CLK_DOUT_CMU_CIS_CLK1 79
|
||||
#define CLK_DOUT_CMU_CIS_CLK2 80
|
||||
#define CLK_DOUT_CMU_CIS_CLK3 81
|
||||
#define CLK_DOUT_CMU_CIS_CLK4 82
|
||||
#define CLK_DOUT_CMU_CIS_CLK5 83
|
||||
#define CLK_DOUT_CMU_CMU_BOOST 84
|
||||
#define CLK_DOUT_CMU_CORE_BUS 85
|
||||
#define CLK_DOUT_CMU_CPUCL0_DBG_BUS 86
|
||||
#define CLK_DOUT_CMU_CPUCL0_SWITCH 87
|
||||
#define CLK_DOUT_CMU_CPUCL1_SWITCH 88
|
||||
#define CLK_DOUT_CMU_CPUCL2_BUSP 89
|
||||
#define CLK_DOUT_CMU_CPUCL2_SWITCH 90
|
||||
#define CLK_DOUT_CMU_CSIS_BUS 91
|
||||
#define CLK_DOUT_CMU_CSIS_OIS_MCU 92
|
||||
#define CLK_DOUT_CMU_DNC_BUS 93
|
||||
#define CLK_DOUT_CMU_DNC_BUSM 94
|
||||
#define CLK_DOUT_CMU_DNS_BUS 95
|
||||
#define CLK_DOUT_CMU_DSP_BUS 96
|
||||
#define CLK_DOUT_CMU_G2D_G2D 97
|
||||
#define CLK_DOUT_CMU_G2D_MSCL 98
|
||||
#define CLK_DOUT_CMU_G3D_SWITCH 99
|
||||
#define CLK_DOUT_CMU_HPM 100
|
||||
#define CLK_DOUT_CMU_HSI0_BUS 101
|
||||
#define CLK_DOUT_CMU_HSI0_DPGTC 102
|
||||
#define CLK_DOUT_CMU_HSI0_USB31DRD 103
|
||||
#define CLK_DOUT_CMU_HSI0_USBDP_DEBUG 104
|
||||
#define CLK_DOUT_CMU_HSI1_BUS 105
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#define CLK_DOUT_CMU_HSI1_MMC_CARD 106
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#define CLK_DOUT_CMU_HSI1_PCIE 107
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#define CLK_DOUT_CMU_HSI1_UFS_CARD 108
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#define CLK_DOUT_CMU_HSI1_UFS_EMBD 109
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||||
#define CLK_DOUT_CMU_HSI2_BUS 110
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||||
#define CLK_DOUT_CMU_HSI2_PCIE 111
|
||||
#define CLK_DOUT_CMU_IPP_BUS 112
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||||
#define CLK_DOUT_CMU_ITP_BUS 113
|
||||
#define CLK_DOUT_CMU_MCSC_BUS 114
|
||||
#define CLK_DOUT_CMU_MCSC_GDC 115
|
||||
#define CLK_DOUT_CMU_CMU_BOOST_CPU 116
|
||||
#define CLK_DOUT_CMU_MFC0_MFC0 117
|
||||
#define CLK_DOUT_CMU_MFC0_WFD 118
|
||||
#define CLK_DOUT_CMU_MIF_BUSP 119
|
||||
#define CLK_DOUT_CMU_NPU_BUS 120
|
||||
#define CLK_DOUT_CMU_OTP 121
|
||||
#define CLK_DOUT_CMU_PERIC0_BUS 122
|
||||
#define CLK_DOUT_CMU_PERIC0_IP 123
|
||||
#define CLK_DOUT_CMU_PERIC1_BUS 124
|
||||
#define CLK_DOUT_CMU_PERIC1_IP 125
|
||||
#define CLK_DOUT_CMU_PERIS_BUS 126
|
||||
#define CLK_DOUT_CMU_SSP_BUS 127
|
||||
#define CLK_DOUT_CMU_TNR_BUS 128
|
||||
#define CLK_DOUT_CMU_VRA_BUS 129
|
||||
#define CLK_DOUT_CMU_DPU 130
|
||||
#define CLK_DOUT_CMU_DPU_ALT 131
|
||||
#define CLK_DOUT_CMU_SHARED0_DIV2 132
|
||||
#define CLK_DOUT_CMU_SHARED0_DIV3 133
|
||||
#define CLK_DOUT_CMU_SHARED0_DIV4 134
|
||||
#define CLK_DOUT_CMU_SHARED1_DIV2 135
|
||||
#define CLK_DOUT_CMU_SHARED1_DIV3 136
|
||||
#define CLK_DOUT_CMU_SHARED1_DIV4 137
|
||||
#define CLK_DOUT_CMU_SHARED2_DIV2 138
|
||||
#define CLK_DOUT_CMU_SHARED4_DIV2 139
|
||||
#define CLK_DOUT_CMU_SHARED4_DIV3 140
|
||||
#define CLK_DOUT_CMU_SHARED4_DIV4 141
|
||||
#define CLK_GOUT_CMU_G3D_BUS 142
|
||||
#define CLK_GOUT_CMU_MIF_SWITCH 143
|
||||
#define CLK_GOUT_CMU_APM_BUS 144
|
||||
#define CLK_GOUT_CMU_AUD_CPU 145
|
||||
#define CLK_GOUT_CMU_BUS0_BUS 146
|
||||
#define CLK_GOUT_CMU_BUS1_BUS 147
|
||||
#define CLK_GOUT_CMU_BUS1_SSS 148
|
||||
#define CLK_GOUT_CMU_CIS_CLK0 149
|
||||
#define CLK_GOUT_CMU_CIS_CLK1 150
|
||||
#define CLK_GOUT_CMU_CIS_CLK2 151
|
||||
#define CLK_GOUT_CMU_CIS_CLK3 152
|
||||
#define CLK_GOUT_CMU_CIS_CLK4 153
|
||||
#define CLK_GOUT_CMU_CIS_CLK5 154
|
||||
#define CLK_GOUT_CMU_CORE_BUS 155
|
||||
#define CLK_GOUT_CMU_CPUCL0_DBG_BUS 156
|
||||
#define CLK_GOUT_CMU_CPUCL0_SWITCH 157
|
||||
#define CLK_GOUT_CMU_CPUCL1_SWITCH 158
|
||||
#define CLK_GOUT_CMU_CPUCL2_BUSP 159
|
||||
#define CLK_GOUT_CMU_CPUCL2_SWITCH 160
|
||||
#define CLK_GOUT_CMU_CSIS_BUS 161
|
||||
#define CLK_GOUT_CMU_CSIS_OIS_MCU 162
|
||||
#define CLK_GOUT_CMU_DNC_BUS 163
|
||||
#define CLK_GOUT_CMU_DNC_BUSM 164
|
||||
#define CLK_GOUT_CMU_DNS_BUS 165
|
||||
#define CLK_GOUT_CMU_DPU 166
|
||||
#define CLK_GOUT_CMU_DPU_BUS 167
|
||||
#define CLK_GOUT_CMU_DSP_BUS 168
|
||||
#define CLK_GOUT_CMU_G2D_G2D 169
|
||||
#define CLK_GOUT_CMU_G2D_MSCL 170
|
||||
#define CLK_GOUT_CMU_G3D_SWITCH 171
|
||||
#define CLK_GOUT_CMU_HPM 172
|
||||
#define CLK_GOUT_CMU_HSI0_BUS 173
|
||||
#define CLK_GOUT_CMU_HSI0_DPGTC 174
|
||||
#define CLK_GOUT_CMU_HSI0_USB31DRD 175
|
||||
#define CLK_GOUT_CMU_HSI0_USBDP_DEBUG 176
|
||||
#define CLK_GOUT_CMU_HSI1_BUS 177
|
||||
#define CLK_GOUT_CMU_HSI1_MMC_CARD 178
|
||||
#define CLK_GOUT_CMU_HSI1_PCIE 179
|
||||
#define CLK_GOUT_CMU_HSI1_UFS_CARD 180
|
||||
#define CLK_GOUT_CMU_HSI1_UFS_EMBD 181
|
||||
#define CLK_GOUT_CMU_HSI2_BUS 182
|
||||
#define CLK_GOUT_CMU_HSI2_PCIE 183
|
||||
#define CLK_GOUT_CMU_IPP_BUS 184
|
||||
#define CLK_GOUT_CMU_ITP_BUS 185
|
||||
#define CLK_GOUT_CMU_MCSC_BUS 186
|
||||
#define CLK_GOUT_CMU_MCSC_GDC 187
|
||||
#define CLK_GOUT_CMU_MFC0_MFC0 188
|
||||
#define CLK_GOUT_CMU_MFC0_WFD 189
|
||||
#define CLK_GOUT_CMU_MIF_BUSP 190
|
||||
#define CLK_GOUT_CMU_NPU_BUS 191
|
||||
#define CLK_GOUT_CMU_PERIC0_BUS 192
|
||||
#define CLK_GOUT_CMU_PERIC0_IP 193
|
||||
#define CLK_GOUT_CMU_PERIC1_BUS 194
|
||||
#define CLK_GOUT_CMU_PERIC1_IP 195
|
||||
#define CLK_GOUT_CMU_PERIS_BUS 196
|
||||
#define CLK_GOUT_CMU_SSP_BUS 197
|
||||
#define CLK_GOUT_CMU_TNR_BUS 198
|
||||
#define CLK_GOUT_CMU_VRA_BUS 199
|
||||
|
||||
/* CMU_HSI0 */
|
||||
#define CLK_MOUT_HSI0_BUS_USER 1
|
||||
#define CLK_MOUT_HSI0_USB31DRD_USER 2
|
||||
#define CLK_MOUT_HSI0_USBDP_DEBUG_USER 3
|
||||
#define CLK_MOUT_HSI0_DPGTC_USER 4
|
||||
#define CLK_GOUT_HSI0_DP_LINK_DP_GTC_CLK 5
|
||||
#define CLK_GOUT_HSI0_DP_LINK_PCLK 6
|
||||
#define CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK 7
|
||||
#define CLK_GOUT_HSI0_LHM_AXI_P_HSI0_CLK 8
|
||||
#define CLK_GOUT_HSI0_PPMU_HSI0_BUS1_ACLK 9
|
||||
#define CLK_GOUT_HSI0_PPMU_HSI0_BUS1_PCLK 10
|
||||
#define CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK 11
|
||||
#define CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2 12
|
||||
#define CLK_GOUT_HSI0_SYSREG_HSI0_PCLK 13
|
||||
#define CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL 14
|
||||
#define CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY 15
|
||||
#define CLK_GOUT_HSI0_USB31DRD_USB31DRD_REF_CLK_40 16
|
||||
#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_REF_SOC_PLL 17
|
||||
#define CLK_GOUT_HSI0_USB31DRD_USBDPPHY_SCL_APB 18
|
||||
#define CLK_GOUT_HSI0_USB31DRD_USBPCS_APB_CLK 19
|
||||
#define CLK_GOUT_HSI0_VGEN_LITE_HSI0_CLK 20
|
||||
#define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21
|
||||
#define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user