mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
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bnx2x: add DCB support
Adding DCB initialization and handling on 57712 FW/HW Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com> Signed-off-by: Shmulik Ravid-Rabinovitz <shmulikr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Vladislav Zolotarov
David S. Miller
parent
8307fa3e86
commit
e4901dde12
@ -4,4 +4,4 @@
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obj-$(CONFIG_BNX2X) += bnx2x.o
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bnx2x-objs := bnx2x_main.o bnx2x_link.o bnx2x_cmn.o bnx2x_ethtool.o bnx2x_stats.o
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bnx2x-objs := bnx2x_main.o bnx2x_link.o bnx2x_cmn.o bnx2x_ethtool.o bnx2x_stats.o bnx2x_dcb.o
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@ -50,6 +50,7 @@
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#include "bnx2x_fw_defs.h"
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#include "bnx2x_hsi.h"
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#include "bnx2x_link.h"
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#include "bnx2x_dcb.h"
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#include "bnx2x_stats.h"
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/* error/debug prints */
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@ -820,6 +821,8 @@ struct bnx2x_slowpath {
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u32 wb_comp;
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u32 wb_data[4];
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/* pfc configuration for DCBX ramrod */
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struct flow_control_configuration pfc_config;
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};
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#define bnx2x_sp(bp, var) (&bp->slowpath->var)
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@ -1180,6 +1183,18 @@ struct bnx2x {
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char fw_ver[32];
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const struct firmware *firmware;
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/* LLDP params */
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struct bnx2x_config_lldp_params lldp_config_params;
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/* DCBX params */
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struct bnx2x_config_dcbx_params dcbx_config_params;
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struct bnx2x_dcbx_port_params dcbx_port_params;
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int dcb_version;
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/* DCBX Negotation results */
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struct dcbx_features dcbx_local_feat;
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u32 dcbx_error;
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};
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/**
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@ -1371,6 +1371,8 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
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}
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}
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bnx2x_dcbx_init(bp);
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bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
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rc = bnx2x_func_start(bp);
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@ -323,6 +323,13 @@ int bnx2x_func_start(struct bnx2x *bp);
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*/
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void bnx2x_ilt_set_info(struct bnx2x *bp);
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/**
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* Inintialize dcbx protocol
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*
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* @param bp
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*/
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void bnx2x_dcbx_init(struct bnx2x *bp);
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/**
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* Set power state to the requested value. Currently only D0 and
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* D3hot are supported.
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1491
drivers/net/bnx2x/bnx2x_dcb.c
Normal file
1491
drivers/net/bnx2x/bnx2x_dcb.c
Normal file
File diff suppressed because it is too large
Load Diff
193
drivers/net/bnx2x/bnx2x_dcb.h
Normal file
193
drivers/net/bnx2x/bnx2x_dcb.h
Normal file
@ -0,0 +1,193 @@
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/* bnx2x_dcb.h: Broadcom Everest network driver.
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*
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* Copyright 2009-2010 Broadcom Corporation
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available
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* at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*
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* Maintained by: Eilon Greenstein <eilong@broadcom.com>
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* Written by: Dmitry Kravkov
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*
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*/
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#ifndef BNX2X_DCB_H
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#define BNX2X_DCB_H
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#include "bnx2x_hsi.h"
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#define LLFC_DRIVER_TRAFFIC_TYPE_MAX 3 /* NW, iSCSI, FCoE */
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struct bnx2x_dcbx_app_params {
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u32 enabled;
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u32 traffic_type_priority[LLFC_DRIVER_TRAFFIC_TYPE_MAX];
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};
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#define E2_NUM_OF_COS 2
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#define BNX2X_DCBX_COS_NOT_STRICT 0
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#define BNX2X_DCBX_COS_LOW_STRICT 1
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#define BNX2X_DCBX_COS_HIGH_STRICT 2
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struct bnx2x_dcbx_cos_params {
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u32 bw_tbl;
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u32 pri_bitmask;
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u8 strict;
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u8 pauseable;
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};
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struct bnx2x_dcbx_pg_params {
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u32 enabled;
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u8 num_of_cos; /* valid COS entries */
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struct bnx2x_dcbx_cos_params cos_params[E2_NUM_OF_COS];
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};
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struct bnx2x_dcbx_pfc_params {
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u32 enabled;
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u32 priority_non_pauseable_mask;
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};
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struct bnx2x_dcbx_port_params {
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u32 dcbx_enabled;
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struct bnx2x_dcbx_pfc_params pfc;
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struct bnx2x_dcbx_pg_params ets;
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struct bnx2x_dcbx_app_params app;
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};
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#define BNX2X_DCBX_CONFIG_INV_VALUE (0xFFFFFFFF)
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#define BNX2X_DCBX_OVERWRITE_SETTINGS_DISABLE 0
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#define BNX2X_DCBX_OVERWRITE_SETTINGS_ENABLE 1
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#define BNX2X_DCBX_OVERWRITE_SETTINGS_INVALID (BNX2X_DCBX_CONFIG_INV_VALUE)
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/*******************************************************************************
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* LLDP protocol configuration parameters.
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******************************************************************************/
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struct bnx2x_config_lldp_params {
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u32 overwrite_settings;
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u32 msg_tx_hold;
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u32 msg_fast_tx;
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u32 tx_credit_max;
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u32 msg_tx_interval;
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u32 tx_fast;
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};
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struct bnx2x_admin_priority_app_table {
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u32 valid;
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u32 priority;
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#define INVALID_TRAFFIC_TYPE_PRIORITY (0xFFFFFFFF)
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u32 traffic_type;
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#define TRAFFIC_TYPE_ETH 0
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#define TRAFFIC_TYPE_PORT 1
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u32 app_id;
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};
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/*******************************************************************************
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* DCBX protocol configuration parameters.
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******************************************************************************/
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struct bnx2x_config_dcbx_params {
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u32 dcb_enable;
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u32 admin_dcbx_enable;
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u32 overwrite_settings;
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u32 admin_dcbx_version;
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u32 admin_ets_enable;
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u32 admin_pfc_enable;
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u32 admin_tc_supported_tx_enable;
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u32 admin_ets_configuration_tx_enable;
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u32 admin_ets_recommendation_tx_enable;
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u32 admin_pfc_tx_enable;
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u32 admin_application_priority_tx_enable;
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u32 admin_ets_willing;
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u32 admin_ets_reco_valid;
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u32 admin_pfc_willing;
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u32 admin_app_priority_willing;
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u32 admin_configuration_bw_precentage[8];
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u32 admin_configuration_ets_pg[8];
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u32 admin_recommendation_bw_precentage[8];
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u32 admin_recommendation_ets_pg[8];
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u32 admin_pfc_bitmap;
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struct bnx2x_admin_priority_app_table admin_priority_app_table[4];
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u32 admin_default_priority;
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};
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#define GET_FLAGS(flags, bits) ((flags) & (bits))
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#define SET_FLAGS(flags, bits) ((flags) |= (bits))
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#define RESET_FLAGS(flags, bits) ((flags) &= ~(bits))
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enum {
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DCBX_READ_LOCAL_MIB,
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DCBX_READ_REMOTE_MIB
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};
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#define ETH_TYPE_FCOE (0x8906)
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#define TCP_PORT_ISCSI (0xCBC)
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#define PFC_VALUE_FRAME_SIZE (512)
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#define PFC_QUANTA_IN_NANOSEC_FROM_SPEED_MEGA(mega_speed) \
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((1000 * PFC_VALUE_FRAME_SIZE)/(mega_speed))
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#define PFC_BRB1_REG_HIGH_LLFC_LOW_THRESHOLD 130
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#define PFC_BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD 170
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struct cos_entry_help_data {
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u32 pri_join_mask;
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u32 cos_bw;
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u8 strict;
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bool pausable;
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};
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struct cos_help_data {
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struct cos_entry_help_data data[E2_NUM_OF_COS];
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u8 num_of_cos;
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};
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#define DCBX_ILLEGAL_PG (0xFF)
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#define DCBX_PFC_PRI_MASK (0xFF)
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#define DCBX_STRICT_PRIORITY (15)
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#define DCBX_INVALID_COS_BW (0xFFFFFFFF)
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#define DCBX_PFC_PRI_NON_PAUSE_MASK(bp) \
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((bp)->dcbx_port_params.pfc.priority_non_pauseable_mask)
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#define DCBX_PFC_PRI_PAUSE_MASK(bp) \
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((u8)~DCBX_PFC_PRI_NON_PAUSE_MASK(bp))
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#define DCBX_PFC_PRI_GET_PAUSE(bp, pg_pri) \
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((pg_pri) & (DCBX_PFC_PRI_PAUSE_MASK(bp)))
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#define DCBX_PFC_PRI_GET_NON_PAUSE(bp, pg_pri) \
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(DCBX_PFC_PRI_NON_PAUSE_MASK(bp) & (pg_pri))
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#define IS_DCBX_PFC_PRI_ONLY_PAUSE(bp, pg_pri) \
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(pg_pri == DCBX_PFC_PRI_GET_PAUSE((bp), (pg_pri)))
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#define IS_DCBX_PFC_PRI_ONLY_NON_PAUSE(bp, pg_pri)\
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((pg_pri) == DCBX_PFC_PRI_GET_NON_PAUSE((bp), (pg_pri)))
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#define IS_DCBX_PFC_PRI_MIX_PAUSE(bp, pg_pri) \
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(!(IS_DCBX_PFC_PRI_ONLY_NON_PAUSE((bp), (pg_pri)) || \
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IS_DCBX_PFC_PRI_ONLY_PAUSE((bp), (pg_pri))))
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struct pg_entry_help_data {
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u8 num_of_dif_pri;
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u8 pg;
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u32 pg_priority;
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};
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struct pg_help_data {
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struct pg_entry_help_data data[LLFC_DRIVER_TRAFFIC_TYPE_MAX];
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u8 num_of_pg;
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};
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/* forward DCB/PFC related declarations */
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struct bnx2x;
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void bnx2x_dcb_init_intmem_pfc(struct bnx2x *bp);
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void bnx2x_dcbx_update(struct work_struct *work);
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void bnx2x_dcbx_init_params(struct bnx2x *bp);
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enum {
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BNX2X_DCBX_STATE_NEG_RECEIVED = 0x1,
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BNX2X_DCBX_STATE_TX_PAUSED = 0x2,
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BNX2X_DCBX_STATE_TX_RELEASED = 0x4
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};
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void bnx2x_dcbx_set_params(struct bnx2x *bp, u32 state);
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#endif /* BNX2X_DCB_H */
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@ -684,7 +684,7 @@ struct shm_dev_info { /* size */
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#define E1VN_MAX 1
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#define E1HVN_MAX 4
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#define E2_VF_MAX 64
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/* This value (in milliseconds) determines the frequency of the driver
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* issuing the PULSE message code. The firmware monitors this periodic
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* pulse to determine when to switch to an OS-absent mode. */
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@ -820,6 +820,8 @@ struct drv_func_mb {
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#define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
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#define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
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#define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
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#define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
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#define DRV_MSG_CODE_SET_MF_BW 0xe0000000
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#define REQ_BC_VER_4_SET_MF_BW 0x00060202
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#define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
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@ -905,6 +907,8 @@ struct drv_func_mb {
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#define DRV_STATUS_DCC_RESERVED1 0x00000800
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#define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
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#define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
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#define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
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#define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
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u32 virt_mac_upper;
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#define VIRT_MAC_SIGN_MASK 0xffff0000
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@ -1089,6 +1093,251 @@ struct fw_flr_mb {
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struct fw_flr_ack ack;
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};
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/**** SUPPORT FOR SHMEM ARRRAYS ***
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* The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
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* define arrays with storage types smaller then unsigned dwords.
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* The macros below add generic support for SHMEM arrays with numeric elements
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* that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
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* array with individual bit-filed elements accessed using shifts and masks.
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*
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*/
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/* eb is the bitwidth of a single element */
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#define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
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#define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
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/* the bit-position macro allows the used to flip the order of the arrays
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* elements on a per byte or word boundary.
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*
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* example: an array with 8 entries each 4 bit wide. This array will fit into
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* a single dword. The diagrmas below show the array order of the nibbles.
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*
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* SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
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*
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* | | | |
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* 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
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* | | | |
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*
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* SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
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*
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* | | | |
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* 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 |
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* | | | |
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*
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* SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
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*
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* | | | |
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* 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 |
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* | | | |
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*/
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#define SHMEM_ARRAY_BITPOS(i, eb, fb) \
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((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
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(((i)%((fb)/(eb))) * (eb)))
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#define SHMEM_ARRAY_GET(a, i, eb, fb) \
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((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
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SHMEM_ARRAY_MASK(eb))
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#define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
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do { \
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a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
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SHMEM_ARRAY_BITPOS(i, eb, fb)); \
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a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
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SHMEM_ARRAY_BITPOS(i, eb, fb)); \
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} while (0)
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/****START OF DCBX STRUCTURES DECLARATIONS****/
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#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
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#define DCBX_PRI_PG_BITWIDTH 4
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#define DCBX_PRI_PG_FBITS 8
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#define DCBX_PRI_PG_GET(a, i) \
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SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
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#define DCBX_PRI_PG_SET(a, i, val) \
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SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
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#define DCBX_MAX_NUM_PG_BW_ENTRIES 8
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#define DCBX_BW_PG_BITWIDTH 8
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#define DCBX_PG_BW_GET(a, i) \
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SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
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#define DCBX_PG_BW_SET(a, i, val) \
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SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
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#define DCBX_STRICT_PRI_PG 15
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#define DCBX_MAX_APP_PROTOCOL 16
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#define FCOE_APP_IDX 0
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#define ISCSI_APP_IDX 1
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#define PREDEFINED_APP_IDX_MAX 2
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struct dcbx_ets_feature {
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u32 enabled;
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u32 pg_bw_tbl[2];
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u32 pri_pg_tbl[1];
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};
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struct dcbx_pfc_feature {
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#ifdef __BIG_ENDIAN
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u8 pri_en_bitmap;
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#define DCBX_PFC_PRI_0 0x01
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#define DCBX_PFC_PRI_1 0x02
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#define DCBX_PFC_PRI_2 0x04
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#define DCBX_PFC_PRI_3 0x08
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#define DCBX_PFC_PRI_4 0x10
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#define DCBX_PFC_PRI_5 0x20
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#define DCBX_PFC_PRI_6 0x40
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#define DCBX_PFC_PRI_7 0x80
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u8 pfc_caps;
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u8 reserved;
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u8 enabled;
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#elif defined(__LITTLE_ENDIAN)
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u8 enabled;
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u8 reserved;
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u8 pfc_caps;
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u8 pri_en_bitmap;
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#define DCBX_PFC_PRI_0 0x01
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#define DCBX_PFC_PRI_1 0x02
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#define DCBX_PFC_PRI_2 0x04
|
||||
#define DCBX_PFC_PRI_3 0x08
|
||||
#define DCBX_PFC_PRI_4 0x10
|
||||
#define DCBX_PFC_PRI_5 0x20
|
||||
#define DCBX_PFC_PRI_6 0x40
|
||||
#define DCBX_PFC_PRI_7 0x80
|
||||
#endif
|
||||
};
|
||||
|
||||
struct dcbx_app_priority_entry {
|
||||
#ifdef __BIG_ENDIAN
|
||||
u16 app_id;
|
||||
u8 pri_bitmap;
|
||||
u8 appBitfield;
|
||||
#define DCBX_APP_ENTRY_VALID 0x01
|
||||
#define DCBX_APP_ENTRY_SF_MASK 0x30
|
||||
#define DCBX_APP_ENTRY_SF_SHIFT 4
|
||||
#define DCBX_APP_SF_ETH_TYPE 0x10
|
||||
#define DCBX_APP_SF_PORT 0x20
|
||||
#elif defined(__LITTLE_ENDIAN)
|
||||
u8 appBitfield;
|
||||
#define DCBX_APP_ENTRY_VALID 0x01
|
||||
#define DCBX_APP_ENTRY_SF_MASK 0x30
|
||||
#define DCBX_APP_ENTRY_SF_SHIFT 4
|
||||
#define DCBX_APP_SF_ETH_TYPE 0x10
|
||||
#define DCBX_APP_SF_PORT 0x20
|
||||
u8 pri_bitmap;
|
||||
u16 app_id;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct dcbx_app_priority_feature {
|
||||
#ifdef __BIG_ENDIAN
|
||||
u8 reserved;
|
||||
u8 default_pri;
|
||||
u8 tc_supported;
|
||||
u8 enabled;
|
||||
#elif defined(__LITTLE_ENDIAN)
|
||||
u8 enabled;
|
||||
u8 tc_supported;
|
||||
u8 default_pri;
|
||||
u8 reserved;
|
||||
#endif
|
||||
struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
|
||||
};
|
||||
|
||||
struct dcbx_features {
|
||||
struct dcbx_ets_feature ets;
|
||||
struct dcbx_pfc_feature pfc;
|
||||
struct dcbx_app_priority_feature app;
|
||||
};
|
||||
|
||||
struct lldp_params {
|
||||
#ifdef __BIG_ENDIAN
|
||||
u8 msg_fast_tx_interval;
|
||||
u8 msg_tx_hold;
|
||||
u8 msg_tx_interval;
|
||||
u8 admin_status;
|
||||
#define LLDP_TX_ONLY 0x01
|
||||
#define LLDP_RX_ONLY 0x02
|
||||
#define LLDP_TX_RX 0x03
|
||||
#define LLDP_DISABLED 0x04
|
||||
u8 reserved1;
|
||||
u8 tx_fast;
|
||||
u8 tx_crd_max;
|
||||
u8 tx_crd;
|
||||
#elif defined(__LITTLE_ENDIAN)
|
||||
u8 admin_status;
|
||||
#define LLDP_TX_ONLY 0x01
|
||||
#define LLDP_RX_ONLY 0x02
|
||||
#define LLDP_TX_RX 0x03
|
||||
#define LLDP_DISABLED 0x04
|
||||
u8 msg_tx_interval;
|
||||
u8 msg_tx_hold;
|
||||
u8 msg_fast_tx_interval;
|
||||
u8 tx_crd;
|
||||
u8 tx_crd_max;
|
||||
u8 tx_fast;
|
||||
u8 reserved1;
|
||||
#endif
|
||||
#define REM_CHASSIS_ID_STAT_LEN 4
|
||||
#define REM_PORT_ID_STAT_LEN 4
|
||||
u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
|
||||
u32 peer_port_id[REM_PORT_ID_STAT_LEN];
|
||||
};
|
||||
|
||||
struct lldp_dcbx_stat {
|
||||
#define LOCAL_CHASSIS_ID_STAT_LEN 2
|
||||
#define LOCAL_PORT_ID_STAT_LEN 2
|
||||
u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
|
||||
u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
|
||||
u32 num_tx_dcbx_pkts;
|
||||
u32 num_rx_dcbx_pkts;
|
||||
};
|
||||
|
||||
struct lldp_admin_mib {
|
||||
u32 ver_cfg_flags;
|
||||
#define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
|
||||
#define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
|
||||
#define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
|
||||
#define DCBX_ETS_RECO_TX_ENABLED 0x00000008
|
||||
#define DCBX_ETS_RECO_VALID 0x00000010
|
||||
#define DCBX_ETS_WILLING 0x00000020
|
||||
#define DCBX_PFC_WILLING 0x00000040
|
||||
#define DCBX_APP_WILLING 0x00000080
|
||||
#define DCBX_VERSION_CEE 0x00000100
|
||||
#define DCBX_VERSION_IEEE 0x00000200
|
||||
#define DCBX_DCBX_ENABLED 0x00000400
|
||||
#define DCBX_CEE_VERSION_MASK 0x0000f000
|
||||
#define DCBX_CEE_VERSION_SHIFT 12
|
||||
#define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
|
||||
#define DCBX_CEE_MAX_VERSION_SHIFT 16
|
||||
struct dcbx_features features;
|
||||
};
|
||||
|
||||
struct lldp_remote_mib {
|
||||
u32 prefix_seq_num;
|
||||
u32 flags;
|
||||
#define DCBX_ETS_TLV_RX 0x00000001
|
||||
#define DCBX_PFC_TLV_RX 0x00000002
|
||||
#define DCBX_APP_TLV_RX 0x00000004
|
||||
#define DCBX_ETS_RX_ERROR 0x00000010
|
||||
#define DCBX_PFC_RX_ERROR 0x00000020
|
||||
#define DCBX_APP_RX_ERROR 0x00000040
|
||||
#define DCBX_ETS_REM_WILLING 0x00000100
|
||||
#define DCBX_PFC_REM_WILLING 0x00000200
|
||||
#define DCBX_APP_REM_WILLING 0x00000400
|
||||
#define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
|
||||
struct dcbx_features features;
|
||||
u32 suffix_seq_num;
|
||||
};
|
||||
|
||||
struct lldp_local_mib {
|
||||
u32 prefix_seq_num;
|
||||
u32 error;
|
||||
#define DCBX_LOCAL_ETS_ERROR 0x00000001
|
||||
#define DCBX_LOCAL_PFC_ERROR 0x00000002
|
||||
#define DCBX_LOCAL_APP_ERROR 0x00000004
|
||||
#define DCBX_LOCAL_PFC_MISMATCH 0x00000010
|
||||
#define DCBX_LOCAL_APP_MISMATCH 0x00000020
|
||||
struct dcbx_features features;
|
||||
u32 suffix_seq_num;
|
||||
};
|
||||
/***END OF DCBX STRUCTURES DECLARATIONS***/
|
||||
|
||||
struct shmem2_region {
|
||||
|
||||
@ -1112,7 +1361,12 @@ struct shmem2_region {
|
||||
#define SHMEM_MF_CFG_ADDR_NONE 0x00000000
|
||||
|
||||
struct fw_flr_mb flr_mb;
|
||||
u32 reserved[3];
|
||||
u32 dcbx_lldp_params_offset;
|
||||
#define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
|
||||
u32 dcbx_neg_res_offset;
|
||||
#define SHMEM_DCBX_NEG_RES_NONE 0x00000000
|
||||
u32 dcbx_remote_mib_offset;
|
||||
#define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
|
||||
/*
|
||||
* The other shmemX_base_addr holds the other path's shmem address
|
||||
* required for example in case of common phy init, or for path1 to know
|
||||
@ -1121,6 +1375,10 @@ struct shmem2_region {
|
||||
*/
|
||||
u32 other_shmem_base_addr;
|
||||
u32 other_shmem2_base_addr;
|
||||
u32 reserved1[E2_VF_MAX / 32];
|
||||
u32 reserved2[E2_FUNC_MAX][E2_VF_MAX / 32];
|
||||
u32 dcbx_lldp_dcbx_stat_offset;
|
||||
#define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
|
||||
};
|
||||
|
||||
|
||||
@ -3022,6 +3280,25 @@ struct fairness_vars_per_vn {
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* The data for flow control configuration
|
||||
*/
|
||||
struct flow_control_configuration {
|
||||
struct priority_cos
|
||||
traffic_type_to_priority_cos[MAX_PFC_TRAFFIC_TYPES];
|
||||
#if defined(__BIG_ENDIAN)
|
||||
u16 reserved1;
|
||||
u8 dcb_version;
|
||||
u8 dcb_enabled;
|
||||
#elif defined(__LITTLE_ENDIAN)
|
||||
u8 dcb_enabled;
|
||||
u8 dcb_version;
|
||||
u16 reserved1;
|
||||
#endif
|
||||
u32 reserved2;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* FW version stored in the Xstorm RAM
|
||||
*/
|
||||
|
||||
@ -216,6 +216,7 @@ struct link_params {
|
||||
|
||||
u32 feature_config_flags;
|
||||
#define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
|
||||
#define FEATURE_CONFIG_PFC_ENABLED (1<<1)
|
||||
#define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
|
||||
#define FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
|
||||
/* Will be populated during common init */
|
||||
@ -332,4 +333,43 @@ u8 bnx2x_phy_probe(struct link_params *params);
|
||||
u8 bnx2x_fan_failure_det_req(struct bnx2x *bp, u32 shmem_base,
|
||||
u32 shmem2_base, u8 port);
|
||||
|
||||
/* PFC port configuration params */
|
||||
struct bnx2x_nig_brb_pfc_port_params {
|
||||
/* NIG */
|
||||
u32 pause_enable;
|
||||
u32 llfc_out_en;
|
||||
u32 llfc_enable;
|
||||
u32 pkt_priority_to_cos;
|
||||
u32 rx_cos0_priority_mask;
|
||||
u32 rx_cos1_priority_mask;
|
||||
u32 llfc_high_priority_classes;
|
||||
u32 llfc_low_priority_classes;
|
||||
/* BRB */
|
||||
u32 cos0_pauseable;
|
||||
u32 cos1_pauseable;
|
||||
};
|
||||
|
||||
/**
|
||||
* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
|
||||
* when link is already up
|
||||
*/
|
||||
void bnx2x_update_pfc(struct link_params *params,
|
||||
struct link_vars *vars,
|
||||
struct bnx2x_nig_brb_pfc_port_params *pfc_params);
|
||||
|
||||
|
||||
/* Used to configure the ETS to disable */
|
||||
void bnx2x_ets_disabled(struct link_params *params);
|
||||
|
||||
/* Used to configure the ETS to BW limited */
|
||||
void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
|
||||
const u32 cos1_bw);
|
||||
|
||||
/* Used to configure the ETS to strict */
|
||||
u8 bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos);
|
||||
|
||||
/* Read pfc statistic*/
|
||||
void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
|
||||
u32 pfc_frames_sent[2],
|
||||
u32 pfc_frames_received[2]);
|
||||
#endif /* BNX2X_LINK_H */
|
||||
|
||||
@ -55,6 +55,7 @@
|
||||
#include "bnx2x_init.h"
|
||||
#include "bnx2x_init_ops.h"
|
||||
#include "bnx2x_cmn.h"
|
||||
#include "bnx2x_dcb.h"
|
||||
|
||||
#include <linux/firmware.h>
|
||||
#include "bnx2x_fw_file_hdr.h"
|
||||
@ -3105,6 +3106,11 @@ static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
|
||||
if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
|
||||
bnx2x_pmf_update(bp);
|
||||
|
||||
if (bp->port.pmf &&
|
||||
(val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS))
|
||||
/* start dcbx state machine */
|
||||
bnx2x_dcbx_set_params(bp,
|
||||
BNX2X_DCBX_STATE_NEG_RECEIVED);
|
||||
} else if (attn & BNX2X_MC_ASSERT_BITS) {
|
||||
|
||||
BNX2X_ERR("MC assert!\n");
|
||||
@ -3724,6 +3730,15 @@ static void bnx2x_eq_int(struct bnx2x *bp)
|
||||
BNX2X_FP_STATE_CLOSED;
|
||||
|
||||
goto next_spqe;
|
||||
|
||||
case EVENT_RING_OPCODE_STOP_TRAFFIC:
|
||||
DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
|
||||
bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
|
||||
goto next_spqe;
|
||||
case EVENT_RING_OPCODE_START_TRAFFIC:
|
||||
DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
|
||||
bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
|
||||
goto next_spqe;
|
||||
}
|
||||
|
||||
switch (opcode | bp->state) {
|
||||
@ -4363,6 +4378,7 @@ static void bnx2x_init_internal_common(struct bnx2x *bp)
|
||||
static void bnx2x_init_internal_port(struct bnx2x *bp)
|
||||
{
|
||||
/* port */
|
||||
bnx2x_dcb_init_intmem_pfc(bp);
|
||||
}
|
||||
|
||||
static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
|
||||
@ -5488,8 +5504,10 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
|
||||
* - SF mode: bits 3-7 are masked. only bits 0-2 are in use
|
||||
* - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
|
||||
* bits 4-7 are used for "per vn group attention" */
|
||||
REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4,
|
||||
(IS_MF(bp) ? 0xF7 : 0x7));
|
||||
val = IS_MF(bp) ? 0xF7 : 0x7;
|
||||
/* Enable DCBX attention for all but E1 */
|
||||
val |= CHIP_IS_E1(bp) ? 0 : 0x10;
|
||||
REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
|
||||
|
||||
bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
|
||||
bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
|
||||
@ -8775,6 +8793,8 @@ static int __devinit bnx2x_init_bp(struct bnx2x *bp)
|
||||
bp->timer.data = (unsigned long) bp;
|
||||
bp->timer.function = bnx2x_timer;
|
||||
|
||||
bnx2x_dcbx_init_params(bp);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user