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clk: qoriq: modify MAX_PLL_DIV to 32

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On LS2088A, Watchdog need clk divided by 32,
so modify MAX_PLL_DIV to 32

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Link: https://lore.kernel.org/r/20200916030311.17280-1-qiang.zhao@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Zhao Qiang 2020-09-16 11:03:10 +08:00 committed by Stephen Boyd
parent 9123e3a74e
commit e9501b975a
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/clk-qoriq.c
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@ -31,7 +31,7 @@
#define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
#define CGB_PLL1 4
#define CGB_PLL2 5
#define MAX_PLL_DIV 16
#define MAX_PLL_DIV 32
struct clockgen_pll_div {
struct clk *clk;