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net: stmmac: overwrite the dma_cap.addr64 according to HW design
The current IP register MAC_HW_Feature1[ADDR64] only defines
32/40/64 bit width, but some SOCs support others like i.MX8MP
support 34 bits but it maps to 40 bits width in MAC_HW_Feature1[ADDR64].
So overwrite dma_cap.addr64 according to HW real design.
Fixes: 94abdad697
("net: ethernet: dwmac: add ethernet glue logic for NXP imx8 chip")
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
5f58591323
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f119cc9818
@ -246,13 +246,7 @@ static int imx_dwmac_probe(struct platform_device *pdev)
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goto err_parse_dt;
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}
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ret = dma_set_mask_and_coherent(&pdev->dev,
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DMA_BIT_MASK(dwmac->ops->addr_width));
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if (ret) {
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dev_err(&pdev->dev, "DMA mask set failed\n");
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goto err_dma_mask;
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}
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plat_dat->addr64 = dwmac->ops->addr_width;
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plat_dat->init = imx_dwmac_init;
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plat_dat->exit = imx_dwmac_exit;
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plat_dat->fix_mac_speed = imx_dwmac_fix_speed;
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@ -272,7 +266,6 @@ static int imx_dwmac_probe(struct platform_device *pdev)
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err_dwmac_init:
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err_drv_probe:
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imx_dwmac_exit(pdev, plat_dat->bsp_priv);
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err_dma_mask:
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err_parse_dt:
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err_match_data:
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stmmac_remove_config_dt(pdev, plat_dat);
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@ -4945,6 +4945,14 @@ int stmmac_dvr_probe(struct device *device,
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dev_info(priv->device, "SPH feature enabled\n");
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}
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/* The current IP register MAC_HW_Feature1[ADDR64] only define
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* 32/40/64 bit width, but some SOC support others like i.MX8MP
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* support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64].
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* So overwrite dma_cap.addr64 according to HW real design.
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*/
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if (priv->plat->addr64)
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priv->dma_cap.addr64 = priv->plat->addr64;
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if (priv->dma_cap.addr64) {
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ret = dma_set_mask_and_coherent(device,
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DMA_BIT_MASK(priv->dma_cap.addr64));
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@ -170,6 +170,7 @@ struct plat_stmmacenet_data {
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int unicast_filter_entries;
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int tx_fifo_size;
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int rx_fifo_size;
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u32 addr64;
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u32 rx_queues_to_use;
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u32 tx_queues_to_use;
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u8 rx_sched_algorithm;
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