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clk: samsung: Improve clk-cpu.c style
clk-cpu.c has numerous style issues reported by checkpatch and easily identified otherwise. Give it some love and fix those warnings where it makes sense. Also make stabilization time a named constant to get rid of the magic number in clk-cpu.c. No functional change. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Link: https://lore.kernel.org/r/20240224202053.25313-3-semen.protsenko@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Sam Protsenko
Krzysztof Kozlowski
parent
76dedb9c0b
commit
f707e891eb
@ -16,18 +16,18 @@
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* of the SoC or supplied after the SoC characterization.
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*
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* The below implementation of the CPU clock allows the rate changes of the CPU
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* clock and the corresponding rate changes of the auxillary clocks of the CPU
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* clock and the corresponding rate changes of the auxiliary clocks of the CPU
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* domain. The platform clock driver provides a clock register configuration
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* for each configurable rate which is then used to program the clock hardware
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* registers to acheive a fast co-oridinated rate change for all the CPU domain
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* registers to achieve a fast coordinated rate change for all the CPU domain
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* clocks.
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*
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* On a rate change request for the CPU clock, the rate change is propagated
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* upto the PLL supplying the clock to the CPU domain clock blocks. While the
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* up to the PLL supplying the clock to the CPU domain clock blocks. While the
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* CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
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* alternate clock source. If required, the alternate clock source is divided
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* down in order to keep the output clock rate within the previous OPP limits.
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*/
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*/
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#include <linux/errno.h>
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#include <linux/io.h>
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@ -50,17 +50,19 @@
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#define E5433_DIV_STAT_CPU0 0x500
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#define E5433_DIV_STAT_CPU1 0x504
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#define E4210_DIV0_RATIO0_MASK 0x7
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#define E4210_DIV1_HPM_MASK (0x7 << 4)
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#define E4210_DIV1_COPY_MASK (0x7 << 0)
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#define E4210_MUX_HPM_MASK (1 << 20)
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#define E4210_DIV0_RATIO0_MASK GENMASK(2, 0)
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#define E4210_DIV1_HPM_MASK GENMASK(6, 4)
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#define E4210_DIV1_COPY_MASK GENMASK(2, 0)
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#define E4210_MUX_HPM_MASK BIT(20)
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#define E4210_DIV0_ATB_SHIFT 16
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#define E4210_DIV0_ATB_MASK (DIV_MASK << E4210_DIV0_ATB_SHIFT)
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/* Divider stabilization time, msec */
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#define MAX_STAB_TIME 10
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#define MAX_DIV 8
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#define DIV_MASK 7
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#define DIV_MASK_ALL 0xffffffff
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#define MUX_MASK 7
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#define DIV_MASK GENMASK(2, 0)
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#define DIV_MASK_ALL GENMASK(31, 0)
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#define MUX_MASK GENMASK(2, 0)
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/*
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* Helper function to wait until divider(s) have stabilized after the divider
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@ -68,7 +70,7 @@
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*/
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static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(10);
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unsigned long timeout = jiffies + msecs_to_jiffies(MAX_STAB_TIME);
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do {
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if (!(readl(div_reg) & mask))
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@ -86,9 +88,9 @@ static void wait_until_divider_stable(void __iomem *div_reg, unsigned long mask)
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* value was changed.
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*/
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static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
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unsigned long mux_value)
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unsigned long mux_value)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(10);
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unsigned long timeout = jiffies + msecs_to_jiffies(MAX_STAB_TIME);
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do {
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if (((readl(mux_reg) >> mux_pos) & MUX_MASK) == mux_value)
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@ -101,18 +103,18 @@ static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
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pr_err("%s: re-parenting mux timed-out\n", __func__);
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}
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/* common round rate callback useable for all types of CPU clocks */
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static long exynos_cpuclk_round_rate(struct clk_hw *hw,
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unsigned long drate, unsigned long *prate)
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/* common round rate callback usable for all types of CPU clocks */
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static long exynos_cpuclk_round_rate(struct clk_hw *hw, unsigned long drate,
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unsigned long *prate)
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{
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struct clk_hw *parent = clk_hw_get_parent(hw);
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*prate = clk_hw_round_rate(parent, drate);
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return *prate;
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}
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/* common recalc rate callback useable for all types of CPU clocks */
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/* common recalc rate callback usable for all types of CPU clocks */
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static unsigned long exynos_cpuclk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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unsigned long parent_rate)
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{
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/*
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* The CPU clock output (armclk) rate is the same as its parent
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@ -135,7 +137,7 @@ static const struct clk_ops exynos_cpuclk_clk_ops = {
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* dividers to be programmed.
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*/
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static void exynos_set_safe_div(void __iomem *base, unsigned long div,
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unsigned long mask)
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unsigned long mask)
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{
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unsigned long div0;
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@ -151,7 +153,6 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
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{
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const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
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unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
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unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
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unsigned long div0, div1 = 0, mux_reg;
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unsigned long flags;
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@ -187,6 +188,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
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*/
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if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
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unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
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unsigned long alt_div, alt_div_mask = DIV_MASK;
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alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
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WARN_ON(alt_div >= MAX_DIV);
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@ -215,7 +217,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
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if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
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writel(div1, base + E4210_DIV_CPU1);
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wait_until_divider_stable(base + E4210_DIV_STAT_CPU1,
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DIV_MASK_ALL);
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DIV_MASK_ALL);
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}
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spin_unlock_irqrestore(cpuclk->lock, flags);
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@ -263,7 +265,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
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* dividers to be programmed.
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*/
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static void exynos5433_set_safe_div(void __iomem *base, unsigned long div,
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unsigned long mask)
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unsigned long mask)
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{
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unsigned long div0;
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@ -279,7 +281,6 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
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{
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const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
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unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
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unsigned long alt_div = 0, alt_div_mask = DIV_MASK;
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unsigned long div0, div1 = 0, mux_reg;
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unsigned long flags;
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@ -309,6 +310,7 @@ static int exynos5433_cpuclk_pre_rate_change(struct clk_notifier_data *ndata,
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*/
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if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
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unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
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unsigned long alt_div, alt_div_mask = DIV_MASK;
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alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
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WARN_ON(alt_div >= MAX_DIV);
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@ -358,7 +360,7 @@ static int exynos5433_cpuclk_post_rate_change(struct clk_notifier_data *ndata,
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* notifications of the parent clock of cpuclk.
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*/
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static int exynos_cpuclk_notifier_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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unsigned long event, void *data)
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{
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struct clk_notifier_data *ndata = data;
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struct exynos_cpuclk *cpuclk;
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@ -381,7 +383,7 @@ static int exynos_cpuclk_notifier_cb(struct notifier_block *nb,
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* notifications of the parent clock of cpuclk.
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*/
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static int exynos5433_cpuclk_notifier_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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unsigned long event, void *data)
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{
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struct clk_notifier_data *ndata = data;
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struct exynos_cpuclk *cpuclk;
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@ -438,11 +440,10 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
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else
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cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
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ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb);
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if (ret) {
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pr_err("%s: failed to register clock notifier for %s\n",
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__func__, name);
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__func__, name);
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goto free_cpuclk;
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}
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@ -454,7 +455,7 @@ static int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx,
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ret = clk_hw_register(NULL, &cpuclk->hw);
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if (ret) {
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pr_err("%s: could not register cpuclk %s\n", __func__, name);
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pr_err("%s: could not register cpuclk %s\n", __func__, name);
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goto free_cpuclk_data;
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}
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@ -482,8 +483,8 @@ void __init samsung_clk_register_cpu(struct samsung_clk_provider *ctx,
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for (num_cfgs = 0; list->cfg[num_cfgs].prate != 0; )
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num_cfgs++;
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exynos_register_cpu_clock(ctx, list->id, list->name, hws[list->parent_id],
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hws[list->alt_parent_id], list->offset, list->cfg, num_cfgs,
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list->flags);
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exynos_register_cpu_clock(ctx, list->id, list->name,
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hws[list->parent_id], hws[list->alt_parent_id],
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list->offset, list->cfg, num_cfgs, list->flags);
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}
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}
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