mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
synced 2025-01-08 15:04:45 +00:00
17ed808ad2 ("EDAC: Fix reference count leaks")
e370f886fe("EDAC: Remove edac_get_dimm_by_index()")b9cae27728("EDAC/ghes: Scan the system once on driver init")b001694d60("EDAC/ghes: Remove unused members of struct ghes_edac_pvt, rename it to ghes_pvt")cb51a371d0("EDAC/ghes: Setup DIMM label from DMI and use it in error reports")8807e15597("EDAC, {skx,i10nm}: Use CPU stepping macro to pass configurations")e9ff6636d3("EDAC/mc: Call edac_inc_ue_error() before panic")30bf38e434("EDAC, pnd2: Set MCE_PRIO_EDAC priority for pnd2_mce_dec notifier") -----BEGIN PGP SIGNATURE----- iIoEABYIADIWIQQW3WBGcnu5yJnSXn0kTJLX0iGMLAUCXyNSJxQcdG9ueS5sdWNr QGludGVsLmNvbQAKCRAkTJLX0iGMLLX+AP0RHxHv0kYI8EScLpdHFnoGAKdKJ8Zb UmTTWqz4GwdoFgD/VIQ/RueIfsV+Hlqj+U+84+NJwPEcbJxY6WLo9ZHUkgc= =aFwG -----END PGP SIGNATURE----- Merge tag 'edac_updates_for_5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras Pull EDAC updates from Tony Luck: "Boris is on vacation and aske me to send you the EDAC changes" * tag 'edac_updates_for_5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/ras/ras: EDAC: Fix reference count leaks EDAC: Remove edac_get_dimm_by_index() EDAC/ghes: Scan the system once on driver init EDAC/ghes: Remove unused members of struct ghes_edac_pvt, rename it to ghes_pvt EDAC/ghes: Setup DIMM label from DMI and use it in error reports EDAC, {skx,i10nm}: Use CPU stepping macro to pass configurations EDAC/mc: Call edac_inc_ue_error() before panic EDAC, pnd2: Set MCE_PRIO_EDAC priority for pnd2_mce_dec notifier
This commit is contained in:
Linus Torvalds
commit
f8851cb2d0
@ -275,6 +275,7 @@ int edac_device_register_sysfs_main_kobj(struct edac_device_ctl_info *edac_dev)
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/* Error exit stack */
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err_kobj_reg:
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kobject_put(&edac_dev->kobj);
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module_put(edac_dev->owner);
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err_out:
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@ -950,6 +950,8 @@ static void edac_ue_error(struct edac_raw_error_desc *e)
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e->other_detail);
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}
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edac_inc_ue_error(e);
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if (edac_mc_get_panic_on_ue()) {
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panic("UE %s%son %s (%s page:0x%lx offset:0x%lx grain:%ld%s%s)\n",
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e->msg,
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@ -959,8 +961,6 @@ static void edac_ue_error(struct edac_raw_error_desc *e)
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*e->other_detail ? " - " : "",
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e->other_detail);
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}
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edac_inc_ue_error(e);
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}
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static void edac_inc_csrow(struct edac_raw_error_desc *e, int row, int chan)
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@ -386,7 +386,7 @@ static int edac_pci_main_kobj_setup(void)
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/* Error unwind statck */
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kobject_init_and_add_fail:
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kfree(edac_pci_top_main_kobj);
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kobject_put(edac_pci_top_main_kobj);
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kzalloc_fail:
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module_put(THIS_MODULE);
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@ -15,9 +15,7 @@
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#include "edac_module.h"
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#include <ras/ras_event.h>
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struct ghes_edac_pvt {
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struct list_head list;
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struct ghes *ghes;
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struct ghes_pvt {
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struct mem_ctl_info *mci;
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/* Buffers for the error handling routine */
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@ -32,7 +30,16 @@ static refcount_t ghes_refcount = REFCOUNT_INIT(0);
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* also provides the necessary (implicit) memory barrier for the SMP
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* case to make the pointer visible on another CPU.
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*/
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static struct ghes_edac_pvt *ghes_pvt;
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static struct ghes_pvt *ghes_pvt;
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/*
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* This driver's representation of the system hardware, as collected
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* from DMI.
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*/
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struct ghes_hw_desc {
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int num_dimms;
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struct dimm_info *dimms;
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} ghes_hw;
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/* GHES registration mutex */
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static DEFINE_MUTEX(ghes_reg_mutex);
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@ -74,136 +81,165 @@ struct memdev_dmi_entry {
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u16 conf_mem_clk_speed;
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} __attribute__((__packed__));
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struct ghes_edac_dimm_fill {
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struct mem_ctl_info *mci;
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unsigned int count;
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};
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static void ghes_edac_count_dimms(const struct dmi_header *dh, void *arg)
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{
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int *num_dimm = arg;
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if (dh->type == DMI_ENTRY_MEM_DEVICE)
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(*num_dimm)++;
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}
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static int get_dimm_smbios_index(struct mem_ctl_info *mci, u16 handle)
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static struct dimm_info *find_dimm_by_handle(struct mem_ctl_info *mci, u16 handle)
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{
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struct dimm_info *dimm;
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mci_for_each_dimm(mci, dimm) {
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if (dimm->smbios_handle == handle)
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return dimm->idx;
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return dimm;
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}
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return -1;
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return NULL;
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}
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static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg)
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static void dimm_setup_label(struct dimm_info *dimm, u16 handle)
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{
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struct ghes_edac_dimm_fill *dimm_fill = arg;
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struct mem_ctl_info *mci = dimm_fill->mci;
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const char *bank = NULL, *device = NULL;
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if (dh->type == DMI_ENTRY_MEM_DEVICE) {
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struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
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struct dimm_info *dimm = edac_get_dimm(mci, dimm_fill->count, 0, 0);
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u16 rdr_mask = BIT(7) | BIT(13);
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dmi_memdev_name(handle, &bank, &device);
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if (entry->size == 0xffff) {
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pr_info("Can't get DIMM%i size\n",
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dimm_fill->count);
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dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
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} else if (entry->size == 0x7fff) {
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dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
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} else {
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if (entry->size & BIT(15))
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dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
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else
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dimm->nr_pages = MiB_TO_PAGES(entry->size);
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}
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/* both strings must be non-zero */
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if (bank && *bank && device && *device)
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snprintf(dimm->label, sizeof(dimm->label), "%s %s", bank, device);
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}
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switch (entry->memory_type) {
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case 0x12:
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if (entry->type_detail & BIT(13))
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dimm->mtype = MEM_RDDR;
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else
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dimm->mtype = MEM_DDR;
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break;
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case 0x13:
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if (entry->type_detail & BIT(13))
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dimm->mtype = MEM_RDDR2;
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else
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dimm->mtype = MEM_DDR2;
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break;
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case 0x14:
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dimm->mtype = MEM_FB_DDR2;
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break;
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case 0x18:
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if (entry->type_detail & BIT(12))
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dimm->mtype = MEM_NVDIMM;
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else if (entry->type_detail & BIT(13))
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dimm->mtype = MEM_RDDR3;
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else
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dimm->mtype = MEM_DDR3;
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break;
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case 0x1a:
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if (entry->type_detail & BIT(12))
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dimm->mtype = MEM_NVDIMM;
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else if (entry->type_detail & BIT(13))
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dimm->mtype = MEM_RDDR4;
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else
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dimm->mtype = MEM_DDR4;
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break;
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default:
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if (entry->type_detail & BIT(6))
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dimm->mtype = MEM_RMBS;
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else if ((entry->type_detail & rdr_mask) == rdr_mask)
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dimm->mtype = MEM_RDR;
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else if (entry->type_detail & BIT(7))
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dimm->mtype = MEM_SDR;
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else if (entry->type_detail & BIT(9))
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dimm->mtype = MEM_EDO;
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else
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dimm->mtype = MEM_UNKNOWN;
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}
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static void assign_dmi_dimm_info(struct dimm_info *dimm, struct memdev_dmi_entry *entry)
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{
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u16 rdr_mask = BIT(7) | BIT(13);
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/*
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* Actually, we can only detect if the memory has bits for
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* checksum or not
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*/
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if (entry->total_width == entry->data_width)
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dimm->edac_mode = EDAC_NONE;
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if (entry->size == 0xffff) {
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pr_info("Can't get DIMM%i size\n", dimm->idx);
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dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
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} else if (entry->size == 0x7fff) {
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dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
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} else {
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if (entry->size & BIT(15))
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dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
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else
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dimm->edac_mode = EDAC_SECDED;
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dimm->nr_pages = MiB_TO_PAGES(entry->size);
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}
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dimm->dtype = DEV_UNKNOWN;
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dimm->grain = 128; /* Likely, worse case */
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switch (entry->memory_type) {
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case 0x12:
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if (entry->type_detail & BIT(13))
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dimm->mtype = MEM_RDDR;
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else
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dimm->mtype = MEM_DDR;
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break;
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case 0x13:
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if (entry->type_detail & BIT(13))
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dimm->mtype = MEM_RDDR2;
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else
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dimm->mtype = MEM_DDR2;
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break;
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case 0x14:
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dimm->mtype = MEM_FB_DDR2;
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break;
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case 0x18:
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if (entry->type_detail & BIT(12))
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dimm->mtype = MEM_NVDIMM;
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else if (entry->type_detail & BIT(13))
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dimm->mtype = MEM_RDDR3;
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else
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dimm->mtype = MEM_DDR3;
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break;
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case 0x1a:
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if (entry->type_detail & BIT(12))
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dimm->mtype = MEM_NVDIMM;
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else if (entry->type_detail & BIT(13))
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dimm->mtype = MEM_RDDR4;
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else
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dimm->mtype = MEM_DDR4;
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break;
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default:
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if (entry->type_detail & BIT(6))
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dimm->mtype = MEM_RMBS;
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else if ((entry->type_detail & rdr_mask) == rdr_mask)
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dimm->mtype = MEM_RDR;
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else if (entry->type_detail & BIT(7))
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dimm->mtype = MEM_SDR;
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else if (entry->type_detail & BIT(9))
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dimm->mtype = MEM_EDO;
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else
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dimm->mtype = MEM_UNKNOWN;
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}
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/*
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* FIXME: It shouldn't be hard to also fill the DIMM labels
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*/
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/*
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* Actually, we can only detect if the memory has bits for
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* checksum or not
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*/
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if (entry->total_width == entry->data_width)
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dimm->edac_mode = EDAC_NONE;
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else
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dimm->edac_mode = EDAC_SECDED;
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if (dimm->nr_pages) {
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edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
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dimm_fill->count, edac_mem_types[dimm->mtype],
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PAGES_TO_MiB(dimm->nr_pages),
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(dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
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edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
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entry->memory_type, entry->type_detail,
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entry->total_width, entry->data_width);
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dimm->dtype = DEV_UNKNOWN;
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dimm->grain = 128; /* Likely, worse case */
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dimm_setup_label(dimm, entry->handle);
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if (dimm->nr_pages) {
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edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
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dimm->idx, edac_mem_types[dimm->mtype],
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PAGES_TO_MiB(dimm->nr_pages),
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(dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
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edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
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entry->memory_type, entry->type_detail,
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entry->total_width, entry->data_width);
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}
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dimm->smbios_handle = entry->handle;
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}
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static void enumerate_dimms(const struct dmi_header *dh, void *arg)
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{
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struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
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struct ghes_hw_desc *hw = (struct ghes_hw_desc *)arg;
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struct dimm_info *d;
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if (dh->type != DMI_ENTRY_MEM_DEVICE)
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return;
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/* Enlarge the array with additional 16 */
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if (!hw->num_dimms || !(hw->num_dimms % 16)) {
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struct dimm_info *new;
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new = krealloc(hw->dimms, (hw->num_dimms + 16) * sizeof(struct dimm_info),
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GFP_KERNEL);
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if (!new) {
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WARN_ON_ONCE(1);
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return;
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}
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dimm->smbios_handle = entry->handle;
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dimm_fill->count++;
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hw->dimms = new;
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}
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d = &hw->dimms[hw->num_dimms];
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d->idx = hw->num_dimms;
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assign_dmi_dimm_info(d, entry);
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hw->num_dimms++;
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}
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static void ghes_scan_system(void)
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{
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static bool scanned;
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||||
if (scanned)
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||||
return;
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||||
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||||
dmi_walk(enumerate_dimms, &ghes_hw);
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||||
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||||
scanned = true;
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||||
}
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||||
void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
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{
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||||
struct edac_raw_error_desc *e;
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struct mem_ctl_info *mci;
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||||
struct ghes_edac_pvt *pvt;
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struct ghes_pvt *pvt;
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||||
unsigned long flags;
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||||
char *p;
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||||
|
||||
@ -228,7 +264,6 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
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||||
memset(e, 0, sizeof (*e));
|
||||
e->error_count = 1;
|
||||
e->grain = 1;
|
||||
strcpy(e->label, "unknown label");
|
||||
e->msg = pvt->msg;
|
||||
e->other_detail = pvt->other_detail;
|
||||
e->top_layer = -1;
|
||||
@ -345,7 +380,7 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
|
||||
p += sprintf(p, "bit_pos:%d ", mem_err->bit_pos);
|
||||
if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
|
||||
const char *bank = NULL, *device = NULL;
|
||||
int index = -1;
|
||||
struct dimm_info *dimm;
|
||||
|
||||
dmi_memdev_name(mem_err->mem_dev_handle, &bank, &device);
|
||||
if (bank != NULL && device != NULL)
|
||||
@ -354,13 +389,18 @@ void ghes_edac_report_mem_error(int sev, struct cper_sec_mem_err *mem_err)
|
||||
p += sprintf(p, "DIMM DMI handle: 0x%.4x ",
|
||||
mem_err->mem_dev_handle);
|
||||
|
||||
index = get_dimm_smbios_index(mci, mem_err->mem_dev_handle);
|
||||
if (index >= 0)
|
||||
e->top_layer = index;
|
||||
dimm = find_dimm_by_handle(mci, mem_err->mem_dev_handle);
|
||||
if (dimm) {
|
||||
e->top_layer = dimm->idx;
|
||||
strcpy(e->label, dimm->label);
|
||||
}
|
||||
}
|
||||
if (p > e->location)
|
||||
*(p - 1) = '\0';
|
||||
|
||||
if (!*e->label)
|
||||
strcpy(e->label, "unknown memory");
|
||||
|
||||
/* All other fields are mapped on e->other_detail */
|
||||
p = pvt->other_detail;
|
||||
p += snprintf(p, sizeof(pvt->other_detail),
|
||||
@ -455,13 +495,12 @@ static struct acpi_platform_list plat_list[] = {
|
||||
int ghes_edac_register(struct ghes *ghes, struct device *dev)
|
||||
{
|
||||
bool fake = false;
|
||||
int rc = 0, num_dimm = 0;
|
||||
struct mem_ctl_info *mci;
|
||||
struct ghes_edac_pvt *pvt;
|
||||
struct ghes_pvt *pvt;
|
||||
struct edac_mc_layer layers[1];
|
||||
struct ghes_edac_dimm_fill dimm_fill;
|
||||
unsigned long flags;
|
||||
int idx = -1;
|
||||
int rc = 0;
|
||||
|
||||
if (IS_ENABLED(CONFIG_X86)) {
|
||||
/* Check if safe to enable on this system */
|
||||
@ -481,20 +520,19 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev)
|
||||
if (refcount_inc_not_zero(&ghes_refcount))
|
||||
goto unlock;
|
||||
|
||||
/* Get the number of DIMMs */
|
||||
dmi_walk(ghes_edac_count_dimms, &num_dimm);
|
||||
ghes_scan_system();
|
||||
|
||||
/* Check if we've got a bogus BIOS */
|
||||
if (num_dimm == 0) {
|
||||
if (!ghes_hw.num_dimms) {
|
||||
fake = true;
|
||||
num_dimm = 1;
|
||||
ghes_hw.num_dimms = 1;
|
||||
}
|
||||
|
||||
layers[0].type = EDAC_MC_LAYER_ALL_MEM;
|
||||
layers[0].size = num_dimm;
|
||||
layers[0].size = ghes_hw.num_dimms;
|
||||
layers[0].is_virt_csrow = true;
|
||||
|
||||
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_edac_pvt));
|
||||
mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_pvt));
|
||||
if (!mci) {
|
||||
pr_info("Can't allocate memory for EDAC data\n");
|
||||
rc = -ENOMEM;
|
||||
@ -502,7 +540,6 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev)
|
||||
}
|
||||
|
||||
pvt = mci->pvt_info;
|
||||
pvt->ghes = ghes;
|
||||
pvt->mci = mci;
|
||||
|
||||
mci->pdev = dev;
|
||||
@ -523,13 +560,34 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev)
|
||||
pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
|
||||
pr_info("If you find incorrect reports, please contact your hardware vendor\n");
|
||||
pr_info("to correct its BIOS.\n");
|
||||
pr_info("This system has %d DIMM sockets.\n", num_dimm);
|
||||
pr_info("This system has %d DIMM sockets.\n", ghes_hw.num_dimms);
|
||||
}
|
||||
|
||||
if (!fake) {
|
||||
dimm_fill.count = 0;
|
||||
dimm_fill.mci = mci;
|
||||
dmi_walk(ghes_edac_dmidecode, &dimm_fill);
|
||||
struct dimm_info *src, *dst;
|
||||
int i = 0;
|
||||
|
||||
mci_for_each_dimm(mci, dst) {
|
||||
src = &ghes_hw.dimms[i];
|
||||
|
||||
dst->idx = src->idx;
|
||||
dst->smbios_handle = src->smbios_handle;
|
||||
dst->nr_pages = src->nr_pages;
|
||||
dst->mtype = src->mtype;
|
||||
dst->edac_mode = src->edac_mode;
|
||||
dst->dtype = src->dtype;
|
||||
dst->grain = src->grain;
|
||||
|
||||
/*
|
||||
* If no src->label, preserve default label assigned
|
||||
* from EDAC core.
|
||||
*/
|
||||
if (strlen(src->label))
|
||||
memcpy(dst->label, src->label, sizeof(src->label));
|
||||
|
||||
i++;
|
||||
}
|
||||
|
||||
} else {
|
||||
struct dimm_info *dimm = edac_get_dimm(mci, 0, 0, 0);
|
||||
|
||||
@ -542,7 +600,7 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev)
|
||||
|
||||
rc = edac_mc_add_mc(mci);
|
||||
if (rc < 0) {
|
||||
pr_info("Can't register at EDAC core\n");
|
||||
pr_info("Can't register with the EDAC core\n");
|
||||
edac_mc_free(mci);
|
||||
rc = -ENODEV;
|
||||
goto unlock;
|
||||
@ -556,6 +614,11 @@ int ghes_edac_register(struct ghes *ghes, struct device *dev)
|
||||
refcount_set(&ghes_refcount, 1);
|
||||
|
||||
unlock:
|
||||
|
||||
/* Not needed anymore */
|
||||
kfree(ghes_hw.dimms);
|
||||
ghes_hw.dimms = NULL;
|
||||
|
||||
mutex_unlock(&ghes_reg_mutex);
|
||||
|
||||
return rc;
|
||||
|
||||
@ -135,9 +135,11 @@ static struct res_config i10nm_cfg1 = {
|
||||
};
|
||||
|
||||
static const struct x86_cpu_id i10nm_cpuids[] = {
|
||||
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &i10nm_cfg0),
|
||||
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &i10nm_cfg0),
|
||||
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &i10nm_cfg1),
|
||||
X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
|
||||
X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
|
||||
X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
|
||||
X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
|
||||
X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_D, X86_STEPPINGS(0x0, 0xf), &i10nm_cfg1),
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);
|
||||
@ -264,10 +266,6 @@ static int __init i10nm_init(void)
|
||||
|
||||
cfg = (struct res_config *)id->driver_data;
|
||||
|
||||
/* Newer steppings have different offset for ATOM_TREMONT_D/ICELAKE_X */
|
||||
if (boot_cpu_data.x86_stepping >= 4)
|
||||
cfg->busno_cfg_offset = 0xd0;
|
||||
|
||||
rc = skx_get_hi_lo(0x09a2, off, &tolm, &tohm);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
@ -1432,6 +1432,7 @@ static int pnd2_mce_check_error(struct notifier_block *nb, unsigned long val, vo
|
||||
|
||||
static struct notifier_block pnd2_mce_dec = {
|
||||
.notifier_call = pnd2_mce_check_error,
|
||||
.priority = MCE_PRIO_EDAC,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_EDAC_DEBUG
|
||||
|
||||
@ -164,7 +164,7 @@ static struct res_config skx_cfg = {
|
||||
};
|
||||
|
||||
static const struct x86_cpu_id skx_cpuids[] = {
|
||||
X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &skx_cfg),
|
||||
X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x0, 0xf), &skx_cfg),
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(x86cpu, skx_cpuids);
|
||||
|
||||
@ -594,27 +594,6 @@ struct mem_ctl_info {
|
||||
? (mci)->dimms[(dimm)->idx + 1] \
|
||||
: NULL)
|
||||
|
||||
/**
|
||||
* edac_get_dimm_by_index - Get DIMM info at @index from a memory
|
||||
* controller
|
||||
*
|
||||
* @mci: MC descriptor struct mem_ctl_info
|
||||
* @index: index in the memory controller's DIMM array
|
||||
*
|
||||
* Returns a struct dimm_info * or NULL on failure.
|
||||
*/
|
||||
static inline struct dimm_info *
|
||||
edac_get_dimm_by_index(struct mem_ctl_info *mci, int index)
|
||||
{
|
||||
if (index < 0 || index >= mci->tot_dimms)
|
||||
return NULL;
|
||||
|
||||
if (WARN_ON_ONCE(mci->dimms[index]->idx != index))
|
||||
return NULL;
|
||||
|
||||
return mci->dimms[index];
|
||||
}
|
||||
|
||||
/**
|
||||
* edac_get_dimm - Get DIMM info from a memory controller given by
|
||||
* [layer0,layer1,layer2] position
|
||||
@ -650,6 +629,12 @@ static inline struct dimm_info *edac_get_dimm(struct mem_ctl_info *mci,
|
||||
if (mci->n_layers > 2)
|
||||
index = index * mci->layers[2].size + layer2;
|
||||
|
||||
return edac_get_dimm_by_index(mci, index);
|
||||
if (index < 0 || index >= mci->tot_dimms)
|
||||
return NULL;
|
||||
|
||||
if (WARN_ON_ONCE(mci->dimms[index]->idx != index))
|
||||
return NULL;
|
||||
|
||||
return mci->dimms[index];
|
||||
}
|
||||
#endif /* _LINUX_EDAC_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user