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https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
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Two reverts and two EN7581 driver fixes:
- Revert the attempt to make CLK_GET_RATE_NOCACHE flag work in
clk_set_rate() because it led to problems with the Qualcomm CPUFreq
driver
- Revert Amlogic reset driver back to the initial implementation. This
broke probe of the audio subsystem on axg based platforms and also
had compilation problems. We'll try again next time.
- Fix a clk frequency and fix array bounds runtime checks in the Airoha
EN7581 driver
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"Two reverts and two EN7581 driver fixes:
- Revert the attempt to make CLK_GET_RATE_NOCACHE flag work in
clk_set_rate() because it led to problems with the Qualcomm CPUFreq
driver
- Revert Amlogic reset driver back to the initial implementation.
This broke probe of the audio subsystem on axg based platforms and
also had compilation problems. We'll try again next time.
- Fix a clk frequency and fix array bounds runtime checks in the
Airoha EN7581 driver"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: en7523: Initialize num before accessing hws in en7523_register_clocks()
clk: en7523: Fix wrong BUS clock for EN7581
clk: amlogic: axg-audio: revert reset implementation
Revert "clk: Fix invalid execution of clk_set_rate"
This commit is contained in:
Linus Torvalds
commit
f92f474986
@ -87,6 +87,7 @@ static const u32 slic_base[] = { 100000000, 3125000 };
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static const u32 npu_base[] = { 333000000, 400000000, 500000000 };
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/* EN7581 */
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static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 };
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static const u32 bus7581_base[] = { 600000000, 540000000 };
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static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
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static const u32 crypto_base[] = { 540000000, 480000000 };
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@ -222,8 +223,8 @@ static const struct en_clk_desc en7581_base_clks[] = {
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.base_reg = REG_BUS_CLK_DIV_SEL,
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.base_bits = 1,
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.base_shift = 8,
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.base_values = bus_base,
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.n_base_values = ARRAY_SIZE(bus_base),
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.base_values = bus7581_base,
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.n_base_values = ARRAY_SIZE(bus7581_base),
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.div_bits = 3,
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.div_shift = 0,
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@ -503,6 +504,8 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat
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u32 rate;
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int i;
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clk_data->num = EN7523_NUM_CLOCKS;
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for (i = 0; i < ARRAY_SIZE(en7523_base_clks); i++) {
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const struct en_clk_desc *desc = &en7523_base_clks[i];
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u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg;
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@ -524,8 +527,6 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat
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hw = en7523_register_pcie_clk(dev, np_base);
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clk_data->hws[EN7523_CLK_PCIE] = hw;
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clk_data->num = EN7523_NUM_CLOCKS;
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}
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static int en7523_clk_hw_init(struct platform_device *pdev,
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@ -2530,7 +2530,7 @@ static int clk_core_set_rate_nolock(struct clk_core *core,
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rate = clk_core_req_round_rate_nolock(core, req_rate);
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/* bail early if nothing to do */
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if (rate == clk_core_get_rate_recalc(core))
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if (rate == clk_core_get_rate_nolock(core))
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return 0;
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/* fail on a direct rate set of a protected provider */
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@ -106,7 +106,7 @@ config COMMON_CLK_AXG_AUDIO
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select COMMON_CLK_MESON_SCLK_DIV
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select COMMON_CLK_MESON_CLKC_UTILS
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select REGMAP_MMIO
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depends on RESET_MESON_AUX
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select RESET_CONTROLLER
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help
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Support for the audio clock controller on AmLogic A113D devices,
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aka axg, Say Y if you want audio subsystem to work.
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@ -15,8 +15,6 @@
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <soc/amlogic/reset-meson-aux.h>
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#include "meson-clkc-utils.h"
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#include "axg-audio.h"
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#include "clk-regmap.h"
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@ -1680,6 +1678,84 @@ static struct clk_regmap *const sm1_clk_regmaps[] = {
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&sm1_earcrx_dmac_clk,
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};
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struct axg_audio_reset_data {
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struct reset_controller_dev rstc;
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struct regmap *map;
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unsigned int offset;
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};
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static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst,
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unsigned long id,
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unsigned int *reg,
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unsigned int *bit)
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{
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unsigned int stride = regmap_get_reg_stride(rst->map);
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*reg = (id / (stride * BITS_PER_BYTE)) * stride;
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*reg += rst->offset;
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*bit = id % (stride * BITS_PER_BYTE);
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}
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static int axg_audio_reset_update(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct axg_audio_reset_data *rst =
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container_of(rcdev, struct axg_audio_reset_data, rstc);
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unsigned int offset, bit;
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axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
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regmap_update_bits(rst->map, offset, BIT(bit),
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assert ? BIT(bit) : 0);
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return 0;
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}
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static int axg_audio_reset_status(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct axg_audio_reset_data *rst =
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container_of(rcdev, struct axg_audio_reset_data, rstc);
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unsigned int val, offset, bit;
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axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
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regmap_read(rst->map, offset, &val);
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return !!(val & BIT(bit));
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}
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static int axg_audio_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return axg_audio_reset_update(rcdev, id, true);
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}
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static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return axg_audio_reset_update(rcdev, id, false);
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}
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static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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int ret;
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ret = axg_audio_reset_assert(rcdev, id);
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if (ret)
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return ret;
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return axg_audio_reset_deassert(rcdev, id);
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}
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static const struct reset_control_ops axg_audio_rstc_ops = {
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.assert = axg_audio_reset_assert,
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.deassert = axg_audio_reset_deassert,
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.reset = axg_audio_reset_toggle,
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.status = axg_audio_reset_status,
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};
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static struct regmap_config axg_audio_regmap_cfg = {
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.reg_bits = 32,
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.val_bits = 32,
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@ -1690,14 +1766,16 @@ struct audioclk_data {
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struct clk_regmap *const *regmap_clks;
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unsigned int regmap_clk_num;
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struct meson_clk_hw_data hw_clks;
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unsigned int reset_offset;
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unsigned int reset_num;
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unsigned int max_register;
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const char *rst_drvname;
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};
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static int axg_audio_clkc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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const struct audioclk_data *data;
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struct axg_audio_reset_data *rst;
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struct regmap *map;
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void __iomem *regs;
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struct clk_hw *hw;
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@ -1756,11 +1834,22 @@ static int axg_audio_clkc_probe(struct platform_device *pdev)
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if (ret)
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return ret;
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/* Register auxiliary reset driver when applicable */
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if (data->rst_drvname)
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ret = devm_meson_rst_aux_register(dev, map, data->rst_drvname);
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/* Stop here if there is no reset */
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if (!data->reset_num)
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return 0;
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return ret;
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rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
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if (!rst)
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return -ENOMEM;
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rst->map = map;
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rst->offset = data->reset_offset;
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rst->rstc.nr_resets = data->reset_num;
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rst->rstc.ops = &axg_audio_rstc_ops;
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rst->rstc.of_node = dev->of_node;
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rst->rstc.owner = THIS_MODULE;
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return devm_reset_controller_register(dev, &rst->rstc);
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}
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static const struct audioclk_data axg_audioclk_data = {
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@ -1780,8 +1869,9 @@ static const struct audioclk_data g12a_audioclk_data = {
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.hws = g12a_audio_hw_clks,
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.num = ARRAY_SIZE(g12a_audio_hw_clks),
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},
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.reset_offset = AUDIO_SW_RESET,
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.reset_num = 26,
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.max_register = AUDIO_CLK_SPDIFOUT_B_CTRL,
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.rst_drvname = "rst-g12a",
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};
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static const struct audioclk_data sm1_audioclk_data = {
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@ -1791,8 +1881,9 @@ static const struct audioclk_data sm1_audioclk_data = {
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.hws = sm1_audio_hw_clks,
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.num = ARRAY_SIZE(sm1_audio_hw_clks),
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},
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.reset_offset = AUDIO_SM1_SW_RESET0,
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.reset_num = 39,
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.max_register = AUDIO_EARCRX_DMAC_CLK_CTRL,
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.rst_drvname = "rst-sm1",
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};
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static const struct of_device_id clkc_match_table[] = {
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