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synced 2025-01-17 22:05:08 +00:00
RDMA/hns: Fix different dgids mapping to the same dip_idx
DIP algorithm requires a one-to-one mapping between dgid and dip_idx. Currently a queue 'spare_idx' is used to store QPN of QPs that use DIP algorithm. For a new dgid, use a QPN from spare_idx as dip_idx. This method lacks a mechanism for deduplicating QPN, which may result in different dgids sharing the same dip_idx and break the one-to-one mapping requirement. This patch replaces spare_idx with xarray and introduces a refcnt of a dip_idx to indicate the number of QPs that using this dip_idx. The state machine for dip_idx management is implemented as: * The entry at an index in xarray is empty -- This indicates that the corresponding dip_idx hasn't been created. * The entry at an index in xarray is not empty but with 0 refcnt -- This indicates that the corresponding dip_idx has been created but not used as dip_idx yet. * The entry at an index in xarray is not empty and with non-0 refcnt -- This indicates that the corresponding dip_idx is being used by refcnt number of DIP QPs. Fixes: eb653eda1e91 ("RDMA/hns: Bugfix for incorrect association between dip_idx and dgid") Fixes: f91696f2f053 ("RDMA/hns: Support congestion control type selection according to the FW") Signed-off-by: Feng Fang <fangfeng4@huawei.com> Signed-off-by: Junxian Huang <huangjunxian6@hisilicon.com> Link: https://patch.msgid.link/20241112055553.3681129-1-huangjunxian6@hisilicon.com Signed-off-by: Leon Romanovsky <leon@kernel.org>
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cdb21c12ad
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faa62440a5
@ -489,12 +489,6 @@ struct hns_roce_bank {
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u32 next; /* Next ID to allocate. */
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};
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struct hns_roce_idx_table {
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u32 *spare_idx;
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u32 head;
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u32 tail;
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};
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struct hns_roce_qp_table {
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struct hns_roce_hem_table qp_table;
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struct hns_roce_hem_table irrl_table;
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@ -503,7 +497,7 @@ struct hns_roce_qp_table {
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struct mutex scc_mutex;
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struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM];
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struct mutex bank_mutex;
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struct hns_roce_idx_table idx_table;
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struct xarray dip_xa;
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};
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struct hns_roce_cq_table {
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@ -658,6 +652,7 @@ struct hns_roce_qp {
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u8 tc_mode;
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u8 priority;
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spinlock_t flush_lock;
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struct hns_roce_dip *dip;
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};
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struct hns_roce_ib_iboe {
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@ -984,8 +979,6 @@ struct hns_roce_dev {
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enum hns_roce_device_state state;
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struct list_head qp_list; /* list of all qps on this dev */
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spinlock_t qp_list_lock; /* protect qp_list */
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struct list_head dip_list; /* list of all dest ips on this dev */
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spinlock_t dip_list_lock; /* protect dip_list */
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struct list_head pgdir_list;
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struct mutex pgdir_mutex;
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@ -2553,20 +2553,19 @@ static void hns_roce_free_link_table(struct hns_roce_dev *hr_dev)
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free_link_table_buf(hr_dev, &priv->ext_llm);
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}
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static void free_dip_list(struct hns_roce_dev *hr_dev)
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static void free_dip_entry(struct hns_roce_dev *hr_dev)
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{
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struct hns_roce_dip *hr_dip;
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struct hns_roce_dip *tmp;
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unsigned long flags;
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unsigned long idx;
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spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
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xa_lock(&hr_dev->qp_table.dip_xa);
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list_for_each_entry_safe(hr_dip, tmp, &hr_dev->dip_list, node) {
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list_del(&hr_dip->node);
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xa_for_each(&hr_dev->qp_table.dip_xa, idx, hr_dip) {
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__xa_erase(&hr_dev->qp_table.dip_xa, hr_dip->dip_idx);
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kfree(hr_dip);
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}
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spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
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xa_unlock(&hr_dev->qp_table.dip_xa);
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}
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static struct ib_pd *free_mr_init_pd(struct hns_roce_dev *hr_dev)
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@ -2974,7 +2973,7 @@ static void hns_roce_v2_exit(struct hns_roce_dev *hr_dev)
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hns_roce_free_link_table(hr_dev);
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if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP09)
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free_dip_list(hr_dev);
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free_dip_entry(hr_dev);
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}
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static int hns_roce_mbox_post(struct hns_roce_dev *hr_dev,
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@ -4694,26 +4693,49 @@ static int modify_qp_rtr_to_rts(struct ib_qp *ibqp, int attr_mask,
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return 0;
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}
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static int alloc_dip_entry(struct xarray *dip_xa, u32 qpn)
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{
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struct hns_roce_dip *hr_dip;
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int ret;
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hr_dip = xa_load(dip_xa, qpn);
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if (hr_dip)
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return 0;
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hr_dip = kzalloc(sizeof(*hr_dip), GFP_KERNEL);
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if (!hr_dip)
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return -ENOMEM;
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ret = xa_err(xa_store(dip_xa, qpn, hr_dip, GFP_KERNEL));
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if (ret)
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kfree(hr_dip);
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return ret;
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}
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static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
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u32 *dip_idx)
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{
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const struct ib_global_route *grh = rdma_ah_read_grh(&attr->ah_attr);
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struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
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u32 *spare_idx = hr_dev->qp_table.idx_table.spare_idx;
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u32 *head = &hr_dev->qp_table.idx_table.head;
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u32 *tail = &hr_dev->qp_table.idx_table.tail;
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struct xarray *dip_xa = &hr_dev->qp_table.dip_xa;
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struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
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struct hns_roce_dip *hr_dip;
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unsigned long flags;
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unsigned long idx;
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int ret = 0;
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spin_lock_irqsave(&hr_dev->dip_list_lock, flags);
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ret = alloc_dip_entry(dip_xa, ibqp->qp_num);
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if (ret)
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return ret;
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spare_idx[*tail] = ibqp->qp_num;
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*tail = (*tail == hr_dev->caps.num_qps - 1) ? 0 : (*tail + 1);
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xa_lock(dip_xa);
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list_for_each_entry(hr_dip, &hr_dev->dip_list, node) {
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if (!memcmp(grh->dgid.raw, hr_dip->dgid, GID_LEN_V2)) {
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xa_for_each(dip_xa, idx, hr_dip) {
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if (hr_dip->qp_cnt &&
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!memcmp(grh->dgid.raw, hr_dip->dgid, GID_LEN_V2)) {
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*dip_idx = hr_dip->dip_idx;
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hr_dip->qp_cnt++;
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hr_qp->dip = hr_dip;
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goto out;
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}
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}
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@ -4721,19 +4743,24 @@ static int get_dip_ctx_idx(struct ib_qp *ibqp, const struct ib_qp_attr *attr,
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/* If no dgid is found, a new dip and a mapping between dgid and
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* dip_idx will be created.
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*/
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hr_dip = kzalloc(sizeof(*hr_dip), GFP_ATOMIC);
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if (!hr_dip) {
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ret = -ENOMEM;
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goto out;
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xa_for_each(dip_xa, idx, hr_dip) {
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if (hr_dip->qp_cnt)
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continue;
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*dip_idx = idx;
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memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
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hr_dip->dip_idx = idx;
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hr_dip->qp_cnt++;
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hr_qp->dip = hr_dip;
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break;
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}
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memcpy(hr_dip->dgid, grh->dgid.raw, sizeof(grh->dgid.raw));
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hr_dip->dip_idx = *dip_idx = spare_idx[*head];
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*head = (*head == hr_dev->caps.num_qps - 1) ? 0 : (*head + 1);
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list_add_tail(&hr_dip->node, &hr_dev->dip_list);
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/* This should never happen. */
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if (WARN_ON_ONCE(!hr_qp->dip))
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ret = -ENOSPC;
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out:
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spin_unlock_irqrestore(&hr_dev->dip_list_lock, flags);
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xa_unlock(dip_xa);
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return ret;
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}
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@ -5587,6 +5614,20 @@ static int hns_roce_v2_destroy_qp_common(struct hns_roce_dev *hr_dev,
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return ret;
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}
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static void put_dip_ctx_idx(struct hns_roce_dev *hr_dev,
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struct hns_roce_qp *hr_qp)
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{
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struct hns_roce_dip *hr_dip = hr_qp->dip;
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xa_lock(&hr_dev->qp_table.dip_xa);
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hr_dip->qp_cnt--;
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if (!hr_dip->qp_cnt)
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memset(hr_dip->dgid, 0, GID_LEN_V2);
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xa_unlock(&hr_dev->qp_table.dip_xa);
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}
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int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
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{
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struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
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@ -5600,6 +5641,9 @@ int hns_roce_v2_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata)
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spin_unlock_irqrestore(&hr_qp->flush_lock, flags);
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flush_work(&hr_qp->flush_work.work);
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if (hr_qp->cong_type == CONG_TYPE_DIP)
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put_dip_ctx_idx(hr_dev, hr_qp);
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ret = hns_roce_v2_destroy_qp_common(hr_dev, hr_qp, udata);
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if (ret)
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ibdev_err_ratelimited(&hr_dev->ib_dev,
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@ -1348,7 +1348,7 @@ struct hns_roce_v2_priv {
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struct hns_roce_dip {
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u8 dgid[GID_LEN_V2];
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u32 dip_idx;
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struct list_head node; /* all dips are on a list */
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u32 qp_cnt;
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};
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struct fmea_ram_ecc {
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@ -1135,8 +1135,6 @@ int hns_roce_init(struct hns_roce_dev *hr_dev)
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INIT_LIST_HEAD(&hr_dev->qp_list);
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spin_lock_init(&hr_dev->qp_list_lock);
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INIT_LIST_HEAD(&hr_dev->dip_list);
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spin_lock_init(&hr_dev->dip_list_lock);
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ret = hns_roce_register_device(hr_dev);
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if (ret)
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@ -1573,14 +1573,10 @@ int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev)
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unsigned int reserved_from_bot;
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unsigned int i;
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qp_table->idx_table.spare_idx = kcalloc(hr_dev->caps.num_qps,
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sizeof(u32), GFP_KERNEL);
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if (!qp_table->idx_table.spare_idx)
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return -ENOMEM;
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mutex_init(&qp_table->scc_mutex);
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mutex_init(&qp_table->bank_mutex);
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xa_init(&hr_dev->qp_table_xa);
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xa_init(&qp_table->dip_xa);
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reserved_from_bot = hr_dev->caps.reserved_qps;
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@ -1605,7 +1601,7 @@ void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev)
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for (i = 0; i < HNS_ROCE_QP_BANK_NUM; i++)
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ida_destroy(&hr_dev->qp_table.bank[i].ida);
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xa_destroy(&hr_dev->qp_table.dip_xa);
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mutex_destroy(&hr_dev->qp_table.bank_mutex);
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mutex_destroy(&hr_dev->qp_table.scc_mutex);
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kfree(hr_dev->qp_table.idx_table.spare_idx);
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}
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