853 Commits

Author SHA1 Message Date
Geert Uytterhoeven
0d6256cb88 pinctrl: sh-pfc: r8a7791: Remove bogus marks from vin1_b_data18 group
The vin1_b_data18_mux[] arrays contains pin marks for the 2 LSB bits of
the color components.  The vin1_b_data18_pins[] array rightfully does
not include the corresponding pin numbers, as RGB18 is subset of RGB24,
containing only the 6 MSB bits of each component.

Fixes: 8e32c9671f84acd8 ("pinctrl: sh-pfc: r8a7791: Add VIN pins")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18 11:25:56 +01:00
Geert Uytterhoeven
884fa25fb6 pinctrl: sh-pfc: r8a7791: Remove bogus ctrl marks from qspi_data4_b group
The qspi_data4_b_mux[] array contains pin marks for the clock and chip
select pins.  The qspi_data4_b_pins[] array rightfully does not contain
the corresponding pin numbers, as the control pins are provided by a
separate group (qspi_ctrl_b).

Fixes: 2d0c386f135e4186 ("pinctrl: sh-pfc: r8a7791: Add QSPI pin groups")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18 11:25:56 +01:00
Geert Uytterhoeven
96bb2a6ab4 pinctrl: sh-pfc: r8a7740: Add missing LCD0 marks to lcd0_data24_1 group
The lcd0_data24_1_pins[] array contains the LCD0 D1[2-5] pin numbers,
but the lcd0_data24_1_mux[] array lacks the corresponding pin marks.

Fixes: 06c7dd866da70f6c ("sh-pfc: r8a7740: Add LCDC0 and LCDC1 pin groups and functions")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18 11:25:56 +01:00
Geert Uytterhoeven
1ebc589a77 pinctrl: sh-pfc: r8a7740: Add missing REF125CK pin to gether_gmii group
The gether_gmii_mux[] array contains the REF125CK pin mark, but the
gether_gmii_pins[] array lacks the corresponding pin number.

Fixes: bae11d30d0cafdc5 ("sh-pfc: r8a7740: Add GETHER pin groups and functions")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18 11:25:56 +01:00
Geert Uytterhoeven
117774fbe6 pinctrl: sh-pfc: r8a77990: Fix IOCTRL reg state after s2ram on R-Car E3
Due to an interaction with commit 9f2b76a2db3c4387 ("pinctrl: sh-pfc:
r8a77990: Add R8A774C0 PFC support"), the state of the I/O Control
Registers is saved/restored during s2ram on RZ/G2E, but not on R-Car E3.
Hence on R-Car E3, SDHI voltage state is lost after system resume.

Fix this by registering the I/O Control Registers on R-Car E3, too.

Fixes: 33847a71373cd6ae ("pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18 11:25:56 +01:00
Geert Uytterhoeven
f4caa6ee73 pinctrl: sh-pfc: r8a77990: Add support for pull-up only pins
The R-Car Gen3 HardWare Manual Errata for Rev. 1.00 (Jul 2, 2018) states
that the USB30_OVC pin supports pull-up only.  It has a bit assigned in
the pull-enable register (PUEN5), but not in the pull-up/down control
register (PUD5).

Add a check for this, to prevent configuring a prohibited setting.

Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Fixes: 83f6941a42a5e773 ("pinctrl: sh-pfc: r8a77990: Add bias pinconf support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-12-18 11:02:33 +01:00
Dmitry Shifrin
c21b73235e pinctrl: sh-pfc: r8a77980: Add QSPI pins, groups, and functions
Add the QSPI{0|1} pins/groups/functions to the R8A77980 PFC driver.

[Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/
SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to
be in the alphanumeric order, removed unneeded empty lines, renamed the
patch.]

Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-20 09:25:31 +01:00
Takeshi Kihara
b5ff38f15c pinctrl: sh-pfc: r8a77990: Add CAN FD pins, groups and functions
This patch adds CAN FD{0,1} pins, groups and functions to the R8A77990
SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
[geert: Move canfd from common to automotive]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19 11:56:35 +01:00
Takeshi Kihara
c1e5bd286f pinctrl: sh-pfc: r8a77990: Add CAN pins, groups and functions
This patch adds CAN{0,1} pins, groups and functions to the R8A77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19 11:56:35 +01:00
Takeshi Kihara
1b259dde9b pinctrl: sh-pfc: r8a77965: Add CAN FD pins, groups and functions
This patch adds CAN FD{0,1} pins, groups and functions to the R8A77965
SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19 11:56:35 +01:00
Takeshi Kihara
3a44d6a92e pinctrl: sh-pfc: r8a77965: Add CAN pins, groups and functions
This patch adds CAN{0,1} pins, groups and functions to the R8A77965 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19 11:56:35 +01:00
Takeshi Kihara
8d7bcad65e pinctrl: sh-pfc: r8a7796: Add I2C{0,3,5} pins, groups and functions
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC.

These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19 11:56:35 +01:00
Takeshi Kihara
e244ff6f91 pinctrl: sh-pfc: r8a7795-es1: Add I2C{0,3,5} pins, groups and functions
This patch adds I2C{0,3,5} pins, groups and functions to
the R8A7795 ES1.x SoC.

These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19 11:56:35 +01:00
Takeshi Kihara
100431b61d pinctrl: sh-pfc: r8a7795: Add I2C{0,3,5} pins, groups and functions
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 SoC.

These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19 11:56:35 +01:00
Ulrich Hecht
50d1ba1764 pinctrl: sh-pfc: Add physical pin multiplexing helper macros
Used by I2C controllers 0, 3 and 5 in R8A7795 and R8A7796 SoCs.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19 11:56:35 +01:00
Geert Uytterhoeven
341fe38975 pinctrl: sh-pfc: r8a77995: Remove unused PINMUX_IPSR_{MSEL2,PHYS}()
The PINMUX_IPSR_MSEL2() and PINMUX_IPSR_PHYS() macros are unused, and
will conflict with generic macros that are to be added.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-11-19 11:56:35 +01:00
Takeshi Kihara
5160063d56 pinctrl: sh-pfc: r8a77990: Add HSCIF pins, groups, and functions
This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to
the R8A77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-19 10:43:51 +01:00
Jacopo Mondi
60b7e5d98c pinctrl: sh-pfc: r8a77990: Add VIN[4|5] groups/functions
Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car E3.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13 11:17:46 +01:00
Jacopo Mondi
270b6eb715 pinctrl: sh-pfc: r8a77965: Add VIN[4|5] groups/functions
The VIN4 and VIN5 interfaces support parallel video input.
Add pin, mux and functions definitions for VIN4 and VIN5 for R-Car M3-N.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13 10:57:46 +01:00
Jacopo Mondi
10e78f03da pinctrl: sh-pfc: r8a7796: Fix VIN versioned groups
Versioned VIN groups can appear on different sets of pins. Using the
VIN_DATA_PIN_GROUP macro now supports proper naming of said groups
through an optional 'version' argument.

Use the 'version' argument for said macro to fix naming of versioned
groups for the R-Car M3-W R8A7796 SoC.

Fixes: a5c2949ff7bd ("pinctrl: sh-pfc: r8a7796: Deduplicate VIN4 pin definitions")
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13 10:52:33 +01:00
Jacopo Mondi
184844ccda pinctrl: sh-pfc: r8a7795: Fix VIN versioned groups
Versioned VIN groups can appear on different sets of pins. Using the
VIN_DATA_PIN_GROUP macro now supports proper naming of said groups
through an optional 'version' argument.

Use the 'version' argument for said macro to fix naming of versioned
groups for the R-Car H3 R8A7795 SoC.

Fixes: 9942a5b52990 ("pinctrl: sh-pfc: r8a7795: Deduplicate VIN4 pin definitions")
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13 10:52:28 +01:00
Jacopo Mondi
11c8f8df85 pinctrl: sh-pfc: r8a7792: Fix VIN versioned groups
Versioned VIN groups can appear on different sets of pins. Using the
VIN_DATA_PIN_GROUP macro now supports proper naming of said groups
through an optional 'version' argument.

Use the 'version' argument for said macro to fix naming of versioned
groups for the R-Car V2H R8A7792 SoC.

Fixes: 7dd74bb1f058 ("pinctrl: sh-pfc: r8a7792: Add VIN pin groups")
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13 10:52:22 +01:00
Jacopo Mondi
e889b29815 pinctrl: sh-pfc: Add optional arg to VIN_DATA_PIN_GROUP
VIN data groups may appear on different sets of pins, usually named
"vinX_data_[a|b]". The existing VIN_DATA_PIN_GROUP() does not support
appending the '_a' or '_b' suffix, leading to the definition of group
names not consistent with the ones defined using the SH_PFC_PIN_GROUP()
macro.

Fix this by making the VIN_DATA_PIN_GROUP macro a variadic one,
which accepts an optional 'version' argument.

Fixes: 423caa52534f ("pinctrl: sh-pfc: r8a779[01]: Move 'union vin_data' to shared header file")
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13 10:52:09 +01:00
Dmitry Shifrin
3ad8fbd83f pinctrl: sh-pfc: r8a77970: Add QSPI pins, groups, and functions
Add the QSPI{0|1} pins/groups/functions to the R8A77970 PFC driver.

[Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/
SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to
be in the alphanumeric order, removed unneeded empty lines, renamed the
patch.]

Signed-off-by: Dmitry Shifrin <dmitry.shifrin@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13 10:08:25 +01:00
Takeshi Kihara
33847a7137 pinctrl: sh-pfc: r8a77990: Add voltage switch operations for SDHI
This patch supports the {get,set}_io_voltage operations of SDHI.

This operates the IOCTRL30 register on the R8A77990 SoC and makes
1.8V/3.3V signal voltage switch possible.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13 10:08:25 +01:00
Takeshi Kihara
21ac0d58bb pinctrl: sh-pfc: r8a77990: Add SDHI pins, groups and functions
This patch adds SDHI{0,1,3} pins, groups and functions to the R8A77990
SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-13 10:08:25 +01:00
Fabrizio Castro
b06a8b4387 pinctrl: sh-pfc: r8a77470: Add SDHI support
Add SH_PFC_PIN_CFG_IO_VOLTAGE definition for the SDHI pins
capable of switching voltage, also add pin groups and functions
for SDHI0 and SDHI1. Please note that with the RZ/G1C only 1
bit of the POC Control Register is used to control each interface.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-06 09:20:26 +01:00
Geert Uytterhoeven
50f3f2d73e pinctrl: sh-pfc: Reduce kernel size for narrow VIN channels
Some VIN channels support less than 24 lanes.  As union vin_data always
consumes space for 24 lanes, this wastes memory.

Hence introduce new smaller unions vin_data12 and vin_data16, to
accommodate VIN channels with only 12 or 16 lanes.

This reduces the static pin controller driver size by 320 bytes for
R-Car V2H, and by 96 bytes for R-Car E2.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2018-11-06 09:20:26 +01:00
Takeshi Kihara
ccb44a8a5b pinctrl: sh-pfc: r8a77990: Add Audio SSI pins, groups and functions
This patch adds Audio SSI{0,1,2,3,4,5,6,7,8,9} pins, groups
and functions to the R8A77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: rebase]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-06 09:20:26 +01:00
Takeshi Kihara
4c833b2fa5 pinctrl: sh-pfc: r8a77990: Add Audio clock pins, groups and functions
This patch adds AUDIO_CLK{A,B,C}, AUDIO_CLKOUT, AUDIO_CLKOUT{1,2,3}
pins, groups and functions to the R8A77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[simon: rebase]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-06 09:20:26 +01:00
Fabrizio Castro
f743f017b7 pinctrl: sh-pfc: r8a77470: Add QSPI1 pin groups
Add QSPI1 pin groups and function to the RZ/G1C (a.k.a. R8A77470)
pinctrl driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-05 13:43:40 +01:00
Fabrizio Castro
610d662ac3 pinctrl: sh-pfc: r8a77470: Add VIN pin groups
Add VIN[01] pin groups and functions to the RZ/G1C (a.k.a.
R8A77470) pinctrl driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-05 13:43:38 +01:00
Fabrizio Castro
5c9258bca9 pinctrl: sh-pfc: r8a77470: Add DU1 pin groups
Add DU1 pin groups and function to the RZ/G1C (a.k.a. R8A77470)
pinctrl driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-05 13:43:36 +01:00
Fabrizio Castro
80ef7d0910 pinctrl: sh-pfc: r8a77470: Add remaining I2C pin groups
This patch adds I2C[0123] groups and functions to the RZ/G1C
(a.k.a. R8A77470) pinctrl driver.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-11-05 13:43:17 +01:00
Geert Uytterhoeven
ef26d96023 pinctrl: sh-pfc: r8a77990: Add INTC-EX pins, groups and function
Add pins, groups, and function for the Interrupt Controller for
External Devices (INTC-EX) on the R-Car E3 SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-10-02 12:16:47 +02:00
Geert Uytterhoeven
a97f340c0a pinctrl: sh-pfc: rcar: Rename automotive-only arrays to automotive
Renesas RZ/G SoCs are pin compatible with R-Car SoCs, but lack several
automotive-specific peripherals.

Currently pin groups and functions for automotive-specific peripherals
are grouped in arrays named after the automative SoC part numbers.
Rename them to "automotive" for clarity and consistency.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-28 09:49:15 +02:00
Fabrizio Castro
8faa0754ec pinctrl: sh-pfc: r8a77470: Add USB pin groups
Add USB[01] pin groups and functions to the R8A77470 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-20 17:11:25 +02:00
Fabrizio Castro
df9c71694f pinctrl: sh-pfc: r8a77470: Add SDHI2 pin groups
Add SDHI2 pin groups and functions to the R8A77470 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-20 17:11:25 +02:00
Fabrizio Castro
e5984d0576 pinctrl: sh-pfc: r8a77470: Add QSPI0 pin groups
Add QSPI0 pin groups and function to the R8A77470 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-20 17:11:25 +02:00
Fabrizio Castro
469c1e97dc pinctrl: sh-pfc: r8a77470: Add DU0 pin groups
Add DU0 pin groups and function to the R8A77470 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-20 17:11:25 +02:00
Fabrizio Castro
e34ebe5a6b pinctrl: sh-pfc: r8a77470: Add I2C4 pin groups
Add I2C4 pin groups and function to the R8A77470 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-20 17:11:25 +02:00
Fabrizio Castro
9f2b76a2db pinctrl: sh-pfc: r8a77990: Add R8A774C0 PFC support
Renesas RZ/G2E (a.k.a. r8a774c0) is pin compatible with R-Car
E3 (a.k.a. r8a77990), however it doesn't have several automotive
specific peripherals. Add a r8a77990 specific pin groups/functions
along with common pin groups/functions for supporting both r8a77990
and r8a774c0 SoCs.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-19 17:29:00 +02:00
Biju Das
d7097b97e9 pinctrl: sh-pfc: r8a7791: Add r8a7744 support
Renesas RZ/G1N (R8A7744) is pin compatible with R-Car M2-W/N (R8A7791/3)
and RZ/G1M.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-19 17:27:18 +02:00
Kuninori Morimoto
63b6d7e762 pinctrl: sh-pfc: Convert to SPDX identifiers
This patch updates license to use SPDX-License-Identifier
instead of verbose license text.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11 12:25:32 +02:00
Takeshi Kihara
2ef7a12f55 pinctrl: sh-pfc: r8a77995: Add MSIOF pins, groups and functions
This patch adds MSIOF{0,1,2,3} pins, groups and functions to R8A77995 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[ykaneko0929@gmail.com: fix the order of definitions]
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11 12:14:06 +02:00
Takeshi Kihara
0a7cad486f pinctrl: sh-pfc: r8a77990: Add MSIOF pins, groups and functions
This patch adds MSIOF{0,1,2,3} pins, groups and functions to
the R8A77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-09-11 12:12:59 +02:00
Laurent Pinchart
2ed03c835d pinctrl: sh-pfc: r8a77990: Add DU pins, groups and function
This patch adds DU pins, groups and function for the R8A77990 (E3) SoC.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-08-30 14:17:20 +02:00
Hoan Nguyen An
7a7dfc4770 pinctrl: sh-pfc: r8a77965: Add Audio SSI pin support
Add Audio SSI pin support for r8a77965.

Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-08-28 11:28:37 +02:00
Hoan Nguyen An
ada9a3d98f pinctrl: sh-pfc: r8a77965: Add Audio clock pin support
Add Audio clock pin support for r8a77965.

Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-08-28 11:28:37 +02:00
Biju Das
91d627a779 pinctrl: sh-pfc: r8a7796: Add R8A774A1 PFC support
Renesas RZ/G2M (r8a774a1) is pin compatible with R-Car M3-W (r8a7796),
however it doesn't have several automotive specific peripherals. Add
an r8a7796 specific pin groups/functions along with common pin
groups/functions for supporting both r8a7796 and r8a774a1 SoCs.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-08-28 11:28:37 +02:00